JPH0469428B2 - - Google Patents

Info

Publication number
JPH0469428B2
JPH0469428B2 JP58119329A JP11932983A JPH0469428B2 JP H0469428 B2 JPH0469428 B2 JP H0469428B2 JP 58119329 A JP58119329 A JP 58119329A JP 11932983 A JP11932983 A JP 11932983A JP H0469428 B2 JPH0469428 B2 JP H0469428B2
Authority
JP
Japan
Prior art keywords
conductor pattern
transparent
wiring board
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58119329A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6010735A (ja
Inventor
Tamio Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58119329A priority Critical patent/JPS6010735A/ja
Publication of JPS6010735A publication Critical patent/JPS6010735A/ja
Publication of JPH0469428B2 publication Critical patent/JPH0469428B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676—Single layer compositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Led Device Packages (AREA)
  • Light Receiving Elements (AREA)
  • Wire Bonding (AREA)
JP58119329A 1983-06-30 1983-06-30 半導体装置 Granted JPS6010735A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58119329A JPS6010735A (ja) 1983-06-30 1983-06-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58119329A JPS6010735A (ja) 1983-06-30 1983-06-30 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5254357A Division JP2597809B2 (ja) 1993-10-12 1993-10-12 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6010735A JPS6010735A (ja) 1985-01-19
JPH0469428B2 true JPH0469428B2 (https=) 1992-11-06

Family

ID=14758775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58119329A Granted JPS6010735A (ja) 1983-06-30 1983-06-30 半導体装置

Country Status (1)

Country Link
JP (1) JPS6010735A (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0224689D0 (en) * 2002-10-23 2002-12-04 Simage Oy Formation of contacts on semiconductor substrates
JP2005202382A (ja) * 2003-12-18 2005-07-28 Sumitomo Bakelite Co Ltd 光プリント回路基板、面実装型半導体パッケージ、及びマザーボード

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5838768B2 (ja) * 1975-12-08 1983-08-25 エプソン株式会社 エキシヨウヒヨウジソウチ
JPS5273693A (en) * 1975-12-16 1977-06-20 Seiko Epson Corp Display device
JPS5276051A (en) * 1975-12-22 1977-06-25 Seiko Epson Corp Liquid crystal indicating device
JPS5276877A (en) * 1975-12-22 1977-06-28 Seiko Epson Corp Semiconductor device
JPS5359398A (en) * 1976-11-09 1978-05-29 Seiko Epson Corp Liquid crystal display panel
JPS53104198A (en) * 1977-02-23 1978-09-11 Takagi Kogyo Kk Liquid crystal panel
JPS5552229A (en) * 1978-10-11 1980-04-16 Nec Corp Manufacture of semiconductor device
JPS5815959B2 (ja) * 1979-12-25 1983-03-28 アルプス電気株式会社 透明積層配線基板の製造方法

Also Published As

Publication number Publication date
JPS6010735A (ja) 1985-01-19

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