JPH0463659U - - Google Patents
Info
- Publication number
- JPH0463659U JPH0463659U JP10559190U JP10559190U JPH0463659U JP H0463659 U JPH0463659 U JP H0463659U JP 10559190 U JP10559190 U JP 10559190U JP 10559190 U JP10559190 U JP 10559190U JP H0463659 U JPH0463659 U JP H0463659U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- plan
- tie bars
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
第１図から第４図にかけては本考案に係る図面
であつて、第１図はリードフレームの１実施例の
平面図、第２図は第１図のものにＬＥＤ素子をダ
イボンデイング、ワイヤボンデイングした後、樹
脂をモールドした場合の平面図、第３図はカツト
するタイバー及びリード部をクロスハツチで示し
た平面図、第４図はタイバー及びリード部をカツ
トした平面図である。第５図と第６図にかけては
従来技術に係る図面であつて、第５図は従来のリ
ードフレームの平面図、第６図は完成したＬＥＤ
の平面図である。
Ｔ１，Ｔ２，Ｔ３……タイバー、Ｌ１，Ｌ２，
Ｌ３，Ｌ４……リード部。
1 to 4 are drawings related to the present invention, in which FIG. 1 is a plan view of one embodiment of a lead frame, and FIG. 2 is a diagram showing an LED element attached to the one shown in FIG. 1 by die bonding and wire bonding. After that, the resin is molded. FIG. 3 is a plan view showing the tie bars and lead portions to be cut with cross hatches, and FIG. 4 is a plan view showing the tie bars and lead portions being cut. 5 and 6 are drawings related to the prior art, where FIG. 5 is a plan view of a conventional lead frame, and FIG. 6 is a completed LED.
FIG. T1, T2, T3...Tie bar, L1, L2,
L3, L4...Lead part.
Claims (1)
ー及びリード部を具備せしめたことを特徴とする
ＬＥＤ用リードフレーム。 A lead frame for an LED, characterized in that a plurality of tie bars and lead parts are provided on the lead frame for one element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10559190U JPH0463659U (en) | 1990-10-05 | 1990-10-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10559190U JPH0463659U (en) | 1990-10-05 | 1990-10-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0463659U true JPH0463659U (en) | 1992-05-29 |
Family
ID=31851331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10559190U Pending JPH0463659U (en) | 1990-10-05 | 1990-10-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0463659U (en) |
-
1990
- 1990-10-05 JP JP10559190U patent/JPH0463659U/ja active Pending