JPS63170962U - - Google Patents
Info
- Publication number
- JPS63170962U JPS63170962U JP6322687U JP6322687U JPS63170962U JP S63170962 U JPS63170962 U JP S63170962U JP 6322687 U JP6322687 U JP 6322687U JP 6322687 U JP6322687 U JP 6322687U JP S63170962 U JPS63170962 U JP S63170962U
- Authority
- JP
- Japan
- Prior art keywords
- guide hole
- lead frame
- tie bar
- molding
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000465 moulding Methods 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Punching Or Piercing (AREA)
Description
第１図は、本考案に係るリードフレームの要部
切欠拡大図、第２図は、従来のリードフレームの
平面図である。
１１……リード線、１２……タイバー、１３…
…パンチ案内孔。
FIG. 1 is an enlarged cutaway view of a main part of a lead frame according to the present invention, and FIG. 2 is a plan view of a conventional lead frame. 11... Lead wire, 12... Tie bar, 13...
...Punch guide hole.
Claims (1)
ルド後、切断除去される部分に、パンチ案内孔を
穿設したことを特徴とするリードフレーム。 A lead frame characterized in that a punch guide hole is formed in a portion of a tie bar connecting adjacent lead wires that is cut and removed after molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6322687U JPS63170962U (en) | 1987-04-24 | 1987-04-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6322687U JPS63170962U (en) | 1987-04-24 | 1987-04-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63170962U true JPS63170962U (en) | 1988-11-07 |
Family
ID=30898255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6322687U Pending JPS63170962U (en) | 1987-04-24 | 1987-04-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63170962U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170048466A (en) * | 2014-10-03 | 2017-05-08 | 미쓰비시덴키 가부시키가이샤 | Lead frame and method for manufacturing semiconductor dece |
-
1987
- 1987-04-24 JP JP6322687U patent/JPS63170962U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170048466A (en) * | 2014-10-03 | 2017-05-08 | 미쓰비시덴키 가부시키가이샤 | Lead frame and method for manufacturing semiconductor dece |
| US10541193B2 (en) | 2014-10-03 | 2020-01-21 | Mitsubishi Electric Corporation | Lead frame and method for manufacturing semiconductor device |
| US11387173B2 (en) | 2014-10-03 | 2022-07-12 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |