JPH0455531B2 - - Google Patents

Info

Publication number
JPH0455531B2
JPH0455531B2 JP61314164A JP31416486A JPH0455531B2 JP H0455531 B2 JPH0455531 B2 JP H0455531B2 JP 61314164 A JP61314164 A JP 61314164A JP 31416486 A JP31416486 A JP 31416486A JP H0455531 B2 JPH0455531 B2 JP H0455531B2
Authority
JP
Japan
Prior art keywords
wire
amorphous alloy
semiconductor device
lead wire
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61314164A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63168031A (ja
Inventor
Toshinori Kogashiwa
Yasuhiko Yoshinaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Original Assignee
Tanaka Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Denshi Kogyo KK filed Critical Tanaka Denshi Kogyo KK
Priority to JP61314164A priority Critical patent/JPS63168031A/ja
Publication of JPS63168031A publication Critical patent/JPS63168031A/ja
Publication of JPH0455531B2 publication Critical patent/JPH0455531B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP61314164A 1986-12-29 1986-12-29 半導体装置 Granted JPS63168031A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61314164A JPS63168031A (ja) 1986-12-29 1986-12-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61314164A JPS63168031A (ja) 1986-12-29 1986-12-29 半導体装置

Publications (2)

Publication Number Publication Date
JPS63168031A JPS63168031A (ja) 1988-07-12
JPH0455531B2 true JPH0455531B2 (cs) 1992-09-03

Family

ID=18050012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61314164A Granted JPS63168031A (ja) 1986-12-29 1986-12-29 半導体装置

Country Status (1)

Country Link
JP (1) JPS63168031A (cs)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2201545B (en) * 1987-01-30 1991-09-11 Tanaka Electronics Ind Method for connecting semiconductor material
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications

Also Published As

Publication number Publication date
JPS63168031A (ja) 1988-07-12

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