JPH0455531B2 - - Google Patents
Info
- Publication number
- JPH0455531B2 JPH0455531B2 JP61314164A JP31416486A JPH0455531B2 JP H0455531 B2 JPH0455531 B2 JP H0455531B2 JP 61314164 A JP61314164 A JP 61314164A JP 31416486 A JP31416486 A JP 31416486A JP H0455531 B2 JPH0455531 B2 JP H0455531B2
- Authority
- JP
- Japan
- Prior art keywords
- wire
- amorphous alloy
- semiconductor device
- lead wire
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 229910000808 amorphous metal alloy Inorganic materials 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 22
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000002178 crystalline material Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000007747 plating Methods 0.000 description 6
- 239000010931 gold Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000004017 vitrification Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229920006280 packaging film Polymers 0.000 description 1
- 239000012785 packaging film Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は各種コンピユーターに使用される半導
体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device used in various computers.
［従来の技術とその問題点］
パツケージ等の基板上面に配設されたリード線
と半導体材料との電気的接続の方法には、いわゆ
るフリツプチツプ方式というものがある。[Prior Art and its Problems] There is a so-called flip-chip method as a method for electrically connecting lead wires disposed on the upper surface of a substrate such as a package and a semiconductor material.
これは、ワイヤレスボンデイングのひとつであ
り、半導体材料の表面の配設された内部配線と基
板上面に配設されたリード線とをバンプ電極又は
半田等の接合材を介して溶着することにより、電
気的接続と半導体材料の取り付けとを同時に行う
ものである。 This is a type of wireless bonding, in which internal wiring arranged on the surface of a semiconductor material and lead wires arranged on the top surface of a substrate are welded together via bump electrodes or a bonding material such as solder. This method simultaneously performs physical connections and attaches semiconductor materials.
ところがこれは、バンプ電極を形成するために
半導体材料表面の内部配線を被覆するフアイナル
パツシペーシヨン膜に穿孔部を開穿すると共に、
基板上面のリード線上には金又は半田等を被着し
て下地金属を形成しなければならないため接続工
程が複雑でかつ製造コストが高くなるという問題
があつた。 However, in order to form bump electrodes, a perforation is made in the final packaging film that covers the internal wiring on the surface of the semiconductor material, and
Since it is necessary to form a base metal by depositing gold or solder on the lead wires on the upper surface of the substrate, there are problems in that the connection process is complicated and the manufacturing cost is high.
［発明が解決しようとする技術的課題］
以上の問題を解決しようとする本発明の技術的
課題は、簡潔でかつ安価に製造できる半導体装置
を提供することである。[Technical Problem to be Solved by the Invention] A technical problem to be solved by the present invention to solve the above problems is to provide a semiconductor device that is simple and can be manufactured at low cost.
［技術的課題を達成するための技術的手段］
以上の技術的課題を達成するための本発明の第
１の技術的手段は半導体装置本体における半導体
材料を、アモルフアス合金又は部分的に結晶質を
含むアモルフアス合金によりなるワイヤから供給
されるバンプ電極を介してリード線に電気的に接
続して形成することであり、第２の技術的手段は
半導体装置本体における半導体材料を、アモルフ
アス合金又は部分的に結晶質を含むアモルフアス
合金よりなる芯線に、他の金属をコーテイングし
て形成したワイヤから供給されるバンプ電極を介
してリード線に電気的に接続して形成することで
ある。[Technical Means for Achieving the Technical Problem] The first technical means of the present invention for achieving the above technical problem is to use an amorphous alloy or a partially crystalline semiconductor material in the semiconductor device main body. The second technical means is to electrically connect the semiconductor material in the semiconductor device body to a lead wire through a bump electrode supplied from a wire made of an amorphous alloy containing amorphous alloy. A core wire made of an amorphous alloy containing crystalline material is electrically connected to a lead wire via a bump electrode supplied from a wire formed by coating another metal.
［発明の効果］
本発明は以上の様な構成にしたことにより下記
の効果を有する。[Effects of the Invention] The present invention has the following effects by having the above configuration.
半導体装置本体における半導体材料を、アモ
ルフアス合金又は部分的に結晶質を含むアモル
フアス合金よりなるワイヤから供給されるバン
プ電極を介してリード線へ接続したことによ
り、ボンダによるボールの供給が可能となり精
度の高い、かつ低コストの半導体装置を提供す
ることができる。 By connecting the semiconductor material in the semiconductor device main body to the lead wire via a bump electrode supplied from a wire made of an amorphous alloy or an amorphous alloy partially containing crystalline materials, it is possible to supply balls by a bonder, which improves accuracy. A high cost and low cost semiconductor device can be provided.
ワイヤーがアモルフアス合金の主要元素でコ
ーテイングされていることにより、ワイヤー先
端に形成されるボールが軟らかくかつその形状
が安定しているため接着強度が大きく、キヤピ
ラリによる変形が容易に行なえる。 Since the wire is coated with the main element of the amorphous alloy, the ball formed at the tip of the wire is soft and stable in shape, resulting in high adhesive strength and easy deformation by a capillary.
［実施例］
以下、本説明の一実施例を図面に基づいて説明
する。[Example] An example of the present description will be described below based on the drawings.
本実施例に使用される半導体装置本体Ａは第１
図に示す如く、いわゆるリードレスチツプキヤリ
ア（LCC）型であり、基板１がアルミナ又はガ
ラスエポキシ樹脂で形成され、該基板１の上面に
はタングステンメタライズ又は銅からなるリード
線２が配設されると共に基板１中央部には半導体
材料３が搭載されてバンプ電極７ａを介して前記
リード線２と電気的に接続されている。 The semiconductor device main body A used in this example is the first
As shown in the figure, it is a so-called leadless chip carrier (LCC) type, and a substrate 1 is made of alumina or glass epoxy resin, and lead wires 2 made of tungsten metallization or copper are disposed on the upper surface of the substrate 1. At the same time, a semiconductor material 3 is mounted on the center portion of the substrate 1 and is electrically connected to the lead wire 2 via a bump electrode 7a.
さらに、該半導体材料３とリード線２の一部と
がシリコン等の保護樹脂で封止して形成されてい
る。 Further, the semiconductor material 3 and a part of the lead wire 2 are sealed with a protective resin such as silicon.
また、第２図〜第５図は前記半導体装置Ａにお
いて、本発明の半導体材料の接続方法を示した断
面図である。 Moreover, FIGS. 2 to 5 are cross-sectional views showing the method of connecting semiconductor materials of the present invention in the semiconductor device A.
第２図はワイヤボンダのキヤピラリ４に挿通さ
れているアモルフアス合金のワイヤー５であり、
その先端を電気トーチ６で加熱溶融するとボール
７が形成されるが、該ボール７はガラス化温度を
越えて結晶質となつており、ボール７の根本部の
アモルフアス相はガラス化温度より低温域であつ
て構造緩和現象の領域となつている。 Figure 2 shows an amorphous alloy wire 5 inserted into a capillary 4 of a wire bonder.
When the tip is heated and melted with an electric torch 6, a ball 7 is formed, but the ball 7 has exceeded the vitrification temperature and has become crystalline, and the amorphous phase at the root of the ball 7 is in a temperature range below the vitrification temperature. This is the area of structural relaxation phenomena.
上記アモルフアス合金は常温において引張強度
及び圧縮強度が大きく強靭性を有するが前記構造
緩和現象の領域においては脆化し切断されやすい
状態となる。 The amorphous alloy has high tensile strength and compressive strength at room temperature and is strong, but in the region of the structural relaxation phenomenon, it becomes brittle and easily breaks.
上記要求を満たすために前記アモルフアス合金
は遷移金属であるCu，Ag，Au，Hi，Pd，Pt，
Co，Rh，Ir，Fe，Mn，Cr，Mo，Ｗ，Re，Ｖ，
Nb，Ta，Ti，Zr，Hfの内１種又は２種以上を
含有し、かつ半金属、半導体元素であるＢ，Ｃ，
AI，Si，Ga，Ge，In，Sn，Pb、及び非金属元
素であるＰ，Ｓ，Sb，Biの１種又は２種以上を
５〜30原子％、好ましくは10〜20原子％配合させ
た組成とする。 In order to meet the above requirements, the amorphous alloy is made of transition metals such as Cu, Ag, Au, Hi, Pd, Pt,
Co, Rh, Ir, Fe, Mn, Cr, Mo, W, Re, V,
B, C, which contains one or more of Nb, Ta, Ti, Zr, Hf, and is a semimetal or semiconductor element;
5 to 30 atom%, preferably 10 to 20 atom% of one or more of AI, Si, Ga, Ge, In, Sn, Pb, and nonmetallic elements P, S, Sb, and Bi are blended. The composition is as follows.
次に第３図及び第４図に示す如く、キヤピラリ
４を下降させてアモルフアス合金の細いワイヤー
５先端に形成されたボール７を配線であるリード
線２に付着させた状態でキヤピラリ４を引き上げ
ることにより、ボール７の根本部で細いワイヤー
５から切断されリード線２上にボール７が供給さ
れてバンプ電極７ａが形成される。 Next, as shown in FIGS. 3 and 4, the capillary 4 is lowered and the ball 7 formed at the tip of the thin amorphous alloy wire 5 is attached to the lead wire 2, which is the wiring, and then the capillary 4 is pulled up. As a result, the ball 7 is cut from the thin wire 5 at the root portion thereof, and the ball 7 is supplied onto the lead wire 2 to form a bump electrode 7a.
以上の様な方法により基板１上面に配線された
リード線２全線にバンプ電極７ａが連続的に形成
される。 By the method described above, bump electrodes 7a are continuously formed on all the lead wires 2 wired on the upper surface of the substrate 1.
そして、第５図に示す如くこれらリード線２上
面に供給し付着されたバンプ電極７ａを半導体材
料３表面に配設された内部配線３ａに接着させる
ことにより、該リード線２と内部配線３ａとが電
気的に接続されると共に、該半導体材料３が取り
付けられるものである。 Then, as shown in FIG. 5, the bump electrodes 7a supplied and attached to the top surface of these lead wires 2 are bonded to the internal wiring 3a disposed on the surface of the semiconductor material 3, thereby connecting the lead wires 2 and the internal wiring 3a. are electrically connected to each other, and the semiconductor material 3 is attached thereto.
また第６図〜第９図は第２発明における半導体
材料の接続方法を示した断面図である。 Further, FIGS. 6 to 9 are cross-sectional views showing a method for connecting semiconductor materials in the second invention.
第１０図における５′は、アモルフアス合金よ
りなる極細芯線５′ａの表面にその主要金属層
５′ｂをコーテイングしたワイヤーである。 5' in FIG. 10 is a wire in which the surface of an ultrafine core wire 5'a made of an amorphous alloy is coated with its main metal layer 5'b.
該ワイヤー５′はアモルフアス合金で形成した
極細芯線５′ａに電気メツキ方により、その主要
元素のメツキ、例えばアモルフアス合金がPd基
合金の場合はPdメツキ、Au基合金の場合はAuメ
ツキ等を施してメツキワイヤ５′を形成する。そ
して、該メツキワイヤ５′に引き抜き加工を施し
て同径のものを形成する。 The wire 5' is formed by electroplating an ultra-fine core wire 5'a made of an amorphous amorphous alloy, with plating of its main element, for example, Pd plating if the amorphous amorphous alloy is a Pd-based alloy, Au plating if it is an Au-based alloy, etc. Then, a plating wire 5' is formed. Then, the plating wire 5' is subjected to a drawing process to form a wire having the same diameter.
第６図はワイヤボンダのキヤピラリ４に挿通さ
れている前記メツキワイヤ５′を示したものであ
り、第６図〜第９図に示す如く、本発明の半導体
装置における半導体材の接続は前述の如く第１発
明と同じ接続方法により接続される。 FIG. 6 shows the plated wire 5' inserted into the capillary 4 of the wire bonder. As shown in FIGS. 6 to 9, the connection of semiconductor materials in the semiconductor device of the present invention is performed as described above. The connection is made using the same connection method as in the first invention.
さらに、本発明におけるアモルフアス合金も第
１発明と同じ組成である。 Furthermore, the amorphous alloy according to the present invention also has the same composition as the first invention.
第１図は半導体装置の断面図、第２図〜第９図
は半導体装置における半導体材料の接続方法を示
す断面図、第１０図はメツキワイヤの拡大断面図
である。
尚、図中、Ａ……半導体装置本体、２……リー
ド線、３……半導体材料、５，５′……ワイヤ、
５′ａ……芯線、５′ｂ……他の金属のコーテイン
グ層、を夫々示す。
FIG. 1 is a sectional view of a semiconductor device, FIGS. 2 to 9 are sectional views showing a method of connecting semiconductor materials in a semiconductor device, and FIG. 10 is an enlarged sectional view of a plating wire. In the figure, A...semiconductor device body, 2... lead wire, 3... semiconductor material, 5, 5'... wire,
5'a... core wire, 5'b... other metal coating layer, respectively.
Claims (1)
ルフアス合金又は部分的に結晶質を含むアモルフ
アス合金によりなるワイヤから供給されるバンプ
電極を介してリード線に電気的に接続して形成し
た半導体装置。 ２ 半導体装置本体における半導体材料を、アモ
ルフアス合金又は部分的に結晶質を含むアモルフ
アス合金よりなる芯線に、他の金属をコーテイン
グして形成したワイヤから供給されるバンプ電極
を介してリード線に電気的に接続して形成した半
導体装置。 ３ 前記他の金属がアモルフアス合金の主要元素
である特許請求の範囲第２項記載の半導体装置。[Claims] 1. A semiconductor material in a semiconductor device main body is electrically connected to a lead wire via a bump electrode supplied from a wire made of an amorphous alloy or an amorphous alloy partially containing crystalline material. Semiconductor equipment. 2 The semiconductor material in the semiconductor device main body is electrically connected to the lead wire through a bump electrode supplied from a wire formed by coating a core wire made of an amorphous alloy or an amorphous alloy partially containing crystalline with another metal. A semiconductor device formed by connecting to. 3. The semiconductor device according to claim 2, wherein the other metal is a main element of an amorphous alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61314164A JPS63168031A (en) | 1986-12-29 | 1986-12-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61314164A JPS63168031A (en) | 1986-12-29 | 1986-12-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63168031A JPS63168031A (en) | 1988-07-12 |
| JPH0455531B2 true JPH0455531B2 (en) | 1992-09-03 |
Family
ID=18050012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61314164A Granted JPS63168031A (en) | 1986-12-29 | 1986-12-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63168031A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2201545B (en) * | 1987-01-30 | 1991-09-11 | Tanaka Electronics Ind | Method for connecting semiconductor material |
| JP3407275B2 (en) | 1998-10-28 | 2003-05-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Bump and method of forming the same |
| US7271497B2 (en) | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
-
1986
- 1986-12-29 JP JP61314164A patent/JPS63168031A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63168031A (en) | 1988-07-12 |
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