JPH0465534B2 - - Google Patents
Info
- Publication number
- JPH0465534B2 JPH0465534B2 JP62130595A JP13059587A JPH0465534B2 JP H0465534 B2 JPH0465534 B2 JP H0465534B2 JP 62130595 A JP62130595 A JP 62130595A JP 13059587 A JP13059587 A JP 13059587A JP H0465534 B2 JPH0465534 B2 JP H0465534B2
- Authority
- JP
- Japan
- Prior art keywords
- ball
- wire
- alloy wire
- alloy
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000956 alloy Substances 0.000 claims description 40
- 229910045601 alloy Inorganic materials 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 32
- 229910052738 indium Inorganic materials 0.000 claims description 10
- 238000007712 rapid solidification Methods 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 10
- 229910052745 lead Inorganic materials 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910052763 palladium Inorganic materials 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000000654 additive Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 230000000996 additive effect Effects 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- 229910052790 beryllium Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052793 cadmium Inorganic materials 0.000 claims description 3
- 229910052791 calcium Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 229910052748 manganese Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 229910052711 selenium Inorganic materials 0.000 claims description 3
- 229910052714 tellurium Inorganic materials 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 8
- 239000006104 solid solution Substances 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 239000010953 base metal Substances 0.000 description 5
- 238000011156 evaluation Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910020658 PbSn Inorganic materials 0.000 description 2
- 101150071746 Pbsn gene Proteins 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000005096 rolling process Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 238000009987 spinning Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000005482 strain hardening Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000005491 wire drawing Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
（産業上の利用分野）
本発明は半導体材料の接続方法、詳しくはワイ
ヤレスボンデイング法、特にフリツプチツプボン
デイング法またはテープキヤリアボンデイング法
により半導体チツプを基板にボンデイングする際
の接続方法及びそれに用いる接続材料に関する。
（従来技術とその問題点）
従来、ワイヤボンダを用いてバンプ電極を形成
する方法には特開昭61−43438号公報があるが、
この方法では亜鈴形状のバンプ電極をボンデイン
グした後に、ワイヤーを切断するために電気トー
チ等で切断する工程を必要としている。
又、現在バンプ電極材料としては、
PbSn5wt%，PbSn40wt%などを用いているが、通
常の鋳造法により作製した前記合金をダイス引き
によによりワイヤー化した合金ワイヤーを、ワイ
ヤーボンダを用いて接続したところ、ワイヤーが
ボールの根本部ではなくワイヤー部の途中で切断
することが多く、また長さのバラツキも大きくバ
ンプ電極としての使用に不適であることが判明し
た。
上記合金ワイヤーがワイヤー部で切断するの
は、ボール根本部の引張り強度がワイヤー部の引
張り強度に較べて十分小さくないことが原因して
いる。
（発明が解決しようとする技術的課題）
本発明は叙上従来問題点を解決して、ワイヤー
ボンダを用いたバンプ電極の形成を可能にし、作
業性の高い半導体の接続方法を提供するとともに
該方法に用いる接続材料を提供することを目的と
する。
（技術的課題を達成するための技術的手段）
斯る本発明の技術的手段は、Pb，Sn，Inの何
れか１つを主要元素として、かつ急冷凝固法によ
り作製された細い合金ワイヤーの先端を加熱して
ボールを形成し該ボールを配線上面又は半導体材
料上面に接着させた状態で合金ワイヤーを引張る
ことにより、ボールがその根本部から切断されて
配線上面又は半導体材料上面にバンプ電極を形成
せしめ、そのバンプ電極を介して半導体材料を接
続する半導体材料の接続方法に係り、また本発明
の接続材料は、Pb，Sn，Inの何れか１つを主要
元素とし、それに添加元素を配合した合金を急冷
凝固法により細いワイヤー状に作製してなること
を特徴とする。
（作用）
本発明によれば、急冷凝固法により作製された
合金ワイヤーは、多くの格子欠陥の導入，結晶粒
の微細化，非平衡相の生成，元素相互間の強制固
溶を有する組織状態となつて引張り強度を著しく
高める。
そして、上記合金ワイヤーの先端を加熱してボ
ールを形成したこときに、該ボールの根本部にお
いて、非平衡相が消失し、元素相互間の強制固溶
が解放し、格子欠陥が解放し、さらに結晶粒が粗
大化するなどの現象が生じてボール根本部の引張
り強度を減少せしめ、該部分の降伏，破断が起り
易い状態ならしめる。
従つて、上記ワイヤーを引張ることによつてボ
ールがその根本部から切断され、半導体材料上面
又は配線上面にワイヤーから切離してなるボール
によりバンプ電極を形成する。
（実施例）
以下、本発明の実施例を図面により説明する。
〔実施例 〕
本実施例で使用する半導体装置Ａは第１１図に
示す如く、所謂フリツプチツプボンデイング型で
あり、基板１がアルミナ又はガラスエポキシ樹脂
等絶縁性樹脂で形成され、該基板１の上面には
Cu又はCr・Cu又はPt又はPd又はAg又はPd・Ag
又はAu又はAl又はNi等の導電性材料からなる配
線２が配線されると共に基板１中央部には半導体
材料としてのチツプ３が搭載されてバンプ電極７
ａを介して前記配線２と電気的に接続されてい
る。
さらに、前記半導体チツプ３と配線２の一部と
がシリコン等の保護樹脂で封止して形成されてい
る。
また、第１図〜第５図は前記半導体装置Ａにお
いて、本発明の半導体材料の接続方法を示した断
面図である。
第１図はワイヤボンダのキヤピラリ４に挿通さ
れている接続材料としての合金ワイヤー５を示
し、この合金ワイヤーの先端を電気トーチ６で加
熱することによつてボール７を形成する。合金ワ
イヤー５は半田材料、すなわちPb，Sn，Inの何
れか１つを主要元素とし、それに添加元素を配合
せしめた合金であり、かつ急冷凝固法により作製
された細線である。すなわち急冷凝固法として、
従来知られた液中紡糸法により直接にワイヤーを
成形するか、あるいは単ロール法により得られた
合金材料を冷間プレスし、さらに押出し成形して
ワイヤーを成形するなどの方法による。そして、
得られたワイヤーに線引き加工を施して所定の細
線径とし前記合金ワイヤー５を作製する。
合金ワイヤー５の添加元素としては、Be，Ｂ，
Ｃ，Mg，Al，Si，Ｐ，Ca，Ti，Ｖ，Cr，Mn，
Fe，Co，Ni，Cu，Zn，Ga，Ge，Se，Zr，Nb，
Mo，Pd，Ag，Cd，Sb，Te，Ir，Pt，Au，Tl，
Bi中の１種又は２種以上を配合せしめ、また主
要元素Pb，Sn，Inをそれを含まない主要元素中
に添加することもよい。
上記合金ワイヤー５は前記急冷処理によつて、
多くの格子欠陥が導入され、結晶粒が微細化し、
非平衡相が生成し、元素相互間に強制固溶に生じ
た組織状態にあり、さらに線引き加工によつて、
加工硬化に伴う格子欠陥が導入され、添加元素に
よつて固溶硬化した組織状態にある。
次に第２図及び第３図に示す如く、キヤピラリ
４を下降させて合金ワイヤー５先端に形成された
ボール７を配線２に付着させた状態でキヤピラリ
４を引き上げることにより、ボール７の根本部で
合金ワイヤー５から切断され配線２上にボール７
が供給されてバンプ電極７ａが形成される。
そして、この様な方法により基板１上面の配線
２全線にバンプ電極７ａが連続的に形成される。
上記合金ワイヤー５の切断は、ボール７を加熱
形成した際に、ボール７の根本部において、前記
非平衡相が消失し、元素相互間の強制固溶が解放
し、格子欠陥が解放し、結晶粒が粗大化した組織
状態となつているため、その部分の引張り強度が
減少し、キヤピラリ４により合金ワイヤー５を引
き上げるだけでボール７がその根本部で降伏，破
断することによつて起こる。
次に、第４図に示す如くこれら配線２上面に供
給し付着されたバンプ電極７ａを半導体チツプ３
表面に配設された電極３ａに接着させることによ
り、該配線２と電極３ａとが電気的に接続される
と共に該半導体チツプ３が取り付けられる。
又、第５図に示す如く、前記配線２とバンプ電
極７ａまたはバンプ電極７ａと半導体チツプ表面
の電極３ａとを電気的に低抵抗で、機械的には強
固に接合する為には、それらの材料と合金を形成
し易い下地金属層３ｂ，３ｃが蒸着法又はスパツ
タリング法又はメツキ法等により形成される。例
えば、半導体チツプの電極３ａの材料がAlなら
ば下地金属層３ｂにはCr又はTi又はCu又はNi又
はPd又はAg又はPt又はAu等を用いた単層又は
積層界面を形成する。又、実施例ではバンプ電極
７ａを配線２上に形成する為にボール７を配線２
上に付着させたが、一方バンプ電極７ａを半導体
チツプ３の電極３ａ上に形成する為にボール７を
電極３ａ上に付着させることも可能である。
〔実施例 〕
本実施例で使用する半導体装置Ｂは、第１２図
に示す如く、所謂テープキヤリアボンデイング型
であり、半導体材料としてのチツプ３の電極３ａ
上にバンプ電極７ａを形成し、これにフイルムリ
ード１０を接合せしめ、基板９上の配線８と前記
フイルムリード１０とを接合したものである。
又、第６図〜第１０図は前記半導体装置Ｂにお
いて、本発明の半導体材料の接続方法を示した断
面図である。
第６図はワイヤボンダのキヤピラリ４に挿通さ
れている接続材料としての合金ワイヤー５を示
し、この合金ワイヤーの先端を電気トーチ６で加
熱することによつてボール７を形成する。合金ワ
イヤー５は半田材料、すなわちPb，Sn，Inの何
れか１つを主要元素とし、それに添加元素を配合
せしめた合金であり、かつ急冷凝固法により作製
された細線である。すなわち急冷凝固法として
は、従来知られた液中紡糸法により直接にワイヤ
ーを成形するか、あるいは単ロール法により得ら
れた合金材料を冷間プレスし、さらに押出し成形
してワイヤーを成形するなどの方法による。そし
て、得られたワイヤーに線引き加工を施して所定
の細線径とし前記合金ワイヤー５を作製する。
合金ワイヤー５の添加元素としては、Be，Ｂ，
Ｃ，Mg，Al，Si，Ｐ，Ca，Ti，Ｖ，Cr，Mn，
Fe，Co，Ni，Cu，Zn，Ga，Ge，Se，Zr，Nb，
Mo，Pd，Ag，Cd，Sb，Te，Ir，Pt，Au，Tl，
Bi中の１種又は２種以上を配合せしめ、また主
要元素Pb，Sn，Inをそれを含まない主要元素中
に添加することもよい。
上記合金ワイヤー５は前記急冷処理によつて、
多くの格子欠陥が導入され、結晶粒が微細化し、
非平衡相が生成し、元素相互間に強制固溶が生じ
た組織状態にあり、さらに線引き加工によつて、
加工硬化に伴う格子欠陥が導入され、添加元素に
よつて固溶硬化した組織状態にある。
次に第７図及び第８図に示す如く、キヤピラリ
４を下降させて合金ワイヤー５先端に形成された
ボール７をフイルムリード１０に付着させた状態
でキヤピラリ４を引き上げることにより、ボール
７の根本部で合金ワイヤー５から切断されフイル
ムリード１０上にボール７が供給されてバンプ電
極７ａが形成される。
そして、この様な方法によりフイルムリード１
０全線にバンプ電極７ａが連続的に形成される。
上記合金ワイヤー５の切断は、ボール７を加熱
形成した際に、ボール７の根本部において、前記
非平衡相が消失し、元素相互間の強制固溶が解放
し、格子欠陥が解放し、結晶粒が粗大化した組織
状態となつているため、その部分の引張り強度が
減少し、キヤピラリ４により合金ワイヤー５を引
き上げるだけでボール７がその根本部で降伏，破
断することによつて起こる。
次に、第９図に示す如くこれらフイルムリード
１０上面に供給し付着されたバンプ電極７ａを半
導体チツプ３表面に配設された電極３ａに接着さ
せることにより、該フイルムリード１０と電極３
ａとが電気的に接続されると共に該半導体チツプ
３が取り付けられる。
又、第１０図に示す如く、前記フイルムリード
１０とバンプ電極７ａまたはバンプ電極７ａと半
導体チツプ表面の電極３ａとを電気的に低抵抗
で、機械的には強固に接合する為には、それらの
材料と合金を形成し易い下地金属層３ｂ，３ｃが
蒸着法又はスパツタリング法又はメツキ法等によ
り形成される。例えば、半導体チツプの電極３ａ
の材料がAlならば下地金属層３ｂにはCr又はTi
又はCu又はNi又はPd又はAg又はPt又はAu等を
用いた単層又は積層界面を形成する。又、実施例
ではバンプ電極７ａをフイルムリード１０上に形
成する為にボール７をフイルムリード１０上に付
着させたが、一方バンプ電極７ａを半導体チツプ
３の電極３ａ上に形成する為にボール７を電極３
ａ上に付着させることも可能である。
以下に、本発明の合金ワイヤー５の種類、加工
性，ボール形成能，引張り強度，伸び，ボール硬
さ及びボール根本部における切断の可・不可を、
従来鋳造法により作製された比較品の場合と共に
示す。
尚、本発明合金ワイヤーにおける急冷凝固時の
冷却速度は103〜105℃／secであり、本発明実施
品及び比較品のワイヤーは何れも線径60um〓に作
製したものを試料とした。
上記試料の特性中、加工性とは、60um〓まで熱
処理無しで伸線加工が可能か否かを次の２段階で
評価したものである。すなわち評価が○印は加工
が可能であり、評価が×印は断線が多い等加工性
に難点があつたものである。
又、ボール形成能とは、各試料をセラミツクス
製のキヤピラリに通し、アルゴンガスに5vol％水
素ガスを加えたガス噴出下で、試料の先端近くに
設けた電極と試料との間のアーク放電によりボー
ルを形成させ、そのボールの形成状況を次の２段
階で評価したものである。すなわち評価○印は真
球度が良く、表面形伏の滑らかなボールが形成で
きたもの、評価×印は真球度が悪く、ばらつきが
大きく、表面形状が優れなかつたものである。
(Industrial Application Field) The present invention relates to a method for connecting semiconductor materials, specifically a method for bonding a semiconductor chip to a substrate by a wireless bonding method, particularly a flip-chip bonding method or a tape carrier bonding method, and a connecting material used therein. Regarding. (Prior art and its problems) A conventional method for forming bump electrodes using a wire bonder is disclosed in Japanese Patent Laid-Open No. 61-43438.
This method requires a step of cutting the wire with an electric torch or the like after bonding the dumbbell-shaped bump electrode. In addition, the current bump electrode materials include:
PbSn 5wt %, PbSn 40wt %, etc. are used, but when the alloy wire produced by the normal casting method was made into a wire by drawing a die and was connected using a wire bonder, the wire bonded to the base of the ball. It was found that the wire was often cut in the middle of the wire rather than at the end, and the length varied widely, making it unsuitable for use as a bump electrode. The reason why the alloy wire breaks at the wire portion is that the tensile strength of the base of the ball is not sufficiently smaller than the tensile strength of the wire portion. (Technical Problems to be Solved by the Invention) The present invention solves the above-mentioned conventional problems, makes it possible to form bump electrodes using a wire bonder, and provides a method for connecting semiconductors with high workability. The object of the present invention is to provide a connecting material for use in the method. (Technical Means for Achieving the Technical Problem) The technical means of the present invention is a thin alloy wire made of one of Pb, Sn, and In as a main element and produced by a rapid solidification method. By heating the tip to form a ball and pulling the alloy wire while adhering the ball to the upper surface of the wiring or the upper surface of the semiconductor material, the ball is cut from its root and a bump electrode is formed on the upper surface of the wiring or the semiconductor material. The connecting material of the present invention has one of Pb, Sn, and In as a main element, and an additive element is added thereto. The alloy is made into a thin wire shape using a rapid solidification method. (Function) According to the present invention, the alloy wire produced by the rapid solidification method has a structure state in which many lattice defects are introduced, crystal grains are refined, non-equilibrium phases are formed, and elements are forced into solid solution. This significantly increases the tensile strength. When the tip of the alloy wire is heated to form a ball, the nonequilibrium phase disappears at the root of the ball, forced solid solution between elements is released, and lattice defects are released. Further, phenomena such as coarsening of crystal grains occur, which reduces the tensile strength of the base of the ball, making it more likely to yield or break. Therefore, by pulling the wire, the ball is cut from its root, and a bump electrode is formed by the ball cut from the wire on the upper surface of the semiconductor material or the upper surface of the wiring. (Example) Hereinafter, an example of the present invention will be described with reference to the drawings. [Example] As shown in FIG. 11, the semiconductor device A used in this example is of the so-called flip-chip bonding type, and the substrate 1 is made of an insulating resin such as alumina or glass epoxy resin. On the top
Cu or Cr・Cu or Pt or Pd or Ag or Pd・Ag
Alternatively, a wiring 2 made of a conductive material such as Au, Al, or Ni is wired, and a chip 3 made of a semiconductor material is mounted in the center of the substrate 1 to form a bump electrode 7.
It is electrically connected to the wiring 2 via a. Further, the semiconductor chip 3 and a part of the wiring 2 are sealed with a protective resin such as silicon. Further, FIGS. 1 to 5 are cross-sectional views showing a method of connecting semiconductor materials of the present invention in the semiconductor device A. FIG. 1 shows an alloy wire 5 as a connecting material inserted into a capillary 4 of a wire bonder, and a ball 7 is formed by heating the tip of this alloy wire with an electric torch 6. The alloy wire 5 is a solder material, that is, an alloy in which one of Pb, Sn, and In is the main element and additional elements are mixed therein, and is a thin wire produced by a rapid solidification method. In other words, as a rapid solidification method,
A wire may be formed directly by a conventionally known submerged spinning method, or an alloy material obtained by a single roll method may be cold pressed and then extruded to form a wire. and,
The obtained wire is drawn to a predetermined fine wire diameter to produce the alloy wire 5. The additive elements of the alloy wire 5 include Be, B,
C, Mg, Al, Si, P, Ca, Ti, V, Cr, Mn,
Fe, Co, Ni, Cu, Zn, Ga, Ge, Se, Zr, Nb,
Mo, Pd, Ag, Cd, Sb, Te, Ir, Pt, Au, Tl,
It is also possible to mix one or more of Bi, or to add main elements Pb, Sn, and In to main elements that do not contain them. The alloy wire 5 undergoes the rapid cooling treatment to
Many lattice defects are introduced, crystal grains become finer,
A non-equilibrium phase is formed and the elements are in a forced solid solution state, and by wire drawing,
Lattice defects are introduced due to work hardening, and the structure is solid solution hardened by the added elements. Next, as shown in FIGS. 2 and 3, the capillary 4 is lowered and the ball 7 formed at the tip of the alloy wire 5 is attached to the wiring 2, and then the capillary 4 is pulled up, and the base of the ball 7 is Ball 7 is cut from alloy wire 5 and placed on wiring 2.
is supplied to form bump electrodes 7a. Then, by such a method, bump electrodes 7a are continuously formed on all lines of wiring 2 on the upper surface of substrate 1. When the alloy wire 5 is cut, when the ball 7 is heated and formed, the non-equilibrium phase disappears at the root of the ball 7, forced solid solution between elements is released, lattice defects are released, and the crystal is crystallized. Since the grains are in a coarsened structure, the tensile strength of that part decreases, and this occurs because the ball 7 yields and breaks at its base when the alloy wire 5 is simply pulled up by the capillary 4. Next, as shown in FIG.
By adhering to the electrode 3a disposed on the surface, the wiring 2 and the electrode 3a are electrically connected and the semiconductor chip 3 is attached. Further, as shown in FIG. 5, in order to connect the wiring 2 and the bump electrode 7a or the bump electrode 7a and the electrode 3a on the surface of the semiconductor chip with low electrical resistance and strong mechanical bonding, it is necessary to Base metal layers 3b and 3c, which can easily form an alloy with the material, are formed by a vapor deposition method, a sputtering method, a plating method, or the like. For example, if the material of the electrode 3a of the semiconductor chip is Al, a single layer or a laminated interface using Cr, Ti, Cu, Ni, Pd, Ag, Pt, Au, etc. is formed in the base metal layer 3b. In addition, in the embodiment, the ball 7 is placed on the wiring 2 in order to form the bump electrode 7a on the wiring 2.
However, in order to form the bump electrode 7a on the electrode 3a of the semiconductor chip 3, the ball 7 can also be attached on the electrode 3a. [Example] The semiconductor device B used in this example is of the so-called tape carrier bonding type, as shown in FIG.
A bump electrode 7a is formed thereon, a film lead 10 is bonded to the bump electrode 7a, and the wiring 8 on the substrate 9 and the film lead 10 are bonded. Further, FIGS. 6 to 10 are cross-sectional views showing the method of connecting semiconductor materials of the present invention in the semiconductor device B. FIG. 6 shows an alloy wire 5 as a connecting material inserted into a capillary 4 of a wire bonder, and a ball 7 is formed by heating the tip of this alloy wire with an electric torch 6. The alloy wire 5 is a solder material, that is, an alloy in which one of Pb, Sn, and In is the main element and additional elements are mixed therein, and is a thin wire produced by a rapid solidification method. In other words, the rapid solidification method involves directly forming a wire using the conventionally known liquid spinning method, or cold pressing an alloy material obtained using a single roll method, and then extruding it to form a wire. According to the method. Then, the obtained wire is drawn to a predetermined fine wire diameter to produce the alloy wire 5. The additive elements of the alloy wire 5 include Be, B,
C, Mg, Al, Si, P, Ca, Ti, V, Cr, Mn,
Fe, Co, Ni, Cu, Zn, Ga, Ge, Se, Zr, Nb,
Mo, Pd, Ag, Cd, Sb, Te, Ir, Pt, Au, Tl,
It is also possible to mix one or more of Bi, or to add main elements Pb, Sn, and In to main elements that do not contain them. The alloy wire 5 undergoes the rapid cooling treatment to
Many lattice defects are introduced, crystal grains become finer,
The structure is such that a non-equilibrium phase is formed and forced solid solution occurs between elements, and furthermore, due to wire drawing,
Lattice defects are introduced due to work hardening, and the structure is solid solution hardened by the added elements. Next, as shown in FIGS. 7 and 8, the capillary 4 is lowered and the ball 7 formed at the tip of the alloy wire 5 is attached to the film lead 10, and then the capillary 4 is pulled up, and the base of the ball 7 is A ball 7 is cut from the alloy wire 5 at a portion and is supplied onto the film lead 10 to form a bump electrode 7a. Then, by this method, film lead 1
Bump electrodes 7a are continuously formed on the entire 0 line. When the alloy wire 5 is cut, when the ball 7 is heated and formed, the non-equilibrium phase disappears at the root of the ball 7, forced solid solution between elements is released, lattice defects are released, and the crystal is crystallized. Since the grains are in a coarsened structure, the tensile strength of that part decreases, and this occurs because the ball 7 yields and breaks at its base when the alloy wire 5 is simply pulled up by the capillary 4. Next, as shown in FIG. 9, the bump electrodes 7a supplied and attached to the upper surface of the film leads 10 are bonded to the electrodes 3a disposed on the surface of the semiconductor chip 3, so that the film leads 10 and the electrodes 3 are bonded to each other.
A is electrically connected to the semiconductor chip 3, and the semiconductor chip 3 is attached. Further, as shown in FIG. 10, in order to bond the film lead 10 and the bump electrode 7a or the bump electrode 7a and the electrode 3a on the surface of the semiconductor chip with low electrical resistance and strong mechanically, Base metal layers 3b and 3c, which can easily form an alloy with the material, are formed by a vapor deposition method, a sputtering method, a plating method, or the like. For example, the electrode 3a of a semiconductor chip
If the material of the base metal layer 3b is Al, the base metal layer 3b is Cr or Ti.
Alternatively, a single layer or laminated interface using Cu, Ni, Pd, Ag, Pt, Au, etc. is formed. Further, in the embodiment, the balls 7 are attached to the film leads 10 in order to form the bump electrodes 7a on the film leads 10, but on the other hand, the balls 7 are attached to the film leads 10 in order to form the bump electrodes 7a on the electrodes 3a of the semiconductor chip 3. The electrode 3
It is also possible to attach it on a. Below, the type, workability, ball forming ability, tensile strength, elongation, ball hardness, and whether or not it is possible to cut the ball root part of the alloy wire 5 of the present invention are as follows.
This figure is also shown together with a comparative product manufactured using the conventional casting method. The cooling rate during rapid solidification of the alloy wire of the present invention was 10 3 to 10 5 °C/sec, and the wires of the present invention and comparative wires were both made to have a wire diameter of 60 μm as samples. Among the characteristics of the above-mentioned sample, workability is an evaluation of whether or not it is possible to wire draw up to 60 um without heat treatment in the following two stages. That is, evaluations marked with ○ indicate that processing is possible, and evaluations marked with × indicate problems in processability, such as frequent disconnections. Ball-forming ability is defined as the ability to form a ball by passing each sample through a ceramic capillary, under a gas jet of 5 vol% hydrogen gas added to argon gas, and by arc discharge between the sample and an electrode placed near the tip of the sample. A ball was formed and the state of the ball formation was evaluated in the following two stages. That is, the evaluation mark ○ means that a ball with good sphericity and smooth surface shape can be formed, and the evaluation mark X means that the sphericity is poor, the variation is large, and the surface shape is not excellent.
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【表】【table】
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【表】
（発明の効果）
本発明によれば、ワイヤーボンダを用いて合金
ワイヤーからボールを供給し、バンプ電極を形成
することができるので、電気トーチなどを用いた
ワイヤーとボールとの切断工程を不要にして作業
工程を簡素化するとともにボールの切断位置が一
定しているため供給量がバラつかず、またワイヤ
ーボンダによるる供給のためバンプ供給位置精度
を高めることができ、しかも合金ワイヤーがPb，
Sn，Inを主要元素する半田材料からなるので、
他に接続材料を用いる必要がなく、作業性及びコ
ストを安価ならしめる。[Table] (Effects of the Invention) According to the present invention, a bump electrode can be formed by supplying balls from an alloy wire using a wire bonder, so the process of cutting the wire and balls using an electric torch etc. This simplifies the work process by eliminating the need for bumps, and since the cutting position of the balls is constant, there is no variation in the supply amount, and since the bumps are supplied using a wire bonder, the accuracy of the bump supply position can be increased. Pb,
Since it is made of solder material whose main elements are Sn and In,
There is no need to use any other connecting material, making workability and cost low.
図面は本発明の実施例を示し、第１図〜第５図
はフリツプチツプボンテイング法（実施例）に
よる半導体材料の接続方法及びそれに用いる接続
材料を示す断面図、第６図〜第１０図はテープキ
ヤリアボンデイング法（実施例）による半導体
材料の接続方法及びそれに用いる接続材料を示す
断面図、第１１図は実施例の半導体装置の断面
図、第１２図は実施例の半導体装置の断面図で
ある。
尚図中、３……半導体チツプ、５……合金ワイ
ヤー、７……ボール、７ａ……バンプ電極。
The drawings show embodiments of the present invention, and FIGS. 1 to 5 are cross-sectional views showing a method for connecting semiconductor materials by the flip-chip bonding method (embodiment) and connection materials used therein, and FIGS. 6 to 10 The figure is a sectional view showing a method of connecting semiconductor materials by tape carrier bonding method (example) and the connection material used therein, FIG. 11 is a sectional view of a semiconductor device of an example, and FIG. 12 is a sectional view of a semiconductor device of an example. It is a diagram. In the figure, 3... semiconductor chip, 5... alloy wire, 7... ball, 7a... bump electrode.
Claims (1)
かつ急冷凝固法により作製された細い合金ワイヤ
ーの先端を加熱してボールを形成し該ボールを配
線上面又は半導体材料上面に接着させた状態で合
金ワイヤーを引張ることにより、ボールがその根
本部から切断されて配線上面又は半導体材料上面
にバンプ電極を形成せしめ、そのバンプ電極を介
して半導体材料を接続する半導体材料の接続方
法。 ２ Pb，Sn，Inの何れか１つを主要元素とし、
それに添加元素を配合した合金を急冷凝固法によ
り細いワイヤー状に作製してなる半導体材料の接
続材料。 ３ 上記添加元素がBe，Ｂ，Ｃ，Mg，Al，Si，
Ｐ，Ca，Ti，Ｖ，Cr，Mn，Fe，Co，Ni，Cu，
Zn，Ga，Ge，Se，Zr，Nb，Mo，Pd，Ag，
Cd，In，Sn，Pb，Sb，Te，Ir，Pt，Au，Tl，
Bi中の１種又は２種以上である特許請求の範囲
第２項記載の半導体材料の接続材料。[Claims] 1. Any one of Pb, Sn, In as a main element,
Then, the tip of a thin alloy wire made by the rapid solidification method is heated to form a ball, and the ball is cut from its base by pulling the alloy wire with the ball adhered to the upper surface of the wiring or the upper surface of the semiconductor material. A method for connecting a semiconductor material, in which a bump electrode is formed on the upper surface of a wiring or a semiconductor material, and the semiconductor material is connected via the bump electrode. 2 One of Pb, Sn, and In is the main element,
A connecting material for semiconductor materials that is made from an alloy containing additives and made into a thin wire shape using the rapid solidification method. 3 The above additive elements are Be, B, C, Mg, Al, Si,
P, Ca, Ti, V, Cr, Mn, Fe, Co, Ni, Cu,
Zn, Ga, Ge, Se, Zr, Nb, Mo, Pd, Ag,
Cd, In, Sn, Pb, Sb, Te, Ir, Pt, Au, Tl,
The connecting material for a semiconductor material according to claim 2, which is one or more kinds of Bi.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62130595A JPS63301535A (en) | 1987-01-30 | 1987-05-27 | Method for bonding semiconductor material and bonding material used therefor |
| GB8800518A GB2201545B (en) | 1987-01-30 | 1988-01-11 | Method for connecting semiconductor material |
| US07/970,232 US5384090A (en) | 1987-01-30 | 1992-10-30 | Fine wire for forming bump electrodes using a wire bonder |
| US08/315,577 US5514912A (en) | 1987-01-30 | 1994-09-30 | Method for connecting semiconductor material and semiconductor device used in connecting method |
| US08/315,575 US5514334A (en) | 1987-01-30 | 1994-09-30 | Fine lead alloy wire for forming bump electrodes |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-21202 | 1987-01-30 | ||
| JP2120287 | 1987-01-30 | ||
| JP62130595A JPS63301535A (en) | 1987-01-30 | 1987-05-27 | Method for bonding semiconductor material and bonding material used therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63301535A JPS63301535A (en) | 1988-12-08 |
| JPH0465534B2 true JPH0465534B2 (en) | 1992-10-20 |
Family
ID=26358236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62130595A Granted JPS63301535A (en) | 1987-01-30 | 1987-05-27 | Method for bonding semiconductor material and bonding material used therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63301535A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2891432B2 (en) * | 1989-12-27 | 1999-05-17 | 田中電子工業株式会社 | Connection method of semiconductor material, connection material used therefor, and semiconductor device |
| JPH04299544A (en) * | 1991-03-28 | 1992-10-22 | Nec Corp | Manufacture of film carrier semiconductor device |
-
1987
- 1987-05-27 JP JP62130595A patent/JPS63301535A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63301535A (en) | 1988-12-08 |
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