JPH0565051B2 - - Google Patents
Info
- Publication number
- JPH0565051B2 JPH0565051B2 JP61314162A JP31416286A JPH0565051B2 JP H0565051 B2 JPH0565051 B2 JP H0565051B2 JP 61314162 A JP61314162 A JP 61314162A JP 31416286 A JP31416286 A JP 31416286A JP H0565051 B2 JPH0565051 B2 JP H0565051B2
- Authority
- JP
- Japan
- Prior art keywords
- ball
- wire
- amorphous
- semiconductor material
- thin wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 claims 2
- 229910000808 amorphous metal alloy Inorganic materials 0.000 description 11
- 239000000758 substrate Substances 0.000 description 8
- 239000010931 gold Substances 0.000 description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000004017 vitrification Methods 0.000 description 2
- -1 Co Substances 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229920006280 packaging film Polymers 0.000 description 1
- 239000012785 packaging film Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01037—Rubidium [Rb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01066—Dysprosium [Dy]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0107—Ytterbium [Yb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は各種コンピユーターに使用される半導
体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device used in various computers.
（従来の技術とその問題点）
パツケージ等の基板上面に配設されたリード線
と半導体材料との電気的接続の方法には、いわゆ
るフリツプチツプ方式というものがある。(Prior Art and its Problems) There is a so-called flip-chip method as a method for electrically connecting lead wires disposed on the upper surface of a substrate such as a package and a semiconductor material.
これは、ワイヤレスボンデイングのひとつであ
り、半導体材料の表面の配設された内部配線と基
板上面に配設されたリード線とをバンプ電極又は
半田等の接合材を介して溶着することにより、電
気的接続と半導体材料の取り付けとを同時に行う
ものである。 This is a type of wireless bonding, in which internal wiring arranged on the surface of a semiconductor material and lead wires arranged on the top surface of a substrate are welded together via bump electrodes or a bonding material such as solder. This method simultaneously performs physical connections and attaches semiconductor materials.
ところがこれは、バンプ電極を形成するために
半導体材料表面の内部配線を被覆するフアイナル
パツシペーシヨン膜に穿孔部を開穿すると共に、
基板上面のリード線上には金又は半田等を被着し
て下地金属を形成しなければならないため接続工
程が複雑でかつ製造コストが高くなるという問題
があつた。 However, in order to form bump electrodes, a perforation is made in the final packaging film that covers the internal wiring on the surface of the semiconductor material, and
Since it is necessary to form a base metal by depositing gold or solder on the lead wires on the upper surface of the substrate, there are problems in that the connection process is complicated and the manufacturing cost is high.
また、亜鈴形状のバンプ電極をワイヤボンダを
用いて形成させる特願昭59−164973号のものがあ
るが、この方法はワイヤ材料が結晶質の金、同ア
ルミウムで構成されているためボンデイングした
後の切断が簡単にできずワイヤーを切断するため
の工程を必要とし、それが電気トーチ等で行われ
ていた。 In addition, there is a Japanese Patent Application No. 164973/1987 in which a dumbbell-shaped bump electrode is formed using a wire bonder, but since the wire material is composed of crystalline gold and aluminum, this method requires It cannot be cut easily and requires a process to cut the wire, which is done using an electric torch or the like.
さらに、バンプ電極は接着強度を高めるため
に、ボールが軟かいと共にその形状が真球に近く
て安定し、かつキヤピラリによる変形が容易に行
なえることが望まれている。 Furthermore, in order to increase the bonding strength of the bump electrode, it is desired that the ball is soft, has a shape close to a true sphere, is stable, and can be easily deformed by a capillary.
（発明が解決しようとする技術的課題）
以上の問題を解決しようとする本発明の技術的
課題は、パツケージ等の基板上面に配設されたリ
ード線とチツプとの電気的接続に関して、該接続
工程を簡略化してその作業能率を高めると共に、
リード線とチツプとの接着強度を高めることであ
る。(Technical Problem to be Solved by the Invention) A technical problem to be solved by the present invention is to solve the above-mentioned problems with respect to electrical connection between lead wires arranged on the top surface of a substrate such as a package and a chip. In addition to simplifying processes and increasing work efficiency,
The purpose is to increase the adhesive strength between the lead wire and the chip.
（技術的課題を達成するための技術的手段）
以上の技術的課題を達成するために本発明の接
続方法は、非晶質構造からなるアモルフアス合金
又は部分的に結晶質を含むアモルフアス合金より
なる芯線に、他の金属をコーテイングして形成し
た細いワイヤーの先端を加熱してボールを形成す
ると共にそのボールの根本部に非晶質構造特有の
構造緩和現象を起こさせた後、該ボールを配線上
面又は半導体材料上面に接着させた状態で該細い
ワイヤーを引張ることにより、該ボールが細いワ
イヤーから切断されて配線上面又は半導体材料上
面にバンプ電極が形成され、該バンプ電極を介し
て半導体材料を接続することを特徴とする。(Technical Means for Achieving the Technical Problem) In order to achieve the above-mentioned technical problem, the connection method of the present invention consists of an amorphous amorphous alloy having an amorphous structure or an amorphous amorphous alloy partially containing a crystalline structure. The tip of a thin wire made by coating the core wire with another metal is heated to form a ball, and the root of the ball is caused to undergo a structural relaxation phenomenon unique to an amorphous structure, and then the ball is wired. By pulling the thin wire while it is adhered to the top surface or the top surface of the semiconductor material, the ball is cut from the thin wire and a bump electrode is formed on the top surface of the wiring or the top surface of the semiconductor material, and the semiconductor material is inserted through the bump electrode. It is characterized by connecting.
（発明の効果）
本発明は以上の様な方法にしたことにより下記
の効果を有する。(Effects of the Invention) By employing the method described above, the present invention has the following effects.
非晶質構造からなるアモルフアス合金の芯線
に他の金属をコーテイングして形成された細い
ワイヤーを用いたことから、該ワイヤー先端に
形成されるボールが軟化し易くなると共にボー
ルの参加を防いで、ボールの真球度が高くな
り、且つキヤピラリによる変形が容易に行える
ようになる。よつて、バンプ電極による接続強
度を高めることができる。 By using a thin wire formed by coating a core wire of an amorphous alloy with an amorphous structure with another metal, the ball formed at the tip of the wire becomes easy to soften and prevents the ball from joining. The ball has a high sphericity and can be easily deformed by a capillary. Therefore, the strength of the connection by the bump electrode can be increased.
上記のようにして形成された細いワイヤーの
先端部を加熱してボールを形成することによ
り、該ボールの根本部が非晶質構造特有の構造
緩和現象により脆くなり、該ボールを配線上面
に接着させた状態でワイヤーを引張ることによ
りボーリウが自動的に切断されるので、何ら切
断装置を必要とせず、従来の電気トーチ等によ
るワイヤーの切断工程を削除できると共にボー
ルの連続供給が可能となり作業能率の向上を図
ることができる。 By heating the tip of the thin wire formed as described above to form a ball, the root of the ball becomes brittle due to the structural relaxation phenomenon unique to an amorphous structure, and the ball is bonded to the top surface of the wiring. Since the balls are automatically cut by pulling the wire in this state, there is no need for any cutting equipment, eliminating the conventional process of cutting the wire using an electric torch, etc., and making it possible to continuously supply balls, increasing work efficiency. It is possible to improve the
ボンダによるボールの供給が可能なため、従
来の形成法により精度の高くかつ製造コストも
低くすることができる。 Since the balls can be supplied by a bonder, it is possible to achieve high precision and low manufacturing costs using conventional forming methods.
（実施例）
以下、本発明の一実施例を図面に基づいて説明
する。(Example) Hereinafter, an example of the present invention will be described based on the drawings.
本発明に使用される半導体装置Ａは第１図に示
す如く、いわゆるリードレスチツプキヤリア
LCC型であり、基板１がアルミナ又はガラスエ
ポキシ樹脂で形成され、該基板１の上面にはタン
グステンメタライズ又は銅からなるリード線１が
配設されると共に基板１中央部には半導体材料３
が搭載されてバンプ電極７ａを介して前記リード
線２と電気的に接続されている。 As shown in FIG. 1, the semiconductor device A used in the present invention is a so-called leadless chip carrier.
It is an LCC type, and the substrate 1 is made of alumina or glass epoxy resin, and a lead wire 1 made of tungsten metallization or copper is provided on the upper surface of the substrate 1, and a semiconductor material 3 is provided in the center of the substrate 1.
is mounted and electrically connected to the lead wire 2 via the bump electrode 7a.
さらに、前記半導体材料３とロード線２の一部
とがシリコン等の保護樹脂で封止して形成されて
いる。 Further, the semiconductor material 3 and a part of the load line 2 are sealed with a protective resin such as silicon.
また、第３図〜第６図は前記半導体装置Ａにお
いて、本発明の半導体材料の接続方法を示した断
面図である。 Moreover, FIGS. 3 to 6 are cross-sectional views showing the method of connecting semiconductor materials of the present invention in the semiconductor device A.
第２図における５はアモルフアス合金よりなる
極細芯線５ａの表面にその金属層５ｂをコーテイ
ングした細いワイヤーである。 Reference numeral 5 in FIG. 2 is a thin wire consisting of an ultrafine core wire 5a made of an amorphous alloy whose surface is coated with a metal layer 5b.
上記アモルフアス合金は非晶質構造からなるこ
とにより、常温においては引張強度及び圧縮強度
が大きく強靭性を有するが、加熱による構造緩和
現象の領域においては脆化し切断されやすい状態
となる。 Since the amorphous alloy has an amorphous structure, it has high tensile strength and compressive strength and is strong and tough at room temperature, but becomes brittle and easily breaks in the region of structural relaxation caused by heating.
上記要求を満たすために前記アモルフアス合金
は遷移金属であるCu、Ag、Au、Ni、Pd、Pt、
Co、Rh、Ir、Fe、Mn、Cr、Mo、Ｗ、Re、Ｖ、
Nb、Ta、Ti、Zr、Hfのうち１種又は２種以上
を含有し、かつ半金属、半導体元素であるＢ、
Ｃ、Al、Si、Ga、Ge、In、Sn、Pb、及び非金
属元素であるＰ、Ｓ、Sb、Biの１種又は２種以
上を５〜30原子％、この好ましくは10〜２原子％
配合させた組成とする。 In order to meet the above requirements, the amorphous alloy contains transition metals Cu, Ag, Au, Ni, Pd, Pt,
Co, Rh, Ir, Fe, Mn, Cr, Mo, W, Re, V,
B, which contains one or more of Nb, Ta, Ti, Zr, and Hf and is a semimetal or semiconductor element;
5 to 30 at% of one or more of C, Al, Si, Ga, Ge, In, Sn, Pb, and nonmetallic elements P, S, Sb, and Bi, preferably 10 to 2 atoms. %
A blended composition is obtained.
また、該金属層５ｂはアモルフアス合金の主要
元素を電気めつきしたものであり、例えばアモル
フアス合金がPd基合金の場合Pdメツキ、Au基合
金の場合はAuメツキを施こして形成する。 The metal layer 5b is formed by electroplating the main elements of the amorphous amorphous alloy, and is formed by, for example, Pd plating if the amorphous amorphous alloy is a Pd-based alloy, or by Au plating if the amorphous amorphous alloy is an Au-based alloy.
そして、該めつきワイヤー５に引き抜き加工を
施して同径のものを形成する。 Then, the plating wire 5 is subjected to a drawing process to form a wire having the same diameter.
尚、この金属層５ｂは前記主要元素に限らず、
例えば、Pd基合金にAuメツキ、Pbメツキ、Au
基合金にPdメツキ、Pbメツキであつても任意で
ある。 Note that this metal layer 5b is not limited to the above-mentioned main elements,
For example, Pd-based alloys are plated with Au, Pb plated, and Au.
Even if the base alloy is Pd plating or Pb plating, it is optional.
以上の様な主要金属をコーテイングした場合は
ボールの硬さを低下（軟化）させ変形を容易にす
ることができる。 When the ball is coated with the above-mentioned main metals, the hardness of the ball can be reduced (softened) and deformation can be made easier.
次に本発明の半導体材料の接続方法を第３図〜
第６図により説明する。 Next, the method of connecting semiconductor materials of the present invention is shown in FIGS.
This will be explained with reference to FIG.
まず、第１のワイヤボンダのキヤピラリ４に挿
通されているアモルフアス合金の極細芯線５ａの
表面に金属層５ｂをコーテイングしたワイヤー５
先端に、電気トーチ６を近ずけてボール７を形成
する。 First, a wire 5 is formed by coating a metal layer 5b on the surface of an amorphous alloy ultrafine core wire 5a that is inserted into a capillary 4 of a first wire bonder.
An electric torch 6 is brought close to the tip to form a ball 7.
このボール７はガラス化温度を越えて結晶質と
なつており、またボールの根本部７′のアモルフ
アス相はガラス化温度により低温度域であつて構
造緩和現象の領域となつている（第３図）。 This ball 7 has exceeded the vitrification temperature and has become crystalline, and the amorphous phase at the root portion 7' of the ball is in a low temperature range due to the vitrification temperature, which is the region of structural relaxation phenomenon (third figure).
次に第４図及び第５図に示す如く、キヤピラリ
４を下降させてアモルフアス合金の細いワイヤー
５先端に形成されたボール７を配線であるリード
線２に付着させた状態でキヤピラリ４を引き上げ
ることにより、ボール７の根本部７′で細いワイ
ヤー５から切断されたリード線２上にボール７が
供給されてバンプ電極７ａが形成される。 Next, as shown in FIGS. 4 and 5, the capillary 4 is lowered and the ball 7 formed at the tip of the thin amorphous alloy wire 5 is attached to the lead wire 2, which is the wiring, and then the capillary 4 is pulled up. As a result, the ball 7 is supplied onto the lead wire 2 cut from the thin wire 5 at the root portion 7' of the ball 7, thereby forming the bump electrode 7a.
以上の様な方法により基板１上面に配線された
リード線２全線にバンプ電極７ａが連続的に形成
される。 By the method described above, bump electrodes 7a are continuously formed on all the lead wires 2 wired on the upper surface of the substrate 1.
そして、第６図に示す如くこれらリード線２上
面に供給し付着されたバンプ電極７ａを半導体材
料３表面に配設された内部配線３ａに接着させる
ことにより、該リード線２と内部配線３ａとが電
気的に接続されると共に、該半導体材料３が取り
付けられるものである。 Then, as shown in FIG. 6, the bump electrodes 7a supplied and attached to the upper surface of these lead wires 2 are bonded to the internal wiring 3a disposed on the surface of the semiconductor material 3, thereby connecting the lead wires 2 and the internal wiring 3a. are electrically connected to each other, and the semiconductor material 3 is attached thereto.
第１図は半導体装置の断面図、第２図は細いワ
イヤー又は細いリボンの横断面図、第３図〜第６
図は半導体装置における半導体材料の接続方法を
示す断面図である。
尚、図中、３：半導体材料、５，５：細いワイ
ヤー又は細いリボン、７：ボール、７ａ：バンプ
電極を夫々示す。
Figure 1 is a cross-sectional view of a semiconductor device, Figure 2 is a cross-sectional view of a thin wire or ribbon, and Figures 3 to 6.
The figure is a cross-sectional view showing a method of connecting semiconductor materials in a semiconductor device. In the figure, 3: semiconductor material, 5, 5: thin wire or thin ribbon, 7: ball, 7a: bump electrode, respectively.
Claims (1)
分的に結晶質を含むアモルフアス合金よりなる芯
線に、他の金属をコーテイングして形成した細い
ワイヤーの先端を加熱してボールを形成すると共
にそのボールの根本部に非晶質構造特有の構造緩
和現象を起こさせた後、該ボールを配線上面又は
半導体材料上面に接着させた状態で該細いワイヤ
ーを引張ることにより、該ボールが細いワイヤー
から切断されて配線上面又は半導体材料上面にバ
ンプ電極が形成され、該バンプ電極を介して半導
体材料を接続する半導体材料の接続方法。1. A ball is formed by heating the tip of a thin wire formed by coating a core wire made of an amorphous acetate alloy with an amorphous structure or an amorphous acetate alloy with a partially crystalline structure with another metal, and then forming a ball at the base of the ball. After causing a structural relaxation phenomenon peculiar to an amorphous structure in the part, by pulling the thin wire with the ball adhered to the upper surface of the wiring or the upper surface of the semiconductor material, the ball is cut from the thin wire and the wiring is formed. A method for connecting semiconductor materials, in which a bump electrode is formed on an upper surface or an upper surface of a semiconductor material, and the semiconductor materials are connected via the bump electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61314162A JPS63168037A (en) | 1986-12-29 | 1986-12-29 | Connection of semiconductor material and applicable connecting material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61314162A JPS63168037A (en) | 1986-12-29 | 1986-12-29 | Connection of semiconductor material and applicable connecting material |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63168037A JPS63168037A (en) | 1988-07-12 |
| JPH0565051B2 true JPH0565051B2 (en) | 1993-09-16 |
Family
ID=18049987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61314162A Granted JPS63168037A (en) | 1986-12-29 | 1986-12-29 | Connection of semiconductor material and applicable connecting material |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63168037A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005005598A (en) * | 2003-06-13 | 2005-01-06 | Fujitsu Ltd | Semiconductor device |
| JP4870407B2 (en) * | 2005-09-21 | 2012-02-08 | 株式会社キンキ | Shearing crusher |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61253384A (en) * | 1985-01-07 | 1986-11-11 | Masami Kobayashi | Method for plating amorphous alloy |
-
1986
- 1986-12-29 JP JP61314162A patent/JPS63168037A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61253384A (en) * | 1985-01-07 | 1986-11-11 | Masami Kobayashi | Method for plating amorphous alloy |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63168037A (en) | 1988-07-12 |
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