JPH0449198B2 - - Google Patents

Info

Publication number
JPH0449198B2
JPH0449198B2 JP58181091A JP18109183A JPH0449198B2 JP H0449198 B2 JPH0449198 B2 JP H0449198B2 JP 58181091 A JP58181091 A JP 58181091A JP 18109183 A JP18109183 A JP 18109183A JP H0449198 B2 JPH0449198 B2 JP H0449198B2
Authority
JP
Japan
Prior art keywords
data
word line
flop
memory
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58181091A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6074194A (ja
Inventor
Yasuo Kobayashi
Yasuo Akatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58181091A priority Critical patent/JPS6074194A/ja
Publication of JPS6074194A publication Critical patent/JPS6074194A/ja
Publication of JPH0449198B2 publication Critical patent/JPH0449198B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
JP58181091A 1983-09-29 1983-09-29 メモリ回路 Granted JPS6074194A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58181091A JPS6074194A (ja) 1983-09-29 1983-09-29 メモリ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58181091A JPS6074194A (ja) 1983-09-29 1983-09-29 メモリ回路

Publications (2)

Publication Number Publication Date
JPS6074194A JPS6074194A (ja) 1985-04-26
JPH0449198B2 true JPH0449198B2 (https=) 1992-08-10

Family

ID=16094664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58181091A Granted JPS6074194A (ja) 1983-09-29 1983-09-29 メモリ回路

Country Status (1)

Country Link
JP (1) JPS6074194A (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6653543B2 (en) 2002-03-07 2003-11-25 Charles J. Kulas Musical instrument tuner with configurable display
IT202000029771A1 (it) * 2020-12-03 2022-06-03 Sk Hynix Inc Architettura di latch

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6061986A (ja) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp 半導体記憶装置
JPS6061985A (ja) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
JPS6074194A (ja) 1985-04-26

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