JPH0444455B2 - - Google Patents

Info

Publication number
JPH0444455B2
JPH0444455B2 JP57214469A JP21446982A JPH0444455B2 JP H0444455 B2 JPH0444455 B2 JP H0444455B2 JP 57214469 A JP57214469 A JP 57214469A JP 21446982 A JP21446982 A JP 21446982A JP H0444455 B2 JPH0444455 B2 JP H0444455B2
Authority
JP
Japan
Prior art keywords
code
data
transmitting
signal
codes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57214469A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59103448A (ja
Inventor
Shinsuke Mizutani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP57214469A priority Critical patent/JPS59103448A/ja
Publication of JPS59103448A publication Critical patent/JPS59103448A/ja
Publication of JPH0444455B2 publication Critical patent/JPH0444455B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP57214469A 1982-12-06 1982-12-06 データ送受信装置 Granted JPS59103448A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57214469A JPS59103448A (ja) 1982-12-06 1982-12-06 データ送受信装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57214469A JPS59103448A (ja) 1982-12-06 1982-12-06 データ送受信装置

Publications (2)

Publication Number Publication Date
JPS59103448A JPS59103448A (ja) 1984-06-14
JPH0444455B2 true JPH0444455B2 (enrdf_load_stackoverflow) 1992-07-21

Family

ID=16656235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57214469A Granted JPS59103448A (ja) 1982-12-06 1982-12-06 データ送受信装置

Country Status (1)

Country Link
JP (1) JPS59103448A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6162266A (ja) * 1984-09-04 1986-03-31 Fujitsu Ltd デイジタル端末のインタフエ−ス方式

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5479609A (en) * 1977-12-08 1979-06-25 Teac Corp Method of recording pcm signal
JPS54154910A (en) * 1978-05-29 1979-12-06 Matsushita Electric Works Ltd Data transmission system

Also Published As

Publication number Publication date
JPS59103448A (ja) 1984-06-14

Similar Documents

Publication Publication Date Title
CA1095604A (en) Computer interface
US6332173B2 (en) UART automatic parity support for frames with address bits
US6360290B1 (en) Commercial standard digital bus interface circuit
KR830008236A (ko) 바이트 동기화를 확립하기 위해 통신 서브씨스템의 장치를 갖는 데이터 처리 씨스템
JPH0444455B2 (enrdf_load_stackoverflow)
US4532627A (en) Time multiplex controlled data system
EP0227311A1 (en) Data processing system in which modules logically "OR" number sequences onto control lines to obtain the use of a time shared bus
EP0283847A3 (en) Apparatus for selecting a reference line for image data compression
JPH04287150A (ja) 同期式シリアルバス方式
JPS6461851A (en) Data transmission/reception system
JPS63231665A (ja) バス有効利用方式
KR100225043B1 (ko) 인터럽트를 이용한 다중 직렬통신방법 및 직렬통신장치
JPS587097B2 (ja) デイジタル回路
JPS60235548A (ja) 信号フレ−ムの伝送方式
SU1675896A1 (ru) Устройство дл обмена информацией ЭВМ с внешними устройствами
JP2949118B1 (ja) バス通信型エンコーダ装置のエンコーダデータ出力方法
JPH0313038A (ja) 非同期式シリアルデータ伝送装置
JPH0630506B2 (ja) シリアル通信装置
JPH0544858B2 (enrdf_load_stackoverflow)
JPS62183233A (ja) 誤り制御システム
KR830008233A (ko) 단일라인 우선순위를 설립시키는 장치를 가지는 통신 멀티플렉서
JPH03158041A (ja) データ多重転送方式
SU1725188A1 (ru) Устройство дл ввода управл ющей программы
JP2763407B2 (ja) 多重化装置
JPS61131632A (ja) 多重伝送のデ−タフオ−マツト方式