JPH0443446B2 - - Google Patents

Info

Publication number
JPH0443446B2
JPH0443446B2 JP60194110A JP19411085A JPH0443446B2 JP H0443446 B2 JPH0443446 B2 JP H0443446B2 JP 60194110 A JP60194110 A JP 60194110A JP 19411085 A JP19411085 A JP 19411085A JP H0443446 B2 JPH0443446 B2 JP H0443446B2
Authority
JP
Japan
Prior art keywords
signal
switch
driving means
signal driving
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60194110A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6253517A (ja
Inventor
Tetsuya Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP60194110A priority Critical patent/JPS6253517A/ja
Publication of JPS6253517A publication Critical patent/JPS6253517A/ja
Publication of JPH0443446B2 publication Critical patent/JPH0443446B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00346Modifications for eliminating interference or parasitic voltages or currents

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)
JP60194110A 1985-09-03 1985-09-03 信号駆動回路 Granted JPS6253517A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60194110A JPS6253517A (ja) 1985-09-03 1985-09-03 信号駆動回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60194110A JPS6253517A (ja) 1985-09-03 1985-09-03 信号駆動回路

Publications (2)

Publication Number Publication Date
JPS6253517A JPS6253517A (ja) 1987-03-09
JPH0443446B2 true JPH0443446B2 (ref) 1992-07-16

Family

ID=16319088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60194110A Granted JPS6253517A (ja) 1985-09-03 1985-09-03 信号駆動回路

Country Status (1)

Country Link
JP (1) JPS6253517A (ref)

Also Published As

Publication number Publication date
JPS6253517A (ja) 1987-03-09

Similar Documents

Publication Publication Date Title
US5198699A (en) Capacitor-driven signal transmission circuit
JP3014164B2 (ja) 出力バッファ回路
US5023472A (en) Capacitor-driven signal transmission circuit
KR100457935B1 (ko) 두집적회로를동전기적으로서로분리시키기위한방법및장치
US5828095A (en) Charge pump
KR100197188B1 (ko) 고내압회로 및 전압레벨 변환회로
US20060202735A1 (en) Bootstrapped switch with an input dynamic range greater than supply voltage
US4628218A (en) Driving circuit suppressing peak value of charging current from power supply to capacitive load
JPH0245851B2 (ref)
US4638182A (en) High-level CMOS driver circuit
EP2965425A1 (en) Voltage level shifter with a low-latency voltage boost circuit
US4894559A (en) Buffer circuit operable with reduced power consumption
EP0055073B1 (en) Improvements in or relating to electronic clock generators
JP3151329B2 (ja) データ出力回路
JPH0257736B2 (ref)
US4395644A (en) Drive circuit
US5426382A (en) Complementary logic recovered energy circuit
JP3190086B2 (ja) 昇圧回路
JP3055223B2 (ja) バッファ回路
US4760281A (en) Clock signal generating circuit
JPH024010A (ja) 出力回路
JPH06105875B2 (ja) 半導体集積論理回路
KR100596748B1 (ko) 다이내믹 시모스 로직
JP2859898B2 (ja) チョッパ型コンパレータ
KR100299050B1 (ko) 상보 게이트-소스 클럭구동회로와 이를 적용한 플립플롭

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term