JPH04330744A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPH04330744A
JPH04330744A JP3130432A JP13043291A JPH04330744A JP H04330744 A JPH04330744 A JP H04330744A JP 3130432 A JP3130432 A JP 3130432A JP 13043291 A JP13043291 A JP 13043291A JP H04330744 A JPH04330744 A JP H04330744A
Authority
JP
Japan
Prior art keywords
inner lead
resin
tape
semiconductor element
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3130432A
Other languages
English (en)
Japanese (ja)
Inventor
Tetsuya Ueda
哲也 上田
Osamu Nakagawa
治 中川
Haruo Shimamoto
晴夫 島本
Yasuhiro Teraoka
寺岡　康宏
Seiji Takemura
竹村　誠次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3130432A priority Critical patent/JPH04330744A/ja
Priority to US07/759,912 priority patent/US5166099A/en
Priority to DE4130544A priority patent/DE4130544C2/de
Priority to FR9111385A priority patent/FR2666931A1/fr
Publication of JPH04330744A publication Critical patent/JPH04330744A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/077—Connecting of TAB connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/453—Leadframes comprising flexible metallic tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07173—Means for moving chips, wafers or other parts, e.g. conveyor belts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP3130432A 1990-09-14 1991-05-02 半導体装置の製造方法 Pending JPH04330744A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP3130432A JPH04330744A (ja) 1990-09-14 1991-05-02 半導体装置の製造方法
US07/759,912 US5166099A (en) 1990-09-14 1991-09-13 Manufacturing method for semiconductor device
DE4130544A DE4130544C2 (de) 1990-09-14 1991-09-13 Verfahren zum Herstellen von Halbleitervorrichtungen
FR9111385A FR2666931A1 (fr) 1990-09-14 1991-09-16 Procede de fabrication pour dispositif a semiconducteurs, a connexion de puces sur une bande de support.

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP24474990 1990-09-14
JP2-244749 1990-09-14
JP3130432A JPH04330744A (ja) 1990-09-14 1991-05-02 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH04330744A true JPH04330744A (ja) 1992-11-18

Family

ID=26465567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3130432A Pending JPH04330744A (ja) 1990-09-14 1991-05-02 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US5166099A (https=)
JP (1) JPH04330744A (https=)
DE (1) DE4130544C2 (https=)
FR (1) FR2666931A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8384228B1 (en) * 2009-04-29 2013-02-26 Triquint Semiconductor, Inc. Package including wires contacting lead frame edge

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338705A (en) * 1992-09-10 1994-08-16 Texas Instruments Incorporated Pressure differential downset
US5474958A (en) * 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5686352A (en) * 1993-07-26 1997-11-11 Motorola Inc. Method for making a tab semiconductor device with self-aligning cavity and intrinsic standoff
US6429112B1 (en) 1994-07-07 2002-08-06 Tessera, Inc. Multi-layer substrates and fabrication processes
US6828668B2 (en) * 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5798286A (en) * 1995-09-22 1998-08-25 Tessera, Inc. Connecting multiple microelectronic elements with lead deformation
US6117694A (en) * 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US5518964A (en) * 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5830782A (en) * 1994-07-07 1998-11-03 Tessera, Inc. Microelectronic element bonding with deformation of leads in rows
US6024274A (en) * 1996-04-03 2000-02-15 Industrial Technology Research Institute Method for tape automated bonding to composite bumps
KR100459968B1 (ko) * 1996-10-17 2005-04-28 세이코 엡슨 가부시키가이샤 반도체장치및그제조방법,회로기판및필름캐리어테이프
US6335225B1 (en) 1998-02-20 2002-01-01 Micron Technology, Inc. High density direct connect LOC assembly
JP3420748B2 (ja) * 2000-12-14 2003-06-30 松下電器産業株式会社 半導体装置及びその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL189379C (nl) * 1977-05-05 1993-03-16 Richardus Henricus Johannes Fi Werkwijze voor inkapselen van micro-elektronische elementen.
JPS63200540A (ja) * 1987-02-17 1988-08-18 Toshiba Corp ボンデイングツ−ルの傾き測定装置
US5057461A (en) * 1987-03-19 1991-10-15 Texas Instruments Incorporated Method of mounting integrated circuit interconnect leads releasably on film
JPH0783036B2 (ja) * 1987-12-11 1995-09-06 三菱電機株式会社 キヤリアテープ
JPH02121342A (ja) * 1988-10-28 1990-05-09 Ibiden Co Ltd フィルムキャリア
JPH02155245A (ja) * 1988-12-07 1990-06-14 Matsushita Electric Ind Co Ltd 電子部品の製造方法
FR2645680B1 (fr) * 1989-04-07 1994-04-29 Thomson Microelectronics Sa Sg Encapsulation de modules electroniques et procede de fabrication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8384228B1 (en) * 2009-04-29 2013-02-26 Triquint Semiconductor, Inc. Package including wires contacting lead frame edge

Also Published As

Publication number Publication date
US5166099A (en) 1992-11-24
DE4130544A1 (de) 1992-03-19
FR2666931A1 (fr) 1992-03-20
DE4130544C2 (de) 1996-07-04
FR2666931B1 (https=) 1995-01-06

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