JPH0428244A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0428244A JPH0428244A JP2133202A JP13320290A JPH0428244A JP H0428244 A JPH0428244 A JP H0428244A JP 2133202 A JP2133202 A JP 2133202A JP 13320290 A JP13320290 A JP 13320290A JP H0428244 A JPH0428244 A JP H0428244A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- tape
- resist layer
- base tape
- thermal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 12
- 230000001681 protective effect Effects 0.000 claims description 14
- 239000000463 material Substances 0.000 abstract description 11
- 229920005989 resin Polymers 0.000 abstract description 7
- 239000011347 resin Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 238000007789 sealing Methods 0.000 abstract description 4
- 239000007767 bonding agent Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 34
- 230000000694 effects Effects 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 2
- 231100000989 no adverse effect Toxicity 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にＴＡＢ （ＴａｐｅＡ
ｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ ）用テープを用い
た半導体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a TAB (TapeA
This invention relates to the structure of a semiconductor device using automated bonding tape.
（従来の技術］
従来、ＴＡＢ用テープを用いた半導体装置の構造として
、第２図に示すものがある。同図において、ＴＡＢ用テ
ープは、ポリイミド等のベーステープ１に接着剤層２で
銅等の金属配線層３を接着し、この金属配線層３の」二
面を保護用レジスト５で覆っている。また、金属配線層
３の一部はインナーリード４としてベーステープ１に設
けた素子搭載用の窓内に突出させている。また、半導体
素子７には表面にバンプ電極８が形成され、このハンプ
電極８を前記インナーリード４に接続しており、その上
でこれらをエポキシ樹脂等の樹脂９で封止している。(Prior Art) Conventionally, there is a structure of a semiconductor device using a TAB tape as shown in FIG. A metal wiring layer 3, such as The bump electrode 8 is formed on the surface of the semiconductor element 7, and the bump electrode 8 is connected to the inner lead 4, and then these are bonded with epoxy resin or the like. It is sealed with resin 9.
なお、樹脂１：１止後の１” Ａ Ｉ３製品はリール状
に巻き取られた状態で特性選別工程で選別され、その後
個片に切断されて基板に実装される。Note that the 1" AI3 product after resin 1:1 fixing is wound into a reel and is sorted in a characteristic selection process, and then cut into individual pieces and mounted on a board.
このような従来のＴＡＢ用テープを用いた半導体装置の
構造では、保護用レジスト層５がＴ Ａ Ｂ用テープの
ベーステープ１の片面にのみ存在しているため、封止樹
脂９を加熱硬化させた後、常温まで冷却した際に、ベー
ステープ１．接着剤層２゜金属配線層３と保護用レジス
ト５との間の熱膨張係数の違いから、ＴＡＢ用テープの
長手方向に沿って−Ｌ側に凹となるような反り変形が生
じてしまうことかある。In the structure of a semiconductor device using such a conventional TAB tape, since the protective resist layer 5 exists only on one side of the base tape 1 of the TAB tape, the sealing resin 9 is hardened by heating. After cooling to room temperature, the base tape 1. Due to the difference in thermal expansion coefficient between the adhesive layer 2゜metal wiring layer 3 and the protective resist 5, warping deformation occurs along the longitudinal direction of the TAB tape concavely toward the −L side. There is.
この反り変形は、後の特性選別工程において特性測定装
置側とＴＡＢ製品側との測定時の位置合わせ精度に非常
に悪い影響を与えるという問題がある。This warping deformation has a problem in that it has a very negative effect on the alignment accuracy during measurement between the characteristic measuring device side and the TAB product side in the subsequent characteristic selection process.
また、選別後、基板に実装する際においても、基板とＴ
ＡＢ製品の接続部の位置合わせ精度に悪影響を及ぼすと
いう問題がある。In addition, even when mounting on a board after sorting, the board and T
There is a problem in that it has a negative effect on the alignment accuracy of the connecting portion of AB products.
本発明の目的は、ＴＡＢ製品における反り変形を防止し
た半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that prevents warpage in TAB products.
本発明の半導体装置は、片面に保護用レジスト層で被覆
された金属配線層を形成してなるベーステープの反対面
に、該保護用レジスト層と同材質の補正レジスト層を形
成している。In the semiconductor device of the present invention, a correction resist layer made of the same material as the protective resist layer is formed on the opposite side of a base tape formed with a metal wiring layer coated with a protective resist layer on one side.
本発明によれば、ベーステープの両面に同材質のレジス
ト層が存在するため、熱履歴を受けた際のベーステープ
における反り変形が防止される。According to the present invention, since resist layers made of the same material are present on both sides of the base tape, the base tape is prevented from warping and deforming when subjected to thermal history.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。ＴＡＢ用テ
ープは、ベーステープ１の上に接着剤層２を介して所要
パターンのシート状に形成された金属配線層３を接着さ
せている。この金属配線層３の一部は、インナリード４
としてベーステープ１の素子搭載部に設けた窓内に突出
されている。FIG. 1 is a sectional view of an embodiment of the present invention. In the TAB tape, a metal wiring layer 3 formed in a sheet shape with a desired pattern is adhered onto a base tape 1 via an adhesive layer 2. A part of this metal wiring layer 3 is connected to an inner lead 4
It protrudes into a window provided in the element mounting portion of the base tape 1.
また、ＴＡＢ製品の組立工程１選別工程、あるいは実装
工程中に塵等の付着によって金属配線層３がショートし
たり、人的起因もしくは機械的起因によるストレスによ
って破損されることのないように金属配線層３の上側に
保護用レジスト層５を形成している。In addition, the metal wiring layer 3 is designed to prevent short-circuiting due to adhesion of dust, etc. during the assembly process 1 sorting process or mounting process of TAB products, and to prevent damage to the metal wiring layer 3 due to stress caused by humans or mechanical causes. A protective resist layer 5 is formed above the layer 3.
さらに、この例では、ベーステープ１の下面にも、前記
保護用レジスト層５と同材質の補正レジスト層６を形成
している。Further, in this example, a correction resist layer 6 made of the same material as the protective resist layer 5 is also formed on the lower surface of the base tape 1.
そして、前記表面にバンプ電極８を有する半導体素子７
をベーステープ１の窓内に配置し、バンプ電極８をイン
ナーリード４に接続する。また、前記インナーリード４
および半導体素子７を含む領域に封止樹脂９を充填し、
これらを樹脂封止して半導体装置を完成している。A semiconductor element 7 having bump electrodes 8 on the surface thereof
is placed within the window of the base tape 1, and the bump electrode 8 is connected to the inner lead 4. In addition, the inner lead 4
and filling the region including the semiconductor element 7 with a sealing resin 9,
These are sealed with resin to complete the semiconductor device.
この構成の半導体装置によれば、ＴＡＢ用テープのベー
ステープ１の下側面に、上側面に塗布した保護用レジス
ト層５と同材質の補正レジスト層６を塗布しているため
、保護用レジスト層５とベーステープ１．接着剤層２．
金属配線層３との間の熱膨張係数の違いによる反り変形
を補正レジスト層６の熱膨張変形によって低減すること
ができる。したがって、後の、特性選別工程において特
性測定装置側とＴＡＢ製品側との測定時の位置合わせ精
度に悪影響を与えることはなく、また、選別後、基板に
実装する際においても、基板とＴＡＢ製品の接続部の位
置合わせ精度に悪影響を与えることがない。According to the semiconductor device having this configuration, since the correction resist layer 6 made of the same material as the protective resist layer 5 applied to the upper surface is applied to the lower surface of the base tape 1 of the TAB tape, the protective resist layer 6 5 and base tape 1. Adhesive layer 2.
Warpage deformation due to a difference in thermal expansion coefficient between the correction resist layer 6 and the metal wiring layer 3 can be reduced by thermal expansion deformation of the correction resist layer 6. Therefore, there is no adverse effect on the alignment accuracy during measurement between the characteristic measuring device side and the TAB product side in the later characteristic selection process. There is no adverse effect on the positioning accuracy of the connecting parts.
なお、補正レジスト層６を塗布する面積と厚さを保護用
レジスト層５と同等にすれば、レジスト塗布用マスクは
共用することができる。また、ベーステープ１と接着剤
層２と金属配線層３間の熱膨張係数の違いにより発生ず
る反り変形も考慮に入れて、補正レジスト層６の面積、
厚みを加減してもよい。Note that if the area and thickness to which the correction resist layer 6 is applied are made to be the same as those of the protective resist layer 5, the resist application mask can be shared. In addition, the area of the correction resist layer 6 is
The thickness may be adjusted.
ここで、補正レジ１１〜層６を保護用レジスト層５と同
面積、同厚さに設けたＴＡＢ用テープについて実験を行
った結果は、次表の通りであり、著しい効果が得られる
ことが確認された。Here, the results of an experiment conducted on a TAB tape in which the correction resist layers 11 to 6 were provided in the same area and thickness as the protective resist layer 5 are as shown in the table below, and it was found that a remarkable effect could be obtained. confirmed.
なお、ベーステープ素材はポリイミドで、厚さ７５μｍ
、３５ｍｍ幅のものを１８５ｍｍ長に切断した。The base tape material is polyimide and has a thickness of 75 μm.
, 35 mm width was cut into 185 mm length.
以」二説明したように本発明は、片面に保護用しシスト
層で被覆された金属配線層を形成しているベーステープ
の反対面に、保護用レジスト層と同材質の補正レンスＩ
〜層を形成しているので、ベーステープの両面に存在さ
れる同材質のレジスト層によって、熱履歴を受＆Ｊた際
のベーステープにおける反り変形が防止され、ＴＡＢ用
テープを用いた半導体装置の信転性を向上させることが
できる効果がある。As explained above, the present invention provides a base tape having a protective metal wiring layer covered with a cyst layer on one side, and a correction lens I made of the same material as the protective resist layer on the opposite side.
The resist layer made of the same material on both sides of the base tape prevents the base tape from warping and deforming when exposed to heat history, making it easier for semiconductor devices using TAB tape to form. It has the effect of improving credibility.
第１図は本発明の半導体装置の一実施例の断面図、第２
図は従来の半導体装置の断面図である。
１・・・ベーステープ、２・・・接着剤層、３・・・金
属配線層、４・・・インナーリード、５・・・保護レジ
スト層、６・・・補正レジスト層、７・・・半導体素子
、８・・・バンブ電極、９・・・封止樹脂。FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention, and FIG.
The figure is a cross-sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Base tape, 2... Adhesive layer, 3... Metal wiring layer, 4... Inner lead, 5... Protective resist layer, 6... Correction resist layer, 7... Semiconductor element, 8... bump electrode, 9... sealing resin.
Claims (1)
た金属配線層を形成し、この金属配線層に半導体素子を
接続してなるＴＡＢ構造の半導体装置において、前記保
護用レジスト層と同材質の補正レジスト層を前記ベース
テープの反対面に形成したことを特徴とする半導体装置
。1. In a semiconductor device with a TAB structure in which a metal wiring layer covered with a protective resist layer is formed on one side of a base tape and a semiconductor element is connected to this metal wiring layer, A semiconductor device characterized in that a correction resist layer is formed on the opposite surface of the base tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2133202A JP2833152B2 (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2133202A JP2833152B2 (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0428244A true JPH0428244A (en) | 1992-01-30 |
| JP2833152B2 JP2833152B2 (en) | 1998-12-09 |
Family
ID=15099120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2133202A Expired - Lifetime JP2833152B2 (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2833152B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491412B1 (en) * | 2001-08-20 | 2005-05-25 | 미츠이 긴조쿠 고교 가부시키가이샤 | Laminate film for mounting electronic devices and film carrier tape for mounting electronic devices |
| KR20060057840A (en) * | 2004-11-24 | 2006-05-29 | 삼성테크윈 주식회사 | Tape chip carrier and the semiconductor package using the same |
-
1990
- 1990-05-23 JP JP2133202A patent/JP2833152B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491412B1 (en) * | 2001-08-20 | 2005-05-25 | 미츠이 긴조쿠 고교 가부시키가이샤 | Laminate film for mounting electronic devices and film carrier tape for mounting electronic devices |
| KR20060057840A (en) * | 2004-11-24 | 2006-05-29 | 삼성테크윈 주식회사 | Tape chip carrier and the semiconductor package using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2833152B2 (en) | 1998-12-09 |
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