JP2001044248A - Tab tape with stiffner and bga semiconductor package using the same - Google Patents
Tab tape with stiffner and bga semiconductor package using the sameInfo
- Publication number
- JP2001044248A JP2001044248A JP11220935A JP22093599A JP2001044248A JP 2001044248 A JP2001044248 A JP 2001044248A JP 11220935 A JP11220935 A JP 11220935A JP 22093599 A JP22093599 A JP 22093599A JP 2001044248 A JP2001044248 A JP 2001044248A
- Authority
- JP
- Japan
- Prior art keywords
- stiffener
- tab tape
- semiconductor element
- tape
- bga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はスティフナ付きＴＡ
Ｂテープおよびそれを用いたＢＧＡ半導体パッケージに
関し、特に、半導体素子、ＴＡＢテープおよびスティフ
ナを具えたtape−ＢＧＡ半導体パッケージに関する。TECHNICAL FIELD The present invention relates to a TA with a stiffener.
The present invention relates to a B-tape and a BGA semiconductor package using the same, and more particularly to a tape-BGA semiconductor package including a semiconductor element, a TAB tape and a stiffener.
【０００２】[0002]
【従来の技術】図３にＴＡＢテープを用いたtape−ＢＧ
Ａパッケージを示す。 tape −ＢＧＡパッケージの主体
は、絶縁層１の各面に配線層２と接着層３を有するＴＡ
Ｂテープ１Ａと、その開口部１ａの部分においてスティ
フナ５３に接着層６を介して接着された半導体素子４か
ら成る。絶縁体テープ１の配線層２は、半導体素子４の
バンプ７に接続され、この接続部はモールドレジン８で
封止されている。また配線層２の上には、図示しないソ
ルダーレジストを介して、はんだボール９が設けられて
いる。スティフナ５３は開口部１ａに臨む部分が高くな
っている。2. Description of the Related Art FIG. 3 shows a tape-BG using a TAB tape.
A package is shown. The main body of the tape-BGA package is a TA having a wiring layer 2 and an adhesive layer 3 on each surface of an insulating layer 1.
It comprises a B tape 1A and a semiconductor element 4 bonded to a stiffener 53 via an adhesive layer 6 at the opening 1a. The wiring layer 2 of the insulating tape 1 is connected to the bump 7 of the semiconductor element 4, and this connection is sealed with a mold resin 8. A solder ball 9 is provided on the wiring layer 2 via a solder resist (not shown). The stiffener 53 has a higher portion facing the opening 1a.
【０００３】スティフナ５３の、半導体素子４の搭載さ
れた面及びそれと反対側の面には、ニッケルめっき層３
１ａ，３１ｂがそれぞれ施されている。これらのニッケ
ルめっき層の表面は０．０５ないし０．０９の輻射能を
もっている。The nickel plating layer 3 is provided on the surface of the stiffener 53 on which the semiconductor element 4 is mounted and on the surface on the opposite side.
1a and 31b are provided respectively. The surface of these nickel plating layers has a radiation ability of 0.05 to 0.09.
【０００４】[0004]
【発明が解決しようとする課題】しかし、従来のＴＡＢ
テープのスティフナの露出面に施されたニッケルめっき
は、０．０５ないし０．０９程度の輻射能しかもたない
ため、それを用いたtape−ＢＧＡパッケージはＩＲリフ
ローの工程で、昇温がおそい。そのため、このパッケー
ジを他の品種のパッケージとともに同じ基板の上でリフ
ローを行うと、ニッケルめっきスティフナを有するtape
−ＢＧＡパッケージの温度が充分上昇したとき、同時に
処理される他のパッケージの温度が高くなり過ぎ、それ
らにリフロークラックがしばしば発生する。However, the conventional TAB
Since the nickel plating applied to the exposed surface of the tape stiffener has only a radiation ability of about 0.05 to 0.09, the temperature of the tape-BGA package using it is increased slowly in the IR reflow process. Therefore, when this package is reflowed on the same board with other types of packages, the tape with nickel plating stiffener
When the temperature of the BGA package has risen sufficiently, the temperature of the other packages being processed at the same time becomes too high and they often undergo reflow cracks.
【０００５】本発明の目的は、ＩＲリフローの工程での
昇温が速く、ＩＲリフローの工程で他の品種のパッケー
ジにリフロークラックを生じさせることのない、スティ
フナ付きＴＡＢテープおよびそれを用いたＢＧＡ半導体
パッケージを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a TAB tape with a stiffener and a BGA using the same, in which the temperature rises quickly in the IR reflow process and does not cause reflow cracks in packages of other types in the IR reflow process. It is to provide a semiconductor package.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するため、半導体素子搭載領域に形成されたインナー
リードと外部接続用はんだボールに接続されるはんだボ
ールパッドを有した配線パターンを、絶縁テープ上に形
成したＴＡＢテープと、ＴＡＢテープを第１の面に接着
するとともに、第１の面に半導体素子搭載領域を有する
スティフナを備え、スティフナは、第２の面が０．１以
上の輻射能を有するように構成されていることを特徴と
する、スティフナ付きＴＡＢテープを提供する。In order to achieve the above object, the present invention provides a wiring pattern having a solder ball pad connected to an inner lead formed in a semiconductor element mounting area and a solder ball for external connection. A TAB tape formed on an insulating tape and a stiffener having a semiconductor element mounting area on the first surface while adhering the TAB tape to the first surface, wherein the stiffener has a second surface of 0.1 or more. Provided is a TAB tape with a stiffener, wherein the TAB tape is configured to have a radiation ability.
【０００７】また、本発明は、上記目的を達成するた
め、半導体素子搭載領域に形成されたインナーリードと
外部接続用はんだボールに接続されるはんだボールパッ
ドを有した配線パターンを、絶縁テープ上に形成したＴ
ＡＢテープと、半導体素子搭載領域に搭載されてインナ
ーリードに接続された半導体素子と、半導体素子とＴＡ
Ｂテープを第１の面に接着して機械的に補強するスティ
フナと、ＴＡＢテープのはんだボールパッドに融着した
はんだボールを具え、スティフナは、第２の面が０．１
以上の輻射能を有するように構成されていることを特徴
とする、ＢＧＡ半導体パッケージを提供する。According to the present invention, in order to achieve the above object, a wiring pattern having an inner lead formed in a semiconductor element mounting area and a solder ball pad connected to a solder ball for external connection is formed on an insulating tape. T formed
AB tape, a semiconductor element mounted on the semiconductor element mounting area and connected to the inner lead,
A stiffener for bonding and mechanically reinforcing the B tape to the first surface; and a solder ball fused to a solder ball pad of the TAB tape.
A BGA semiconductor package characterized by being configured to have the above radiation ability is provided.
【０００８】スティフナの、半導体素子及びＴＡＢテー
プが接着された面（第１の面）と反対側の面( 第２の
面) は、０．２以上の輻射能を有することが好ましい。
本発明は、スティフナが高さの異なる部分を有し、半導
体素子搭載領域としてのＴＡＢテープの開口部に臨む部
分が、ＴＡＢテープが接着された部分より高い位置にあ
るような場合に、特に効果的である。[0008] The surface (second surface) of the stiffener opposite to the surface (first surface) to which the semiconductor element and the TAB tape are adhered preferably has a radiation ability of 0.2 or more.
The present invention is particularly effective when the stiffener has portions with different heights, and the portion facing the opening of the TAB tape as a semiconductor element mounting area is located at a position higher than the portion where the TAB tape is bonded. It is a target.
【０００９】スティフナの露出した面（第２の面）の輻
射能を０．１以上にするには、従来のニッケルめっきに
代わり、黒ロジウムめっき、Ｃｒ２Ｏ３めっきのほか、
Ｃｏ−Ｎｉ，Ｃｏ−Ｓｎ，Ｓｎ−Ｎｉ，Ｓｎ−Ｎｉ−
Ｓ，Ｓｎ−Ｃｏ−Ｓ，Ｓｎ−Ｎｉ−Ｃｕ，Ｓｎ−Ｎｉ−
Ｍｏ等の複成分めっき、銅酸化皮膜形成等を用いること
ができる。黒ニッケルめっきでも目的を達することがで
きる。In order to increase the radiant power of the exposed surface (second surface) of the stiffener to 0.1 or more, black rhodium plating, Cr2O3 plating,
Co-Ni, Co-Sn, Sn-Ni, Sn-Ni-
S, Sn-Co-S, Sn-Ni-Cu, Sn-Ni-
Multi-component plating of Mo or the like, formation of a copper oxide film, or the like can be used. The purpose can also be achieved with black nickel plating.
【００１０】図１は本発明によるtape−ＢＧＡ半導体パ
ッケージを示す。 tape −ＢＧＡパッケージの主体は、
絶縁層１とその各面に設けられた配線層２と接着層３か
ら成るＴＡＢテープ１Ａと、スティフナ５１と、ＴＡＢ
テープ１Ａの開口部１ａの部分においてスティフナ５１
に接着層６を介して接着された半導体素子４から成る。
テープ上の配線層２は半導体素子４のバンプ７に接続さ
れ、この接続部はモールドレジン８で封止されている。
また配線層２の上には、図示しないソルダーレジストを
介して、はんだボール９が設けられている。スティフナ
５１は開口部１ａに臨む部分が高くなっている。スティ
フナ５１の、半導体素子４が搭載された面およびそれと
反対側の面には、めっき層１１ａ，１１ｂがそれぞれ施
されている。FIG. 1 shows a tape-BGA semiconductor package according to the present invention. The main body of tape-BGA package is
A TAB tape 1A comprising an insulating layer 1, a wiring layer 2 provided on each surface thereof, and an adhesive layer 3, a stiffener 51, a TAB tape
The stiffener 51 is formed at the opening 1a of the tape 1A.
The semiconductor device 4 is bonded to the semiconductor device via an adhesive layer 6.
The wiring layer 2 on the tape is connected to a bump 7 of the semiconductor element 4, and this connection is sealed with a mold resin 8.
A solder ball 9 is provided on the wiring layer 2 via a solder resist (not shown). The stiffener 51 has a higher portion facing the opening 1a. Plating layers 11a and 11b are applied to the surface of the stiffener 51 on which the semiconductor element 4 is mounted and the surface on the opposite side, respectively.
【００１１】接着層３の厚さは、例えば、０．１ｍｍで
ある。スティフナ５１は、例えば、厚さ０．２５ｍｍの
ＯＦＣで構成される。めっき層１１ａ，１１ｂは、例え
ば、厚さ０．８マイクロメートルのＣｏ−Ｎｉ黒色電解
めっき層で、その表面は約０．９の輻射能を有してい
る。The thickness of the adhesive layer 3 is, for example, 0.1 mm. The stiffener 51 is made of, for example, an OFC having a thickness of 0.25 mm. The plating layers 11a and 11b are, for example, Co-Ni black electrolytic plating layers having a thickness of 0.8 micrometers, and their surfaces have a radiation ability of about 0.9.
【００１２】図２は、本発明によるtape−ＢＧＡ半導体
パッケージの別の形態を示す。スティフナ５２と皮膜２
１以外は図１と同様であり、説明を省略する。スティフ
ナ５２の、半導体素子４が搭載された面と反対側の面
は、黒色顔料を含むエポキシ皮膜２１で被覆されてい
る。この皮膜の厚さは１０マイクロメートルで、皮膜の
表面は約０．９以上の輻射能を有している。FIG. 2 shows another embodiment of the tape-BGA semiconductor package according to the present invention. Stiffener 52 and coating 2
Other than 1 is the same as FIG. 1 and the description is omitted. The surface of the stiffener 52 opposite to the surface on which the semiconductor element 4 is mounted is covered with the epoxy film 21 containing a black pigment. The thickness of this film is 10 micrometers, and the surface of the film has an emissivity of about 0.9 or more.
【００１３】本発明は、ＴＡＢテープを用いたＣＳＰに
も適用できる。The present invention can be applied to a CSP using a TAB tape.
【００１４】[0014]
【発明の効果】本発明によると、ＩＲリフローの工程で
の昇温が速く、ＩＲリフローの工程で他の品種のパッケ
ージにリフロークラックを生じさせることのない、ステ
ィフナ付きＴＡＢテープおよびそれを用いたＢＧＡパッ
ケージが提供される。この効果は、本発明のtape−ＢＧ
Ａパッケージにおいて、スティフナの第２の面（半導体
素子及びＴＡＢテープが接着された面と反対側の面) が
０．１以上の輻射能を有することによる。According to the present invention, a TAB tape with a stiffener and a TAB tape with a stiffener which does not cause a reflow crack in a package of another kind in the IR reflow process at a high temperature in the IR reflow process. A BGA package is provided. This effect is due to the tape-BG of the present invention.
This is because in the A package, the second surface of the stiffener (the surface opposite to the surface to which the semiconductor element and the TAB tape are bonded) has a radiation ability of 0.1 or more.
【図１】本発明によるtape−ＢＧＡ半導体パッケージの
説明図。FIG. 1 is an explanatory diagram of a tape-BGA semiconductor package according to the present invention.
【図２】本発明によるtape−ＢＧＡ半導体パッケージの
説明図。FIG. 2 is an explanatory diagram of a tape-BGA semiconductor package according to the present invention.
【図３】従来のtape−ＢＧＡ半導体パッケージの説明
図。FIG. 3 is an explanatory diagram of a conventional tape-BGA semiconductor package.
１ 絶縁層 １Ａ ＴＡＢテープ １ａ 開口部 ２ 配線層 ３ 接着層 ４ 半導体素子 ６ 接着層 ７ バンプ ８ モールドレジン ９ はんだボール １１ａ，１１ｂ めっき層 ２１ 皮膜 ３１ａ，３１ｂ ニッケルめっき層 ５１ スティフナ ５２ スティフナ ５３ スティフナ DESCRIPTION OF SYMBOLS 1 Insulating layer 1A TAB tape 1a Opening 2 Wiring layer 3 Adhesive layer 4 Semiconductor element 6 Adhesive layer 7 Bump 8 Mold resin 9 Solder ball 11a, 11b Plating layer 21 Film 31a, 31b Nickel plating layer 51 Stiffener 52 Stiffener 53 Stiffener
Claims (6)
ーリードと外部接続用はんだボールに接続されるはんだ
ボールパッドを有した配線パターンを、絶縁テープ上に
形成したＴＡＢテープと、 前記ＴＡＢテープを第１の面に接着するとともに、前記
第１の面に半導体素子搭載領域を有するスティフナを備
え、 前記スティフナは、第２の面が０．１以上の輻射能を有
するように構成されていることを特徴とする、スティフ
ナ付きＴＡＢテープ。1. A TAB tape formed on an insulating tape, a wiring pattern having an inner lead formed in a semiconductor element mounting region and a solder ball pad connected to a solder ball for external connection, and a TAB tape formed on an insulating tape. A stiffener having a semiconductor element mounting region on the first surface, wherein the stiffener is configured such that the second surface has a radiation ability of 0.1 or more. Features TAB tape with stiffener.
ーリードと外部接続用はんだボールに接続されるはんだ
ボールパッドを有した配線パターンを、絶縁テープ上に
形成したＴＡＢテープと、 前記半導体素子搭載領域に搭載されて前記インナーリー
ドに接続された半導体素子と、 前記半導体素子と前記ＴＡＢテープを第１の面に接着し
て機械的に補強するスティフナと前記ＴＡＢテープの前
記はんだボールパッドに融着したはんだボールを具え、 前記スティフナは、第２の面が０．１以上の輻射能を有
するように構成されていることを特徴とする、ＢＧＡ半
導体パッケージ。2. A TAB tape in which a wiring pattern having an inner lead formed in a semiconductor element mounting area and a solder ball pad connected to a solder ball for external connection is formed on an insulating tape; A semiconductor element mounted on the inner lead and connected to the inner lead; a stiffener for bonding the semiconductor element and the TAB tape to a first surface to mechanically reinforce the semiconductor element and the TAB tape; A BGA semiconductor package comprising a solder ball, wherein the stiffener is configured such that the second surface has a radiation ability of 0.1 or more.
載領域として開口部を有し、 前記スティフナは、前記半導体素子を収容して接着する
凹部を有する構成の、請求項２のＢＧＡ半導体パッケー
ジ。3. The BGA semiconductor package according to claim 2, wherein said TAB tape has an opening as said semiconductor element mounting area, and said stiffener has a recess for accommodating and bonding said semiconductor element.
キシ樹脂と黒色顔料から成る有機皮膜で被覆されている
構成の、請求項２または３のＢＧＡ半導体パッケージ。4. The BGA semiconductor package according to claim 2, wherein said stiffener is configured such that said second surface is covered with an organic film made of an epoxy resin and a black pigment.
色の外観を有する金属めっき層または銅の酸化皮膜で被
覆されている構成の、請求項２のＢＧＡ半導体パッケー
ジ。5. The BGA semiconductor package according to claim 2, wherein said stiffener is configured such that said second surface is covered with a metal plating layer having a black appearance or a copper oxide film.
ｒ２Ｏ３、Ｃｏ−Ｎｉ，Ｃｏ−Ｓｎ，Ｓｎ−Ｎｉ，Ｓｎ
−Ｎｉ−Ｓ，Ｓｎ−Ｃｏ−Ｓ，Ｓｎ−Ｎｉ−Ｃｕもしく
はＳｎ−Ｎｉ−Ｍｏから成るめっき層、又は黒ロジウム
もしくは黒ニッケルめっき層から成る構成の、請求項
２、３又は５のＢＧＡ半導体パッケージ。6. The stiffener according to claim 5, wherein the second surface is C
r2O3, Co-Ni, Co-Sn, Sn-Ni, Sn
The BGA semiconductor according to claim 2, 3 or 5, wherein the BGA semiconductor has a plating layer made of -Ni-S, Sn-Co-S, Sn-Ni-Cu or Sn-Ni-Mo, or a black rhodium or nickel plating layer. package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11220935A JP2001044248A (en) | 1999-08-04 | 1999-08-04 | Tab tape with stiffner and bga semiconductor package using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11220935A JP2001044248A (en) | 1999-08-04 | 1999-08-04 | Tab tape with stiffner and bga semiconductor package using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001044248A true JP2001044248A (en) | 2001-02-16 |
Family
ID=16758873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11220935A Pending JP2001044248A (en) | 1999-08-04 | 1999-08-04 | Tab tape with stiffner and bga semiconductor package using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001044248A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6562661B2 (en) | 2000-02-24 | 2003-05-13 | Micron Technology, Inc. | Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same |
| JP2005340596A (en) * | 2004-05-28 | 2005-12-08 | Toppan Printing Co Ltd | Compound stiffener and substrate for semiconductor device as well as semiconductor device equipped therewith |
-
1999
- 1999-08-04 JP JP11220935A patent/JP2001044248A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6562661B2 (en) | 2000-02-24 | 2003-05-13 | Micron Technology, Inc. | Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same |
| US6740962B1 (en) * | 2000-02-24 | 2004-05-25 | Micron Technology, Inc. | Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same |
| US6746899B2 (en) | 2000-02-24 | 2004-06-08 | Micron Technology, Inc. | Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same |
| US6900078B2 (en) | 2000-02-24 | 2005-05-31 | Micron Technology, Inc. | Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same |
| US7029954B2 (en) | 2000-02-24 | 2006-04-18 | Micron Technology, Inc. | Tape stiffener, semiconductor device component assemblies including same, and stereolithographic methods for fabricating same |
| US7189600B2 (en) | 2000-02-24 | 2007-03-13 | Micron Technology, Inc. | Methods for fabricating stiffeners for flexible substrates |
| JP2005340596A (en) * | 2004-05-28 | 2005-12-08 | Toppan Printing Co Ltd | Compound stiffener and substrate for semiconductor device as well as semiconductor device equipped therewith |
| JP4599891B2 (en) * | 2004-05-28 | 2010-12-15 | 凸版印刷株式会社 | Semiconductor device substrate and semiconductor device |
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