JPH04277689A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH04277689A
JPH04277689A JP3968491A JP3968491A JPH04277689A JP H04277689 A JPH04277689 A JP H04277689A JP 3968491 A JP3968491 A JP 3968491A JP 3968491 A JP3968491 A JP 3968491A JP H04277689 A JPH04277689 A JP H04277689A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
hole
holes
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3968491A
Other languages
Japanese (ja)
Inventor
Kunihiro Tanaka
國弘 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3968491A priority Critical patent/JPH04277689A/en
Publication of JPH04277689A publication Critical patent/JPH04277689A/en
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE:To prevent the positional divergence between an inspection pin to be positioned by a positioning hole and a minute pin and prevent the contact error of the inspection pin by removing the divergence between the position of the pad and the positioning hole. CONSTITUTION:Conductive layers are made on both sides of an insulating substrate 1, and wiring, a pad, and hole position patterns 11a, 11b, and 11c are provided. Next, positioning holes 13a, 13b, and 13c are provided according to the respective centers of the hole position patterns 11a, 11b, and 11c.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、印刷配線板の製造方法
に関し、特に高密度配線パターンを有する印刷配線板の
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board having a high-density wiring pattern.

【0002】0002

【従来の技術】従来の印刷配線板は図5(a)に示すよ
うに、絶縁基板1の両面に銅箔2を設けた銅張り積層板
にスルーホール3と位置決め穴4を形成する。
2. Description of the Related Art In a conventional printed wiring board, as shown in FIG. 5(a), through holes 3 and positioning holes 4 are formed in a copper-clad laminate in which copper foil 2 is provided on both sides of an insulating substrate 1.

【0003】次に、図5(b)に示すように、絶縁基板
1の全面に銅層をめっきして導電層5を形成する。
Next, as shown in FIG. 5(b), a conductive layer 5 is formed by plating a copper layer over the entire surface of the insulating substrate 1.

【0004】次に、図5(c),(d)に示すように、
導電層5の両面に選択的にエッチングレジスト層を形成
した後、エッチングレジスト層をマスクとして導電層5
、及び銅箔2を順次エッチング除去して配線6を形成し
た後、エッチングレジスト層を剥離除去し、絶縁基板1
の両面の所望部分にソルダーレジスト層を形成し、印刷
配線板を構成していた。
Next, as shown in FIGS. 5(c) and 5(d),
After selectively forming an etching resist layer on both sides of the conductive layer 5, the conductive layer 5 is etched using the etching resist layer as a mask.
, and the copper foil 2 to form the wiring 6, the etching resist layer is peeled off and the insulating substrate 1 is removed.
A solder resist layer was formed on desired portions of both sides of the printed wiring board.

【0005】図6は従来の印刷配線板を説明するための
部分拡大平面図である。
FIG. 6 is a partially enlarged plan view for explaining a conventional printed wiring board.

【0006】図6に示すように、スルーホール3及び位
置決め穴に対する配線パターンの位置合わせがずれると
、パッド12の位置も位置決め穴に対してずれを生ずる
As shown in FIG. 6, when the wiring pattern is misaligned with the through hole 3 and the positioning hole, the position of the pad 12 also becomes misaligned with the positioning hole.

【0007】[0007]

【発明が解決しようとする課題】近年、印刷配線板表面
実装技術の進展と実装部品の小型化によりパッドの微小
化及びパッドのピッチの縮小化が進んでおり、印刷配線
板位置決め穴と配線パターンの位置ずれが発生しやすく
、現状の配線パターンの電気検査装置では上面のみパタ
ーン認識による位置ずれ補正が可能であるが、下面側は
位置決め穴を基準として検査ピンが配置されるため、検
査ピンと回路パターンの位置補正ができず、図6に示す
ように、検査ピン20と特にパッド12の接触不良が発
生しやすく配線パターンの電気検査の効率が悪くなると
いう問題点があった。
[Problems to be Solved by the Invention] In recent years, with the advancement of printed wiring board surface mounting technology and the miniaturization of mounted components, pads have become smaller and the pad pitch has become smaller. Current electrical inspection equipment for wiring patterns can correct positional deviations by pattern recognition only on the top surface, but on the bottom surface, inspection pins are placed based on the positioning holes, so the inspection pins and circuits are easily misaligned. The position of the pattern cannot be corrected, and as shown in FIG. 6, poor contact between the test pins 20 and especially the pads 12 is likely to occur, resulting in a problem that the efficiency of electrical testing of the wiring pattern is reduced.

【0008】[0008]

【課題を解決するための手段】本発明のプリント配線板
の製造方法は、絶縁基板の両面に銅箔を設けた銅張り積
層板に選択的にスルーホールを設け前記スルーホールを
含む表面にめっき法により導電層を形成する工程と、前
記導電層をパターニングして配線及び位置決め穴形成用
の穴位置パターンを形成する工程と、前記穴位置パター
ンの中心に合わせて位置決め穴を形成する工程とを含ん
で構成される。
[Means for Solving the Problems] The method for manufacturing a printed wiring board of the present invention includes selectively forming through holes in a copper-clad laminate having copper foil provided on both sides of an insulating substrate, and plating the surface including the through holes. a step of forming a conductive layer by a method, a step of patterning the conductive layer to form a hole position pattern for forming wiring and positioning holes, and a step of forming a positioning hole in alignment with the center of the hole position pattern. It consists of:

【0009】[0009]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【0010】図1(a)〜(d)及び図2は本発明の第
1の実施例を説明するための工程順に示した断面図及び
平面図である。
1(a) to 1(d) and FIG. 2 are sectional views and plan views showing the steps of the first embodiment of the present invention.

【0011】まず、図1(a)に示すように、絶縁基板
1の両面に銅箔2を設けた銅張り積層板に選択的にスル
ーホール3を設ける。
First, as shown in FIG. 1(a), through holes 3 are selectively provided in a copper-clad laminate in which copper foils 2 are provided on both sides of an insulating substrate 1.

【0012】次に、図1(b)に示すように、めっき法
によりスルーホール3の側壁を含む銅箔2の表面に銅層
等の導電層5を形成する。
Next, as shown in FIG. 1B, a conductive layer 5 such as a copper layer is formed on the surface of the copper foil 2 including the side walls of the through holes 3 by plating.

【0013】次に、図1(c)に示すように、銅張り積
層板の両面の導電層5の表面にエッチングレジスト層を
形成してパターニングし、エッチングレジスト層をマス
クとして導電層5、及び銅箔2を順次エッチング除去し
た後、エッチングレジスト層を剥離除去し、図1(c)
に示すように位置決め穴形成用の穴位置パターン11a
,11b,11c及び配線6を形成する。
Next, as shown in FIG. 1(c), an etching resist layer is formed and patterned on the surface of the conductive layer 5 on both sides of the copper-clad laminate, and the conductive layer 5 and the conductive layer 5 are patterned using the etching resist layer as a mask. After sequentially etching away the copper foil 2, the etching resist layer is peeled off and removed, as shown in FIG. 1(c).
Hole position pattern 11a for forming positioning holes as shown in FIG.
, 11b, 11c and wiring 6 are formed.

【0014】次に、図2に示すように、穴位置パターン
11a,11b,11cの各中心に合わせてパターン認
識付穴あけ機により位置決め穴13a,13b,13c
を設け、印刷配線板を構成する。
Next, as shown in FIG. 2, positioning holes 13a, 13b, 13c are formed by a hole punching machine with pattern recognition in alignment with the centers of the hole position patterns 11a, 11b, 11c.
are provided to constitute a printed wiring board.

【0015】図3は本発明の第1の実施例を説明するた
めの部分拡大平面図である。
FIG. 3 is a partially enlarged plan view for explaining the first embodiment of the present invention.

【0016】図3に示すように、スルーホール3の位置
と配線6の相対位置が設計値からずれて形成された場合
でも位置決め穴を穴位置パターンの中心に合わせて形成
しているため、位置決め穴により接触位置が設定される
検査ピン20とパッド12との位置ずれを無くして安定
した接触が得られる。
As shown in FIG. 3, even if the relative position of the through hole 3 and the wiring 6 are formed deviating from the design value, the positioning hole is formed to match the center of the hole position pattern, so the positioning is easy. Stable contact can be obtained by eliminating misalignment between the test pin 20 and the pad 12, the contact position of which is set by the hole.

【0017】図4は本発明の第2の実施例を示す部分拡
大平面図である。
FIG. 4 is a partially enlarged plan view showing a second embodiment of the present invention.

【0018】図4に示すように、第1の実施例と同様の
工程により図1(d)に示す穴位置パターン11aを形
成した後、穴位置パターン11aを含む表面に選択的に
ソルダーレジスト膜15を形成する。ここで、ソルダー
レジスト膜15の位置ずれを生じ穴位置パターン11a
の一部がソルダーレージスト膜15により被覆されるが
、ソルダーレジスト膜15から露出している部分の穴位
置パターン11aの中心に位置決め穴13aを形成する
ことにより、配線とソルダーレジスト膜15の両方の位
置ずれを加味して補正した印刷配線板を構成できる利点
がある。
As shown in FIG. 4, after the hole position pattern 11a shown in FIG. 1(d) is formed by the same process as in the first embodiment, a solder resist film is selectively applied to the surface including the hole position pattern 11a. form 15. Here, the positional shift of the solder resist film 15 occurs and the hole position pattern 11a
is partially covered with the solder resist film 15, but by forming the positioning hole 13a at the center of the hole position pattern 11a in the part exposed from the solder resist film 15, both the wiring and the solder resist film 15 are covered. There is an advantage that a printed wiring board can be constructed that is corrected by taking into account the positional deviation.

【0019】[0019]

【発明の効果】以上説明したように本発明は配線パター
ン形成後に穴位置パターンを基準として印刷配線板の位
置決め穴加工を行なう為、スルーホールと配線パターン
の位置ずれが生じても配線パターンの電気的検査を行な
う際の検査ピンとパッドとの位置ずれを無くして安定し
た接触が得られ、電気的検査の信頼性を向上できるとい
う効果を有する。
Effects of the Invention As explained above, the present invention processes the positioning holes on the printed wiring board based on the hole position pattern after the wiring pattern is formed, so even if there is a misalignment between the through hole and the wiring pattern, the wiring pattern's electrical This has the effect of eliminating misalignment between the test pins and pads during electrical testing, allowing stable contact to be obtained, and improving the reliability of electrical testing.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の第1の実施例を説明するための工程順
に示した断面図及び平面図である。
FIG. 1 is a sectional view and a plan view showing the order of steps for explaining a first embodiment of the present invention.

【図2】本発明の第1の実施例を説明するための工程順
に示した断面図及び平面図であ。
FIG. 2 is a sectional view and a plan view showing the order of steps for explaining the first embodiment of the present invention.

【図3】本発明の第1の実施例を説明するための部分拡
大平面図である。
FIG. 3 is a partially enlarged plan view for explaining the first embodiment of the present invention.

【図4】本発明の第2の実施例を説明するための部分拡
大平面図である。
FIG. 4 is a partially enlarged plan view for explaining a second embodiment of the present invention.

【図5】従来の印刷配線板の製造方法を説明するための
工程順に示した断面図及び平面図である。
FIG. 5 is a cross-sectional view and a plan view showing the order of steps for explaining a conventional printed wiring board manufacturing method.

【図6】従来の印刷配線板を説明するための部分拡大平
面図である。
FIG. 6 is a partially enlarged plan view for explaining a conventional printed wiring board.

【符号の説明】[Explanation of symbols]

1    絶縁基板 2    銅箔 3    スルーホール 4    位置決め穴 5    導電層 6    配線 11a,11b,11c    穴位置パターン12 
   パッド 13a,13b,13c    位置決め穴15   
 ソルダーレジスト膜 20    検査ピン位置
1 Insulating substrate 2 Copper foil 3 Through hole 4 Positioning hole 5 Conductive layer 6 Wiring 11a, 11b, 11c Hole position pattern 12
Pads 13a, 13b, 13c Positioning holes 15
Solder resist film 20 Inspection pin position

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  絶縁基板の両面に銅箔を設けた銅張り
積層板に選択的にスルーホールを設け前記スルーホール
を含む表面にめっき法により導電層を形成する工程と、
前記導電層をパターニングして配線及び位置決め穴形成
用の穴位置パターンを形成する工程と、前記穴位置パタ
ーンの中心に合わせて位置決め穴を形成する工程とを含
むことを特徴とする印刷配線板の製造方法。
1. A step of selectively forming through holes in a copper-clad laminate in which copper foil is provided on both sides of an insulating substrate, and forming a conductive layer on the surface including the through holes by a plating method;
A printed wiring board comprising the steps of patterning the conductive layer to form a hole position pattern for forming wiring and positioning holes, and forming positioning holes in alignment with the center of the hole position pattern. Production method.
JP3968491A 1991-03-06 1991-03-06 Manufacture of printed wiring board Pending JPH04277689A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3968491A JPH04277689A (en) 1991-03-06 1991-03-06 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3968491A JPH04277689A (en) 1991-03-06 1991-03-06 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPH04277689A true JPH04277689A (en) 1992-10-02

Family

ID=12559903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3968491A Pending JPH04277689A (en) 1991-03-06 1991-03-06 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPH04277689A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107509304A (en) * 2017-08-02 2017-12-22 深圳市景旺电子股份有限公司 A kind of method of flexible electric circuit board reinforcement steel disc

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107509304A (en) * 2017-08-02 2017-12-22 深圳市景旺电子股份有限公司 A kind of method of flexible electric circuit board reinforcement steel disc
CN107509304B (en) * 2017-08-02 2019-09-13 深圳市景旺电子股份有限公司 A kind of method of flexible electric circuit board reinforcement steel disc

Similar Documents

Publication Publication Date Title
KR100783340B1 (en) Method for production of interposer for mounting semiconductor element
KR101068539B1 (en) Method of manufacturing a wiring board by utilizing electro plating
JP4792673B2 (en) Manufacturing method of high-density multilayer build-up wiring board
JP5176643B2 (en) Multilayer circuit board manufacturing method
KR20020050704A (en) Flexible wiring boards and manufacturing processes thereof
JP2002190674A (en) Method for manufacturing multilayer flexible circuit board
JPH04277689A (en) Manufacture of printed wiring board
JP2001358257A (en) Method for manufacturing substrate for semiconductor device
JP2000091722A (en) Printed wiring board and its manufacture
JP2003142823A (en) Manufacturing method for both-sided flexible circuit board
JPH06334067A (en) Multilayer printed wiring board and production thereof
JP2002290044A (en) Multilayer printed wiring board and manufacturing method thereof
KR100652132B1 (en) Printed circuit board and Method of manufacturing the same
JPH0222890A (en) Flexible printed wiring board and connection thereof
JP4252227B2 (en) Manufacturing method of double-sided flexible circuit board
JP2005229008A (en) Printed wiring board and its manufacturing method
JP2004079703A (en) Multilayer substrate and manufacturing method of same
JPH0567871A (en) Printed-wiring board and manufacture thereof
JP2002064160A (en) Method of forming conductive pattern
JPH03272194A (en) Manufacture of multilayer printed wiring board
JP2001053189A (en) Wiring board and manufacturing method thereof
JPH0444292A (en) Printed wiring board and its manufacture
JPH03205896A (en) Manufacture of multilayer printed circuit board
JP2000133914A (en) Printed wiring board and manufacture thereof
JPH03225992A (en) Surface mount printed circuit board and its manufacture