JP2005229008A - Printed wiring board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board which can readily reproduce fine patterns, even if copper foil of ordinary thickness is used by setting the prescribed region of a wiring layer between solder ball connection terminals and between lands, an inner lead and a connection terminal for a semiconductor element as a fined region, by applying thin-film treatment for the film thickness on this region, and to provide its manufacturing method. <P>SOLUTION: The printed board is formed, by forming the solder ball connection terminal, the land, the wiring layer, the inner lead and the connection terminal for a semiconductor element or the like on an insulating base material. The region, wherein the wiring layer between the connection terminals for a solder ball and between the lands, the inner lead and the connection terminal for a semiconductor element are constituted of a finer pattern than other wiring layers, is set as a fined region. The film thickness and line width of the wiring layer, the inner lead and the connection terminal for a semiconductor element of the fined region are formed thinner and finer than the film thickness of a wiring layer, except for the fined region in the printed wiring board. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a printed wiring board having fine wirings for manufacturing semiconductor devices for various electronic devices.

  A conventional printed wiring board includes a wiring layer having a uniform thickness and connection terminals in the same wiring layer, and a wiring layer having a substantially uniform thickness is formed by etching a copper foil having a uniform thickness or plating. Also, it is common that only the connection terminal part is plated with noble metal to provide a thickness difference of several μm. However, the thickness of the conductor layer itself made of copper or the like forming the wiring layer and the connection terminal is basic. The same is true.

  Recently, a semiconductor element connection terminal portion formed with a thin thickness, or a structure in which a recess is formed in the land for the purpose of improving the bondability of an interlayer connection land of a multilayer wiring board has been proposed (for example, (See Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4.)

  Patent Document 1 relates to a tape for COF, by extending the tip of the inner lead, forming a semiconductor element connection terminal wider than the lead, and lowering the height if necessary. It is intended to prevent peeling of the tip of the connection terminal when bonding semiconductor elements face down, to prevent destabilization of bonding due to lead deformation in the bonding region, and to prevent short circuits.

  In Patent Document 2, in order to reinforce the connection of solder bumps, a spherical concave portion is provided on a solder joint pad.

  Patent Document 3 discloses that in a multilayer wiring board in which electrical connection of interlayer wiring layers is performed by pressure bonding of conductive bumps, a crimp bonding surface is provided in the pressure bonding area of the wiring pattern in order to ensure interlayer connection of the multilayer wiring board. Smaller bump bonding recesses are provided.

In Patent Document 4, a recess is formed in a part of the lead line of the connection pad, and the recess and its vicinity are covered with a reinforcing film. Therefore, when the IC chip is mounted by a flip chip method, the molten solder is caused by surface tension. The connection pad is prevented from flowing out from the connection pad to the lead wire, and the mechanical strength of the connection pad and the lead wire in the vicinity thereof can be increased.
Japanese Patent Laid-Open No. 2003-249592 JP 2002-290022 A JP 2002-252467 A Japanese Patent Laid-Open No. 7-142849

In the conventional printed wiring board manufacturing technology, the wiring layer, the inner lead, and the connection terminal for the semiconductor element are made of copper foil having the same thickness, so the fine pattern forming part and the other part must be manufactured under the same conditions. Therefore, it was necessary to optimize the design of the original plate for pattern formation according to the product type. However, as finer processing advances and the pitch of the wiring layer is refined from 50 μm pitch to 40 μm pitch, a method of selecting a thin copper foil in accordance with a fine pattern has become common.

  For example, it is necessary to use a 15 μm copper foil, a 12 μm copper foil, or a 9 μm copper foil depending on the pattern pitch and line width with respect to a commonly used copper foil of 18 μm. . If there are several types of materials with different copper foil thicknesses, there is a high possibility that they will be used by mistake, and if the differences in size are included, the types will become enormous, making procurement and storage management difficult. Therefore, it is required to reduce the types of materials.

  And it is necessary to optimize the dummy pattern such as adjustment of side etch amount at the time of etching and serif etc. for the wiring layer with high difficulty that has to be manufactured by changing the thickness of the copper foil, For this purpose, it is necessary to repeat the fabrication of the mask for forming the wiring pattern and the actual measurement of the finished wiring layer by the trial production several times, and the period from the first trial production to the mass production tends to be long.

  Further, since the connection terminals for the semiconductor elements and the connection terminals for the solder balls are likely to crack in the wiring around the connection terminals, the strength required to withstand connection and subsequent use is required. However, if a fine pattern forming portion exists, a thin copper foil corresponding to the fine pattern forming portion must be used. If it does so, there exists a problem that the intensity | strength of the connecting terminal for solder balls is not fully obtained.

  The present invention has been devised in view of the above problems, and a predetermined region of a wiring layer between solder ball connection terminals and between lands, an inner lead and a connection terminal for a semiconductor element is set as a refined region, and a film in the region is formed. An object of the present invention is to provide a printed wiring board capable of easily reproducing a fine pattern even when a copper foil having a normal thickness is used by thinning the thickness, and a manufacturing method thereof.

  In order to achieve the above object, according to the first aspect of the present invention, in claim 1, a solder ball connection terminal, a land, a wiring layer, an inner lead, a semiconductor element connection terminal, and the like are formed on an insulating substrate. An area in which the wiring layers between the solder ball connection terminals and between the lands, the inner leads, and the connection terminals for semiconductor elements are configured with a finer pattern than the other wiring layers is set as a refinement area. Further, the film thickness and the line width of the wiring layer, the inner lead, and the connection terminal for the semiconductor element in the fine region are thinner and thinner than the film thickness of the wiring layer other than the fine region. It is a printed wiring board.

  According to a second aspect of the present invention, there is provided a step of forming a semiconductor element connection terminal at least on an insulating base material, on a land, a solder ball connection terminal, a wiring layer, an inner lead, and a tip portion of the inner lead; A step of setting a predetermined region of the wiring layer, the wiring layer between the solder ball connection terminals, the inner lead, and the connection terminal for the semiconductor element as a refined region; and a step of forming a resist pattern in a region excluding the refined region; 2. The method of manufacturing a printed wiring board according to claim 1, further comprising: etching a predetermined amount of a wiring layer, an inner lead, and a semiconductor element connection terminal in a finer region using the resist pattern as a mask. It is a thing.

  The printed wiring board of the present invention eliminates the need to optimize the design of the pattern forming original plate according to the product type even if a fine pattern is partially present, and can greatly shorten the period from trial production to mass production. it can. And even if fine pattern refinement further progresses, it becomes unnecessary to select a thin copper foil in accordance with the pattern.

  In addition, since it is not necessary to prepare several kinds of materials with slightly different copper foil thicknesses, there is no possibility of using the materials by mistake, and the procurement and storage management of the materials are facilitated.

  FIG. 1A is a partial schematic plan view showing an embodiment of the printed wiring board of the present invention, and FIG. 1B is a schematic plan view of FIG. FIG. 1 (c) shows a cut schematic configuration cross-sectional view, and FIG. 1 (c) shows a schematic configuration cross-sectional view of the schematic plan view of FIG. 1 (a) cut along the line BB ′. The printed wiring board of FIG. 1 (a) shows an embodiment of the printed wiring board according to claim 1, and a plurality of solder ball connecting terminals or lands are provided on an insulating base material 11 made of an insulating resin film. A wiring layer is provided, and a wiring layer 22a between solder ball connection terminals or lands 23 is set as a finer region. The wiring layer 22a is thinner and thinner than the other wiring layers 22. Has been.

  4A is a schematic plan view of a substrate for a semiconductor device showing another embodiment of the printed wiring board of the present invention, and FIG. 4B is a schematic plan view of FIG. 4A. 4C is a schematic cross-sectional view taken along the line -C '. FIG. 4C is a schematic cross-sectional view taken along the line DD' shown in FIG. FIG. 5B is a schematic plan view of the semiconductor device substrate, FIG. 5B is a schematic cross-sectional view of the schematic plan view of FIG. (C) is a schematic cross-sectional view of the schematic plan view of FIG. 5 (a) cut along the line DD ′.

  The semiconductor device substrate of FIG. 4A shows another embodiment of the printed wiring board according to claim 1, and a device hole 15 and a solder ball connection are formed on an insulating base material 11 made of an insulating resin film. The terminal 26, the inner lead 24a, and the inner lead 24a are formed with a semiconductor element connection terminal 24b at the tip thereof. As shown in FIG. 5A, the inner lead 24a and the semiconductor element connection terminal 24b are formed in a fine region. The inner lead 22a and the semiconductor element connection terminal 24b in the refined region are formed thinner and thinner than the other wiring layers.

  According to a second aspect of the present invention, there is provided a printed wiring board manufacturing method comprising: a land, a solder ball connection terminal, a wiring layer, an inner lead, and a semiconductor element connection terminal on an insulating substrate 11 made of an insulating resin film. Wiring that is formed by a known process, and the predetermined areas of the wiring layer, inner leads, and connection terminals for semiconductor elements are set as fine areas, and areas other than the fine areas are masked with a resist pattern. By etching a predetermined amount of the layer, the inner lead, and the semiconductor element connection terminal, a thinner wiring layer, the inner lead, and the semiconductor element connection terminal are formed which are thinner than the other wiring layers.

  As a result, even in the case of a printed wiring board in which a normal wiring pattern and a fine pattern are mixed, the wiring layer, the inner lead, and the semiconductor element connection terminal in the refined region are excellent in shape reproducibility.

Hereinafter, a method for manufacturing the printed wiring board shown in FIG.
FIGS. 2A to 2G and FIGS. 3A to 3G are schematic cross-sectional views of manufacturing steps of the printed wiring board according to the present invention. 2 (a) to 2 (g) are schematic cross-sectional views of FIG. 1 (a) cut along the line AA ', and FIGS. 3 (a) to 3 (g) show FIG. 1 (a) along the line BB'. The schematic structure sectional drawing cut | disconnected by is shown.

  First, an adhesive layer 12 is formed by a method such as laminating an adhesive film on an insulating base material 11 made of a polyimide film or the like, a copper foil 21 having a predetermined thickness is laminated on the adhesive layer 12, and the copper foil 21 Is produced (see FIGS. 2A and 3A).

  Next, a photosensitive layer is formed by a method such as laminating a dry film after cleaning the surface of the copper foil 21, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 31 (FIG. 2B). ) And FIG. 3B).

  Next, using the resist pattern 31 as a mask, the copper foil 21 is spray-etched using an etchant such as a ferric chloride solution (see FIGS. 2C and 3C), and the resist is removed using a special stripping solution. The pattern 31a is peeled off to form the wiring layer 22 and the land 23 on the insulating substrate 11 (see FIG. 2D and FIG. 3D).

Next, a predetermined area of the wiring layer 22 disposed between the lands 23 is set as a fine area (see FIG. 1A).
Next, a photosensitive layer is formed by a method such as laminating a dry film on the insulating base material 11 on which the wiring layer 22 and the land 23 are formed, and a series of patterning processes such as pattern exposure and development are performed. A resist pattern 32 is formed in a region excluding the refined region shown in (a) (see FIGS. 2 (e) and 3 (e)).

Next, using the resist pattern 32 as a mask, the wiring layer 22 in the refined region is etched by a predetermined amount using an etchant such as a ferric chloride solution (see FIGS. 2 (f) and 3 (f)). The resist pattern 32 is stripped with the stripping solution to obtain a printed wiring board in which the wiring layer 22a formed between the lands 23 is thinner and thinner than the wiring layer 22 (FIG. 2 (g) and FIG. g) and FIG. 1 (a)).
Here, when the wiring layer 22 in the fine region is etched, the pattern shape of the wiring layer 22 is also relaxed, the taper shape is eliminated, and the insulation between the wiring layers 22a is improved.
Further, the etching amount of the fine region is appropriately set depending on the thickness of the copper foil and the pattern pitch, but a range of 1 to 6 μm is preferable.

Hereinafter, a method for manufacturing the substrate for a semiconductor device illustrated in FIG.
6 (a) to (f), FIGS. 7 (g) to (k) and FIGS. 8 (a) to (f), schematic configurations of manufacturing processes of the printed wiring board (semiconductor device substrate) according to the present invention. A cross-sectional view is shown. 6 (a) to 6 (f) and FIGS. 7 (g) to (k) are schematic cross-sectional views of FIG. 4 (a) taken along the line CC ′, and FIGS. 8 (a) to 8 (f) are diagrams. The schematic structure sectional drawing which cut | disconnected 4 (a) by DD 'line is shown.

First, the adhesive layer 12 is formed by a method such as laminating an adhesive film on the insulating base material 11 made of a polyimide film or the like (see FIG. 6A).
Next, the insulating base material 11 on which the adhesive layer 12 is formed is punched with a mold to form sprocket holes 13 and device holes 15 (see FIG. 6B).

Next, a copper foil having a predetermined thickness is laminated on the adhesive layer 12 to produce a base material on which the copper foil 21 is laminated (see FIGS. 6C and 8A).
Next, a photosensitive layer 33 is formed by a method such as laminating a dry film after cleaning the surface of the copper foil 21 (see FIG. 6D), and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern. 33a is formed (see FIGS. 6E and 8B).

  Next, using the resist pattern 33a as a mask, the copper foil 21 is etched using an etchant such as a ferric chloride solution (see FIGS. 6 (f) and 8 (c)), and the resist pattern is removed with a special stripping solution. 33a is peeled off to form the inner leads 24, the wiring layer 25, and the solder ball connection terminals 26 on the insulating substrate 11 (see FIGS. 7G, 8D, and 5A).

  Next, a photosensitive layer is formed by a method such as laminating a dry film on the insulating base material 11 on which the inner lead 24, the wiring layer 25, and the solder ball connection terminal 26 are formed, and a series of pattern exposure, development, and the like are performed. A patterning process is performed to form a resist pattern 34 in a region excluding the refined region shown in FIG. 5A (see FIG. 7H).

  Here, for the sake of convenience of description, the fine region is set around the inner lead 24, but the wiring layer 25 between the solder ball connection terminals 26 can also be set as a fine region if the wiring layer pitch is complicated.

Next, using the resist pattern 34 as a mask, the inner lead 24 in the refined region is etched by a predetermined amount using an etching solution such as ferric chloride solution (see FIG. 7 (i)), and the resist is removed using a special stripping solution. The pattern 34 is peeled off to form the inner lead 24a formed thinner and thinner than the wiring layer 24 and the semiconductor element connection terminal 24b at the tip of the inner lead 24a (FIGS. 7J and 8E). )reference).
Here, when the inner lead 24 in the fine region is etched, the taper shape of the pattern of the inner lead is relaxed, the taper shape is eliminated, and the insulation between the inner leads is improved.
Further, the etching amount of the fine region is appropriately set depending on the thickness of the copper foil and the pattern pitch, but a range of 1 to 6 μm is preferable.

  Finally, a photosensitive solder resist is printed to form a solder resist layer, and a series of patterning processes such as pattern exposure and development are performed to form a solder resist pattern 41, using the solder resist pattern 41 as a mask. For the semiconductor device in which the solder ball connection terminal 26 and the semiconductor element connection terminal 24b are formed on the insulating base 11 by sequentially performing electrolytic nickel plating and gold plating on the solder ball connection terminal 26 and the semiconductor element connection terminal 24b. A substrate is obtained (see FIGS. 7 (k), 8 (f) and 4 (a)).

Hereinafter, the present invention will be described in detail by way of examples.
First, an adhesive (type X (trade name), manufactured by Yodogawa Paper Co., Ltd.) sheet is laminated on one side of an insulating substrate 11 made of a 50 μm polyimide film (Upilex S (trade name): manufactured by Ube Industries, Ltd.). An adhesive layer 12 having a thickness of 12 μm is formed, and a laminator is used to laminate a copper foil 21 having a thickness of 18 μm on the adhesive layer 12 at a setting temperature of 120 ° C., a laminating roller pressure of 0.2 MPa, and a laminating speed of 1.2 m / min. did. After that, it was heated stepwise in an oven, and finally held at 140 ° C. for 5 hours to completely cure the adhesive, and a base material on which the copper foil 21 was laminated was produced (FIG. 2A). And FIG. 3 (a)).

  Next, after cleaning the surface of the copper foil 21, a 10 μm thick dry film resist (SUNFORT (trade name) manufactured by Asahi Kasei Co., Ltd.) is laminated at a roll temperature of 105 ° C., a pressure of 0.3 MPa, and a laminating speed of 1.5 m / min. Then, a photosensitive layer was formed, and a series of patterning processes such as pattern exposure and development were performed using a projection exposure apparatus to form a resist pattern 31 (see FIGS. 2B and 3B).

  Next, a ferric chloride solution heated to 50 ° C. is sprayed by using the resist pattern 31 as a mask, and the exposed copper foil 21 is etched (see FIGS. 2C and 3C). The resist pattern 31 was peeled off by spraying a 3% sodium hydroxide solution at 0 ° C., and the wiring layer 22 and the land 23 were formed on the insulating substrate 11 (FIG. 2D, FIG. 3D and FIG. a)).

  Here, the pitch of the wiring layer 22 between the lands 23 was 30 μm.

  Next, a 40 μm thick dry film resist (SUNFORT (trade name) manufactured by Asahi Kasei Co., Ltd.) is laminated at a roll temperature of 105 ° C., a pressure of 0.4 MPa, and a laminating speed of 1.2 m / min to form a photosensitive layer, and projected. A predetermined pattern exposure is performed by a mold exposure apparatus, and a patterning process is performed by spray development of a 1% sodium carbonate solution at 30 ° C. for about 30 seconds, and a resist pattern is formed in an area excluding the refined area shown in FIG. 32 was formed (see FIG. 2 (e) and FIG. 3 (e)).

Next, using the resist pattern 32 as a mask, the inner lead 22 in the refined region is spray etched by about 2 μm with a ferric chloride solution (see FIG. 2 (f) and FIG. 3 (f)), and 50 ° C. 3% water. The resist pattern 32 was peeled off by spraying a sodium oxide solution by spraying to obtain a printed wiring board on which the wiring layer 22a between the lands 23 formed about 2 μm thinner and about 5 μm thinner than the wiring layer 22 was formed (FIG. 2 (g), FIG. 3 (g) and FIG. 1 (a)).
Here, when the wiring layer 22 in the refined region is etched, the pattern shape of the wiring layer 22 is also reduced in taper shape, the tapered shape is eliminated, and the insulation between the wiring layers 22a is also improved.

  First, an adhesive (type X (trade name), manufactured by Yodogawa Paper Co., Ltd.) sheet is laminated on one side of an insulating substrate 11 made of a 50 μm polyimide film (Upilex S (trade name): manufactured by Ube Industries, Ltd.). Thus, an adhesive layer 12 having a thickness of 12 μm was formed (see FIG. 6A).

  Next, the sprocket hole 13 and the device hole 15 were formed by punching a predetermined position of the insulating base material 11 with a mold (see FIGS. 6B and 5A).

  Next, a copper foil 21 having a thickness of 18 μm was laminated on the adhesive layer 12 using a laminator at a set temperature of 120 ° C., a laminating roller pressure of 0.2 MPa, and a laminating speed of 1.2 m / min. Then, it heated in steps in an oven, and finally it was held at 140 ° C. for 5 hours to completely cure the adhesive, and a base material on which the copper foil 21 was laminated was produced (FIG. 6C). And FIG. 8 (a)).

  Next, after cleaning the surface of the copper foil 21, a 10 μm thick dry film resist (SUNFORT (trade name) manufactured by Asahi Kasei Co., Ltd.) is laminated at a roll temperature of 105 ° C., a pressure of 0.3 MPa, and a laminating speed of 1.5 m / min. Then, the photosensitive layer 33 was formed (see FIG. 6D).

  Next, a series of patterning processes such as pattern exposure and development were performed using a projection type exposure apparatus to form a resist pattern 33a (see FIGS. 6E and 8B).

  Next, a ferric chloride solution heated to 50 ° C. is sprayed by using the resist pattern 33a as a mask, and the exposed copper foil 21 is etched (see FIGS. 6 (f) and 8 (c)). The resist pattern 33a was peeled off by spraying a 3% sodium hydroxide solution at 0 ° C., and the inner leads 24, the wiring layer 25, and the solder ball connection terminals 26 were formed on the insulating substrate 11 (FIG. 7 (g), FIG. 8 (d) and FIG. 5 (a)).

  Here, the pitch of the inner leads 24 was 35 μm.

Next, a 40 μm thick dry film resist (SUNFORT (trade name) manufactured by Asahi Kasei Co., Ltd.) is laminated at a roll temperature of 105 ° C., a pressure of 0.4 MPa, and a laminating speed of 1.2 m / min to form a photosensitive layer, and projected. A predetermined pattern exposure is performed with a mold exposure apparatus, and 30 ° C., 1
% Of sodium carbonate solution was spray-developed for about 30 seconds to perform patterning, and a resist pattern 34 was formed in a region excluding the refined region shown in FIG. 5A (see FIG. 7H).

  Next, using the resist pattern 34 as a mask, the inner lead 24 in the refined region is spray-etched with a ferric chloride solution for a total of about 5 μm (see FIG. 7 (i)), and a 50 ° C. 3% sodium hydroxide solution The resist pattern 34 is peeled off by spraying to form an inner lead 24a that is about 6 μm thinner than the wiring layer 25 and about 3 μm thinner, and a semiconductor element connection terminal 24b is formed at the tip of the inner lead 24a (see FIG. FIG. 7 (j) and FIG. 8 (e)).

  Finally, a photosensitive solder resist is printed to form a solder resist layer, and a series of patterning processes such as pattern exposure and development are performed to form a solder resist pattern 41, using the solder resist pattern 41 as a mask. A semiconductor device in which the solder ball connection terminal 26 and the semiconductor element connection terminal 24b are formed on the insulating substrate 11 by performing electrolytic nickel plating and gold plating on the solder ball connection terminal 26 and the semiconductor element connection terminal 24b in this order. A substrate was obtained (see FIG. 7 (k), FIG. 8 (f) and FIG. 4 (a)).

(A) is a schematic plan view which shows one Example of the printed wiring board which concerns on this invention.

  (B) is a schematic cross-sectional view taken along line A-A ′ of (a).

(C) is a schematic cross-sectional view of (a) cut along the line BB ′.
(A)-(g) is the schematic structure sectional drawing cut | disconnected by the AA 'line which shows an example of the manufacturing process of the printed wiring board concerning this invention. (A)-(g) is the schematic structure sectional drawing cut | disconnected by the BB 'line which shows an example of the manufacturing process of the printed wiring board which concerns on this invention. (A) is a schematic top view of the board | substrate for semiconductor devices which shows the other Example of the printed wiring board concerning this invention.

  (B) is a schematic cross-sectional view taken along line C-C ′ of (a).

(C) is a schematic cross-sectional view of (a) cut along line DD ′.
(A) is a schematic plan view which shows the intermediate | middle process of the board | substrate for semiconductor devices which shows the other Example of the printed wiring board concerning this invention.

  (B) is a schematic cross-sectional view taken along line C-C ′ of (a).

(C) is a schematic cross-sectional view of (a) cut along line DD ′.
(A)-(f) is typical structure sectional drawing cut | disconnected by CC 'line which shows a part of process in the manufacturing method of the board | substrate for semiconductor devices which shows the other Example of the printed wiring board concerning this invention. is there. (G)-(k) is typical structure sectional drawing cut | disconnected by CC 'line | wire which shows a part of process in the manufacturing method of the board | substrate for semiconductor devices which shows the other Example of the printed wiring board concerning this invention. is there. (A)-(f) is typical structure sectional drawing cut | disconnected by the DD 'line | wire which shows the manufacturing process of the board | substrate for semiconductor devices which shows the other Example of the printed wiring board concerning this invention.

Explanation of symbols

11 ... Insulating substrate 12 ... Adhesive layer 13 ... Sprocket hole 15 ... Device hole 21 ... Copper foil 22, 25 ... Wiring layer 22a ... Thinned wiring layer 23 ... Lands 31, 32 , 33a, 34... Resist pattern 24... Inner lead 24a... Thinned inner lead 24b... Semiconductor element connection terminal 26... Solder ball connection pad 33... Photosensitive layer 41.

Claims (2)

  A printed wiring board in which solder ball connection terminals, lands, wiring layers, inner leads, semiconductor element connection terminals, and the like are formed on an insulating substrate, wherein the wiring between the solder ball connection terminals and between the lands A region in which the layer, the inner lead, and the connection terminal for the semiconductor element are configured with a finer pattern than the other wiring layer is set as a fined region, and the wiring layer, the inner lead, and the connection terminal for the semiconductor element in the fined region are set. A printed wiring board characterized in that the film thickness and the line width are thinner and thinner than the film thickness of the wiring layer other than the refined region.   A step of forming a connection terminal for a semiconductor element at least on an insulating base material, a land, a solder ball connection terminal, a wiring layer, an inner lead and a tip of the inner lead, and a wiring layer between the lands and the connection for the solder ball A step of setting a predetermined region of a wiring layer between terminals, inner leads, and connection terminals for semiconductor elements as a finer region, a step of forming a resist pattern in a region excluding the finer region, and using the resist pattern as a mask The method of manufacturing a printed wiring board according to claim 1, further comprising a step of etching a predetermined amount of the wiring layer, the inner lead, and the semiconductor element connection terminal in the refined region.

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