JP4419656B2 - Semiconductor device substrate and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for semiconductor device, the manufacturing method thereof and a semiconductor device in which the connecting strength and the connecting reliability of solder ball are improved by connecting a connecting terminal to the solder ball through an opening on a land. <P>SOLUTION: A pad 21b, the land 21a having an opening 22, and a solder resist layer 41 are formed on one surface of an insulating substrate 11 while an opening 13 for forming a solder ball is formed on the other surface of the same. An IC chip 71 is mounted on a substrate for semiconductor device, in the land 21a in the opening 42 of the solder resist layer 41 of which the connecting terminal 51 consisting of the solder is formed and the electrode of the IC chip 71 is connected to the pad 21b of the semiconductor device through wire bond connection. The IC chip 71 is sealed by a transfer mold through resin sealing, and ball-type solder is disposed to form the solder ball 61 through reflowing and obtain the semiconductor device. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device for various electronic devices and a substrate for a semiconductor device used therefor, and more particularly, a substrate for a semiconductor device that requires a solder ball (external connection terminal) with a narrow connection pitch such as a chip size, a package, etc. The present invention relates to a semiconductor device.

With the recent high integration of ICs, the number of electrode pads per chip has increased, and in the semiconductor device substrate, the pad area has been reduced and the pad pitch has been reduced.
Currently, semiconductor devices of a type in which a conductor is exposed from an opening of an insulating layer and solder balls are joined thereto are widely used. In particular, in CSP (chip size package) type semiconductor devices, connection terminals are becoming increasingly narrow due to demands for smaller size and higher performance, and products with a ball pitch of 0.5 mm or less are also mass-produced. ing. However, as the ball pitch narrows, the situation where the solder ball connection strength cannot be maintained has been highlighted. In other words, a reduction in the bonding area between the land and the solder ball has become a big problem due to the reduction in the connection area due to the narrow pitch.
In order to improve the bonding strength of the above solder balls, the surface treatment method on the land side, such as changing the surface roughness of the land, forming a recess in the land, or changing the thickness and type of plating applied to the land, will be studied. Several attempts have been proposed (see, for example, Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4).

In Patent Document 1, a connection area is increased by providing a recess in a land of a wiring board, and a bonding strength by solder is improved.
Patent Document 2 improves the bonding strength between the printed wiring board and the pad by providing a lead-out pattern from the pad to increase the bonding area between the printed wiring board and the pad.
Patent Document 3 discloses that in a multilayer circuit board in which interlayer connection is made with a conductive paste, the contact area between the conductive paste and the land with openings in each layer is increased by forming through holes in a tapered shape and forming ridges on the lands. Thus, the interlayer contact resistance between the multilayer circuits is reduced to improve the transmission characteristics of the entire circuit.
Patent Document 4 discloses that in a multilayer circuit board in which interlayer connection is performed with a conductive paste, bubbles at the time of filling the conductive paste are eliminated by making the cross-sectional shape of the opening of the insulating layer a curved surface. Improves continuity.
JP 2000-269271 A JP 2000-31630 A JP 2003-179321 A JP 2003-258431 A

In the above case, the effect is limited and has not led to an essential solution. For example, in Patent Document 1, an attempt is made to improve the bonding strength of a solder ball by forming a recess in a land and using a connection surface in an improved direction and a vertical connection surface. However, the point common to these prior arts including Patent Document 1 and Patent Document 2 is that the land and solder are relied on only at the interface, and there are problems such as abnormal surface conditions and contamination. In such a case, the bonding strength is remarkably lowered, and there is a risk of disconnection due to interface peeling.

  In addition, when the recess is formed in the land, depending on the process and its structure, generally, the bottom of the recess often comes into contact with a mold resin, a solder resist, or the like. It is known that the contact area between these resin and solder is extremely weak compared to the contact area with metal. In that case, even if the connection area is increased on the side of the land, In the end, the adhesive force is not so much improved because the typical connection area is reduced.

  The present invention has been devised in view of the above problems, and by connecting a connection terminal and a solder ball through an opening of a land, a semiconductor device substrate having improved solder ball connection strength and connection reliability, and An object of the present invention is to provide a manufacturing method and a semiconductor device.

In order to achieve the above object, according to the present invention, first, in claim 1 , the pad 21b, the land 21d 'having the recess 23 and the solder resist layer 41 are provided on one surface of the insulating substrate 11, and the solder resist layer 41 is provided on the other surface. an opening 1 4 for ball formation is formed, the solder resist for a semiconductor device, characterized in that the connection terminals 52 made of solder on the lands 21d 'in the opening 43 of the layer 41 is formed a substrate It is what.

According to a second aspect of the present invention, there is provided the method for manufacturing a semiconductor device substrate according to the first aspect, comprising at least the following steps.
(A) The process of forming the opening part 14 in the predetermined position of the insulating base material 11 in which the adhesive bond layer 15 was formed. (B) A step of laminating the copper foil 21.
(C) A step of patterning the copper foil 21 to form the land 21d.
(D) A step of forming a resist pattern 33 having a predetermined shape on the land 21d.
(E) A step of etching the land 21d to a predetermined depth using the resist pattern 33 as a mask, peeling the resist pattern 33, and forming a recess 23 having a predetermined shape on the land 21d.
(F) The process of forming the soldering resist layer 41 which has the opening part 43 in the predetermined position of the land 21d.
(G) A step of filling the opening 43 of the solder resist layer 41 with a solder paste to form the connection terminal 52.

Substrate for a semiconductor device of the present invention, by forming the connection terminals by reflowing the solder on the land having a concave portion, increases the contact area of the land and the solder connection during the formation of the solder balls for external connection A solder ball having an integrated structure with the terminal can be formed, and a semiconductor device having excellent solder ball connection strength and connection reliability can be obtained.
Further, the connection terminals formed on the substrate for a semiconductor device of the present invention are the same as when the openings are provided in the connection terminals even in a rigid substrate process in which a pattern cannot be formed in the vicinity of the opening of the insulating layer typified by a flying lead. A semiconductor device substrate can be obtained.
In addition, by forming the connection terminal with solder containing Sn as a main component, a reflow process that is currently generally used can be used as it is.

Embodiments of a semiconductor device substrate, a method of manufacturing the same, and a semiconductor device according to the present invention will be described.
FIG. 1A is a schematic plan view showing an embodiment of the substrate for a semiconductor device of the present invention, and FIG. 1B is a schematic plan view of FIG. the schematic configuration sectional view of a semi-conductor device substrate cut, in Fig. 1 (c), the semiconductor device substrate according to claim 1, a schematic plan view taken along the line a-a 'in FIGS. 1 (a) 2A is a partially schematic cross-sectional view in which part A of FIG. 1B is enlarged, and FIG. 2B is a part B of FIG. 1C. The expanded partial schematic structure sectional drawing is shown, respectively.

As shown in FIGS. 1C and 2B, the substrate for a semiconductor device according to claim 1 includes a pad 21b, a land 21d ′ having a recess 23 on one surface of the insulating base material 11, and a solder resist layer. 41, a solder ball forming opening 14 is formed on the other surface, and a connection terminal 52 made of solder is formed on a land 21d 'in the opening 43 of the solder resist layer 41.
The connection terminal 52 formed in the opening 43 of the solder resist layer 41 is integrated at the time of solder ball bonding described later, thereby improving the connection strength and connection reliability of the solder ball.

Hereinafter, you describes making how a semiconductor device substrate of the present invention.

6 (a) to 6 (f) and FIGS. 7 (g) to 7 (k) are partial schematic cross-sectional views showing the method of manufacturing a semiconductor device substrate according to claim 1 in the order of steps.

  First, an adhesive layer 15 is formed by a method such as laminating an adhesive film on one surface of an insulating base material 11 made of a polyimide film or the like (see FIG. 6A), and punching is performed with a mold, thereby insulating base material. The opening part 14 is formed in the predetermined position of the sprocket hole 12 and the insulation base material 11 at the both ends of 11 (refer FIG.6 (b)).

Next, the copper foil 21 is bonded to the adhesive layer 15 on the insulating base material 11 with a laminator and heated at a predetermined temperature to cure the adhesive layer 15 to produce a composite material (FIG. 6C). reference).
Further, a photosensitive layer 31 is formed by a method such as laminating a dry film after cleaning the surface of the copper foil 21 (see FIG. 6D), and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 31a. (See FIG. 6E).
Here, the backing material 32 is formed so that the copper foil 21 in the opening 14 is not etched.

  Next, using the resist pattern 31a as a mask, the copper foil 21 is etched using an etchant such as a ferric chloride solution, and the resist pattern 31a is stripped with a special stripping solution. And the pad 21b is formed (refer FIG.6 (f)).

  Next, a photosensitive layer is formed by a method such as laminating a dry film, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 33 (see FIG. 7G). Here, the backing material 32 is formed so that the copper foil 21 in the opening 14 is not etched.

Next, using the resist pattern 33 as a mask, the copper foil 21 is etched to a predetermined depth, and the resist pattern 33 and the backing material 32 are peeled off with a special stripping solution. 21d ', pad 21b, and ground base metal 21c are formed (see FIG. 7 (h) and FIG. 1 (a)).
Here, the thickness of the bottom of the recess 23 of the land 21d ′ is preferably thin (about 1 to 3 μm) so as to have an integrated structure when the connection terminal 52 is formed with solder described later. Moreover, the shape of the recessed part 23 can use the thing of all shapes, such as circular shape, ellipse shape, cross shape, and polygonal shape as shown to Fig.10 (a)-(d).

  Next, the solder resist layer 41 is formed by a method such as laminating a dry film type solder resist having photosensitivity (see FIG. 7I). Further, a series of patterning processes such as pattern exposure and development are performed to expose the pad 21b and form the solder resist layer 41 having the opening 43 on the land 21d ′ having the recess 23 (see FIG. 7J). ).

Next, the lands 21 d ′ having the recesses 23 and the pads 21 b are plated with gold, screen-printed with cream solder, filled with the cream solder in the openings 43 of the solder resist layer 41, and reflowed in a reflow furnace for connection. Terminals 52 are formed to obtain a semiconductor device substrate (see FIGS. 7K and 1C).
Here, when the cream solder is melted and reflowed, the copper at the bottom of the recess 23 of the land 21d ′ is thin (1 to 3 μm thick), so it melts into the solder to form an integrated structure, and an opening is provided. Since a connection terminal having substantially the same shape as the structure can be obtained, even in a rigid substrate process in which a pattern cannot be formed in the vicinity of the opening of an insulating layer typified by a flying lead, the same semiconductor as the case where an opening is provided in the connection terminal An apparatus substrate can be obtained. Further, the melting point of the connection terminal 52 made of cream solder is set to be the same as or slightly lower than the melting point of a solder ball to be formed later.

Next, the IC chip 71 is bonded to the ground base metal 21c with a conductive adhesive, the electrodes of the IC chip 71 and the pads 21b of the semiconductor device substrate are wire-bonded with the bonding wires 72, and the IC chip 71 is transferred by transfer molding. Is sealed with resin. Further, ball-shaped solder is placed and reflowed to form solder balls 61, whereby the semiconductor device 300 is obtained (see FIG. 3).
Here, when the solder balls 61 are formed by reflowing, the connection terminals 52 made of solder formed in advance are also remelted and integrated with the solder balls 61.

This example is an example for reference.
First, both ends of a composite material (Espanex KC (trade name) manufactured by Nippon Steel Chemical Co., Ltd.) in which an 18 μm-thick copper foil 21 is laminated on one side of an insulating base material 11 made of a polyimide film having a thickness of 50 μm are molded. A sprocket hole 12 was formed by punching (see FIGS. 1A and 4A).

Next, a hole was formed in a predetermined position of the insulating substrate 11 using a carbon dioxide laser processing apparatus to form an opening 13 having a diameter of 275 μmφ (see FIGS. 4B and 8). Further, after cleaning the surface of the opening 13 and the copper foil 21, a positive liquid resist (PMER-P (trade name): manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied and dried to form a photosensitive layer 31 having a thickness of 3 to 5 μm. Then (see FIG. 4C), pattern exposure was performed with a projection exposure apparatus, and development processing was performed to form a resist pattern 31a (see FIG. 4D). Further, a backing material 32 was formed so that the copper foil 21 in the opening 13 was not etched.

  Next, using the resist pattern 31a as a mask, the copper foil 21 is etched by spraying a ferric chloride solution in which the copper foil 21 is heated to 50 ° C., and spraying a 3% sodium hydroxide solution at 50 ° C. by spraying. The stopper was peeled off at the same time to form a 380 μmφ land 21a, a pad 21b, and a ground base metal 21c having an oval opening 22 having a width of 125 μm and a length of 250 μm on the insulating substrate 11 (FIG. 4E). 8 and FIG. 1 (a)).

Next, a dry film type solder resist having photosensitivity was laminated to form a solder resist layer 41 (see FIG. 4F). Further, a series of patterning processes such as pattern exposure and development were performed to expose the pad 21b and form the solder resist layer 41 having the opening 42 on the land 21a having the opening 22 (see FIG. 5G). ).
Here, the opening 42 of the solder resist layer 41 was set to be about 50 μm outside from the edge of the oval opening 22.

  Next, the lands 21a and the pads 21b are plated with gold, screen-printed with a tin alloy paste containing about 3% silver, filled in the openings of the solder resist layer 41 with the tin alloy paste, and reflowed in a reflow furnace. The connection terminals 51 made of solder were formed to obtain a semiconductor device substrate 100 (see FIG. 5H and FIG. 1B).

Next, the IC chip 71 is bonded to the ground base metal 21c with a conductive adhesive, the electrodes of the IC chip 71 and the pads 21b of the semiconductor device substrate are wire-bonded with the bonding wires 72, and the IC chip 71 is transferred by transfer molding. Is sealed with resin. Furthermore, ball-shaped solder was placed and reflowed to form solder balls 61, whereby a semiconductor device 300 was obtained (see FIG. 3).
Here, when the solder balls 61 were formed by reflowing, the connection terminals 51 made of a tin alloy formed in advance were also remelted and integrated with the solder balls 61.

Hereinafter, the present invention will be described in detail by way of examples.
First, a 12 μm-thick adhesive film (type X (trade name): manufactured by Yodogawa Paper Co., Ltd.) on one side of an insulating base material 11 made of a polyimide film (UPILEX S (trade name): manufactured by Ube Industries Co., Ltd.) having a thickness of 50 μm. Are laminated to form an adhesive layer 15 (see FIG. 6A), punched out with a mold, sprocket holes 12 at both ends of the insulating base material 11, and openings 14 at predetermined positions of the insulating base material 11. Was formed (see FIG. 6B).

Next, a 18 μm thick copper foil 21 was bonded to the adhesive layer on the insulating substrate 11 with a laminator set at a roll temperature of 120 ° C., a laminating roller pressure of 0.2 MPa, and a laminating speed of 1.0 m / min. Heating was performed stepwise in an oven, and finally the adhesive layer was cured by holding at 140 ° C. for 6 hours (see FIG. 6C).
Further, after cleaning the surface of the copper foil 21, a positive liquid resist (PMER-P (trade name): manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied and dried to form a photosensitive layer 31 having a thickness of 3 to 5 μm (FIG. 6). (See (d)), pattern exposure was performed with a projection exposure apparatus, and development processing was performed to form a resist pattern 31a (see FIG. 6E). Further, a backing material 32 was formed so that the copper foil 21 in the opening 14 was not etched.

Next, using the resist pattern 31a as a mask, the copper foil 21 is etched by spraying a ferric chloride solution in which the copper foil 21 is heated to 50 ° C., and spraying a 3% sodium hydroxide solution at 50 ° C. by spraying. The stopper was peeled off at the same time to form lands 21d, pads 21b, and ground base metal 21c on the insulating substrate 11 (see FIG. 6 (f) and FIG. 1 (a)).

  Next, a 25 μm thick dry film resist (SUNFORT (trade name) manufactured by Asahi Kasei Co., Ltd.) is laminated at a roll temperature of 105 ° C., a pressure of 0.4 MPa, and a laminating speed of 1.2 m / min to form a photosensitive layer. Further, the resist pattern 33 was formed at a predetermined position on the land 21d by performing exposure with a projection type exposure apparatus and spray developing a 1% sodium carbonate solution at 30 ° C. for about 30 seconds (see FIG. 7G). . Further, a backing material 33 was formed so that the copper foil 21 in the opening 14 was not etched.

  Next, using the resist pattern 33 as a mask, the copper foil 21 is etched to a depth of 15 to 16 μm (bottom thickness: 2 to 3 μm) by spraying a 50 ° C. ferric chloride solution with a spray, and a dedicated peeling is performed. The resist pattern 33 was stripped with a liquid, and a cross-shaped concave portion 23 and a pad 21b having a depth of 15 to 16 μm were formed on the insulating substrate 11 at predetermined positions of the land 21d (see FIGS. 7H and 9). .

Next, a dry film type solder resist having photosensitivity was laminated to form a solder resist layer 41 (see FIG. 7 (i)). Further, a series of patterning processes such as pattern exposure and development were performed to expose the pad 21b and form the solder resist layer 41 having the opening 43 on the land 21d ′ having the recess 23 (see FIG. 7J). ).
Here, the opening 43 of the solder resist layer 41 was made smaller than the opening 14 of the insulating base material 11 and larger than the cross-shaped recess 23 (see FIG. 9).

  Next, the lands 21d 'having the recesses 23 and the pads 21b are plated with gold, screen-printed with cream solder, filled with the cream solder in the openings 43 of the solder resist layer 41, and reflowed in a reflow furnace to be connected. Terminals 52 were formed to obtain a semiconductor device substrate 200 (see FIGS. 7 (k) and 1 (c)).

Next, the IC chip 71 is bonded to the ground base metal 21c with a conductive adhesive, the electrodes of the IC chip 71 and the pads 21b of the semiconductor device substrate are wire-bonded with the bonding wires 72, and the IC chip 71 is transferred by transfer molding. Was sealed with resin. Furthermore, ball-shaped solder was placed and reflowed to form solder balls 61, whereby a semiconductor device 300 was obtained (see FIG. 3).
Here, when the solder balls 61 were formed by reflowing, the connection terminals 52 made of solder formed in advance were also remelted and integrated with the solder balls 61.

(A) is a schematic plan view which shows one Example of the board | substrate for semiconductor devices which concerns on this invention. (B) is a schematic cross-sectional view of a semiconductor device substrate according to Example 1 in which (a) is cut along line AA ′. (C) is a schematic cross-sectional view of a semiconductor device substrate according to claim 1 , wherein (a) is cut along the line AA ′. (A) is the partial schematic structure sectional drawing which expanded the A section of the schematic structure sectional drawing of the board | substrate for semiconductor devices which concerns on Example 1 of FIG.1 (b). FIG. 2B is a partial schematic cross-sectional view of an enlarged B portion of the schematic cross-sectional view of the semiconductor device substrate according to claim 1 of FIG. 1 is a schematic cross-sectional view showing an embodiment of a semiconductor device of the present invention. (A)-(f) is typical structure sectional drawing which shows a part of process in the manufacturing method of the board | substrate for semiconductor devices which concerns on Example 1 of this invention. (G)-(h) is typical structure sectional drawing which shows a part of process in the manufacturing method of the board | substrate for semiconductor devices which concerns on Example 1 of this invention. (A) ~ (f) are schematic configuration sectional view showing a part of steps in the method for manufacturing a semiconductor device substrate according to claim 1 of the present invention. (G) ~ (k) is a schematic configuration sectional view showing a part of a step in the method for manufacturing a substrate for a semiconductor device according to claim 1 of the present invention. (A) And (b) is explanatory drawing which shows the Example of the land which has the opening part used in Example 1. FIG. (A) And (b) is explanatory drawing which shows the Example of the land which has the recessed part used in Example 2. FIG. (A) ~ (d) are explanatory views showing a specific example of the shape of the concave portion you formed on the land.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Insulating base material 12 ... Sprocket hole 13, 14 ... Opening part 15 ... Adhesive layer 21 ... Copper foil 21a ... Land 21b which has an opening part ... Pad 21c ... Ground base metal 21d ... Land 21d '... Land 22 with recesses ... Opening 23 ... Concave 31 ... Photosensitive layer 31a, 33 ... Resist pattern 32 ... Backing material 41 ... Solder resist layer 42, 43 ... Opening 51 52 ... Connection terminal 61 ... Solder ball 71 ... IC chip 72 ... Bonding wire 81 ... Seal resin 100, 200 ... Semiconductor device substrate 300 ... Semiconductor device

Claims (2)

Pads on one surface of the insulating base material (11) (21b), recesses lands with (23) (21d ') and the solder resist layer (41) is an opening for the solder balls formed on the other surface (1 4 And a connection terminal (52) made of solder is formed on the land (21d ') in the opening (43) of the solder resist layer (41). substrate. The method for manufacturing a substrate for a semiconductor device according to claim 1 , comprising at least the following steps.
(A) The process of forming an opening part (14) in the predetermined position of the insulating base material (11) in which the adhesive bond layer (15) was formed.
(B) A step of laminating the copper foil (21).
(C) A step of patterning the copper foil (21) to form lands (21d) and pads (21b).
(D) A step of forming a resist pattern (33) having a predetermined shape on the land (21d).
(E) A step of etching the land (21d) to a predetermined depth using the resist pattern (33) as a mask, peeling the resist pattern (33), and forming a concave portion (23) having a predetermined shape on the land (21d). .
(F) A step of forming a solder resist layer (41) having an opening (43) at a predetermined position of the land (21d).
(G) A step of filling the solder paste in the opening (43) of the solder resist layer (41) to form the connection terminal (52).

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