JP4984502B2 - BGA type carrier substrate manufacturing method and BGA type carrier substrate - Google Patents

Description

  The present invention relates to a method for manufacturing a BGA type carrier substrate on which a semiconductor chip is mounted and a BGA type carrier substrate.

  With recent demands for smaller, thinner and higher density semiconductor devices, the package forms used in these semiconductor devices are QFP (quad flat package) type and TCP (tape carrier tape). CSP (Chip Size Package) using BGA (Ball Grid Array) in which bump electrodes are arranged in an area array from the package) is widely deployed in the market.

  In recent years, semiconductor devices such as semiconductor large-scale integrated circuits (LSIs) have appeared that have an operating speed of 1 GHz in terms of clock frequency. In such a high-speed semiconductor device, there are some devices in which the degree of integration of transistors is high, and as a result, the number of input / output terminals exceeds 1000.

  In order to mount such a multi-terminal number of semiconductor elements on a printed wiring board, a carrier board is disposed between the semiconductor elements and the printed board, and serves as a bridge for electrical connection between the two. The carrier substrate has a much thinner layer structure than the printed wiring board to support bonding with the high-density semiconductor element terminals, and bumps for mounting the semiconductor chip on one surface are on the other surface. A BGA type carrier substrate having a solder ball electrode pad formed thereon is used.

  Recently, in order to respond to the demand for higher density mounting and higher operating frequency, the thickness of the entire multilayer circuit wiring board is reduced by laminating a polyimide resin film with a wiring layer formed. At the same time, ones that are compatible with high frequencies by shortening the interlayer connection length have been developed.

5A and 5B are a schematic plan view and a schematic cross-sectional view showing an example of a conventional tape carrier for a semiconductor device.
The tape carrier 200 is provided with an inner lead 121c, a wiring layer 121b, a land 121a, a device hole 113, and a solder ball electrode 131 at predetermined positions of an insulating film 111 made of a polyimide film or the like.

  The solder ball electrode 131 is provided in the opening 112 formed in the insulating film 111 on the back surface of the land 121a, and the solder ball electrode 131 is plated with Au (gold), Sn (tin), solder, or the like. Is given.

  Furthermore, solder balls 141 are formed on the solder ball electrodes 131 by mounting solder balls on the solder ball electrodes 131, or by printing and reflowing solder paste (see FIG. 6). A semiconductor device is obtained.

When the solder ball 141 is formed on the solder ball electrode 131, the diameter of the opening 112 is smaller than the thickness of the insulating film 111 due to the recent flow of fine pitch and high density mounting. (Or solder paste) is less likely to contact the solder ball electrode 131 in the opening 112.
As a result, solder wetting failure may occur or a void may be generated in the opening 112, and solder may not be joined to the solder ball electrode 131.

  As a method of solving the problem of poor bonding of solder to the solder ball electrode 131, a tape carrier for a semiconductor device is proposed in which a raised conductor layer is formed by electrolytic copper plating in the opening 112 on the solder ball electrode 131 ( For example, see Patent Document 1).

However, as the diameter of the opening formed on the solder ball electrode 131 becomes smaller, the surface shape of the raised conductor layer becomes a problem.
FIG. 7A is a partial schematic cross-sectional view of a tape carrier in which a solder ball electrode 131 is formed in an opening 112 formed in the insulating film 111 on the back surface of the land 121a.

  An example of the surface shape of the raised conductor layer 151 in which the raised conductor layer 151 is formed by electrolytic copper plug plating on the solder ball electrode 131 in the opening 112 shown in FIG. 7A is shown in FIG. 7B.

The surface of the raised conductor layer 151 shown in FIG. 7B has a convex shape. When the thickness of the raised conductor layer 151 reaches about 80% of the insulating film 111, solder balls are mounted. In this case, it becomes unstable on the raised conductor layer 151, and when reflowing, the solder balls fall or the position of the solder balls is misaligned.
Therefore, the surface shape of the raised conductor layer 151 is preferably flat or concave.

The convex shape on the surface of the raised conductor layer 151 shown in FIG. 7B is an example when copper plug plating is performed by direct current electrolytic copper plating, and it is difficult to control the copper plating deposition shape by plating conditions and the like. Has the problem.
Japanese Patent No. 3238074

  The present invention has been devised in view of the above problems. When a raised conductor layer is formed by direct current electrolytic copper plating on a solder ball electrode in an opening, copper is previously used as a copper plating solution used for electrolytic copper plating. It is an object of the present invention to provide a method for producing a BGA type carrier substrate and a BGA type carrier substrate in which the surface shape of the raised conductor layer is controlled by adding a plating additive (accelerator).

In order to achieve the above object in the present invention, first, in claim 1, a pad for mounting a semiconductor chip is formed on one surface, and a solder ball electrode and a raised conductor layer are formed on the other surface. In the manufacturing method of the BGA type carrier substrate,
When the raised conductor layer of the solder ball connection pad is formed by DC electrolytic copper plating, the copper plating solution used for electrolytic copper plating is disulfide (disulfide) copper plating additive (accelerator) as 3-sulfo Producing a BGA type carrier substrate characterized in that the surface of the raised conductor layer in contact with the solder ball connection pad is made concave by adding propyl-disulfide in a compounding concentration of 0.04 to 0.15 ml / L. It is a method.

  A second aspect of the present invention is a BGA type carrier substrate manufactured by the method for manufacturing a BGA type carrier substrate according to the first aspect.

According to the method for manufacturing a BGA type carrier substrate of the present invention, since the surface shape of the raised conductor layer of the solder ball electrode can be formed in a concave shape, the solder ball mountability is stabilized, and a solder ball having excellent bonding strength can be formed.
In addition, since the BGA type carrier substrate can form solder balls with excellent bonding strength, a semiconductor device obtained by mounting a semiconductor chip or the like becomes a semiconductor device with excellent reliability.

Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a schematic cross-sectional view showing an example of a BGA type carrier substrate produced by the method for producing a BGA type carrier substrate of the present invention.
FIG. 2 is a partial enlarged schematic cross-sectional view in which the peripheral portion of the raised conductor layer 31 for forming solder balls is enlarged.

The BGA type carrier substrate 100 of the present invention is formed with an electrode pad 21b for connecting a land 21a and a semiconductor chip to one surface of an insulating base material 11, and a solder ball electrically connected to the land 21a on the other surface. A raised conductor layer 31 and a Ni / Au plating layer 51 are formed.
As shown in FIG. 2, the surface shape of the raised conductor layer 31 is concave, so that stable ball mountability can be secured and excellent solder ball bonding strength can be obtained.

Hereinafter, the manufacturing method of the BGA type | mold carrier substrate of this invention is demonstrated.
3A to 3H are schematic cross-sectional views showing an example of a method for manufacturing a BGA type carrier substrate of the present invention.
First, the insulating base material 11 which consists of a polyimide film film etc. in which the adhesive material layer 12 was formed is prepared (refer Fig.3 (a)).

Next, a hole is formed by punching, laser processing or the like to form an opening 13 at a predetermined position of the insulating base material 11, and a desmear process in the opening 13 is performed (see FIG. 3B).
The opening 13 is used to form a raised conductor layer for forming solder balls, and a drilling method is selected according to the hole diameter, processing accuracy, and the like of the opening 13.

  Next, the adhesive layer 12 surface of the insulating base material 11 in which the opening 13 is formed and the copper foil are pressed and heated to bond together, and the conductor layer 21 is formed on the insulating base material 11 in which the opening 13 is formed. The laminated base material 20 thus prepared is prepared (see FIG. 3C).

  Next, in order to electrically protect the surface of the conductor layer 21 of the laminated substrate 20, a protective layer (particularly not shown) is formed by a method such as attaching a mending tape, etc. Using the copper plating solution shown below to which a sulfide) -based copper plating additive (accelerator) is added, DC electrolytic copper plug plating is performed using the conductor layer 21 as a cathode, and the surface shape is formed in the opening 13. A raised conductor layer 31 having a concave shape is formed (see FIG. 3D).

Example of composition of copper plating solution Copper sulfate concentration: 130 g / L
Sulfuric acid concentration: 190 g / L
Hydrochloric acid concentration: 100 mg / L
Inhibitor for copper plating solution (polyethylene glycol): 15 mg / L
Easily soluble copper oxide: appropriate amount disulfide (disulfide) based copper plating additive (accelerator): 004-068 ml / L
The amount of the disulfide (disulfide) -based copper plating additive (accelerator) is, for example, a case where 3-sulfopropyl-disulfide (Rohm and Haas Co., USA) is used.

The relationship between the blending concentration of 3-sulfopropyl-disulfide (Rohm and Haas: USA) and the surface shape of the raised conductor layer 31 of the opening 13 is 0.04 to 0.15 ml / L. The surface of the raised conductor layer 31 of the portion 13 has a concave shape.
The surface of the raised conductor layer 31 of the opening 13 is changed from a concave shape to a flat shape as it increases from 0.15 ml / L to 068 ml / L, and when it is 068 ml / L or more, the surface of the raised conductor layer 31 of the opening portion 13 is convex. Show shape.
In this way, by adding an appropriate amount of a disulfide (disulfide) -based copper plating additive (accelerator) to a normal copper plating solution, the raised conductor layer 31 having a concave surface shape can be formed by DC electrolytic copper plating. It becomes possible to form.

  Next, the protective layer on the conductor layer 21 is stripped to form a resist on the conductor layer 21, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 41. A protective layer 42 is formed on the 31st surface with a mending tape or the like (see FIG. 3E).

  Next, using the resist pattern 41 as an etching mask, the conductor layer 21 is etched, the resist pattern 41 and the protective layer 42 are peeled off, and the land 21, the wiring layer (not shown) and the semiconductor chip are connected. An electrode pad 21b is formed (see FIG. 3F).

  Next, a resist layer 43 for preventing Au / Ni plating is formed at a predetermined position on the surface on which the land 21 is formed (see FIG. 3G).

Next, using the resist layer 43 as a plating mask, Au plating and Ni plating are performed on the surface of the raised conductor layer 31 and the electrode pad 21b to form an Au / Ni plating layer 51.
Through the above steps, an electrode pad 21b for connecting the land 21a and the semiconductor chip to one surface of the insulating base 11, and a raised conductor layer for forming a solder ball electrically connected to the land 21a on the other surface BGA type carrier substrate 100 of the present invention in which 31 and Ni / Au plating layer 51 are formed can be obtained (see FIG. 3 (h)).

Further, using the BGA type carrier substrate 100 of the present invention, solder balls 61 are formed by mounting and reflowing solder balls on the raised conductor layer 31 of the BGA type carrier substrate 100.
Furthermore, the semiconductor chip 71 is mounted via the die attach agent 44, the semiconductor chip 71 and the electrode pad 21b are bonded and connected by the bonding wire 72, the solder resist 45 is formed, and the molding resin 46 is molded. A semiconductor device 110 can be obtained (see FIG. 4).

  First, an adhesive tape (Yodogawa X) was bonded to an insulating substrate 11 made of a 25 μm-thick polyimide film (Upilex S) to form a 12 μm-thick adhesive layer 12 (see FIG. 3A).

  Next, punching was performed to form an opening 13 at a predetermined position of the insulating base material 11 on which the adhesive layer 12 was formed, and a desmear process in the opening 13 was performed (FIG. 3B). reference).

  Next, the surface of the adhesive layer 12 of the insulating base material 11 in which the opening 13 is formed and a 25 μm thick copper foil (3EC-VLP) are pressed and heated to bond together, and the insulating base in which the opening 13 is formed. A laminated substrate 20 in which a conductor layer 21 having a thickness of 25 μm was formed on the material 11 was produced (see FIG. 3C).

Next, in order to electrically protect the surface of the conductor layer 21 of the laminated base material 20, a protective layer (not shown) is formed by a method such as attaching a mending tape or the like, and 3-sulfo Using the following copper plating solution to which propyl-disulfide (Rohm and Haas Co., USA) was added, direct current electrolytic copper plug plating was performed using the conductor layer 21 as a cathode, and the surface shape was formed in the opening 13. A 40 μm-thick concave conductive layer 31 was formed (see FIG. 3D).

Composition example of copper plating solution ・ Concentration of copper sulfate: 130g / L
・ Sulfuric acid concentration: 190 g / L
Hydrochloric acid concentration: 100 mg / L
・ Suppressor for copper plating solution (polyethylene glycol): 15mg / L
-Easily soluble copper oxide: appropriate amount-3-sulfopropyl-disulfide (Rohm and Haas: USA): 0.10 ml / L
Here, DC electrolytic copper plug plating uses a horizontal copper plating line (manufactured by Schmitt), current density (set current): 22.5 A / dm2 (12 A × 4), conveyance speed 0.3 m / min, plating time An elevated conductor layer 31 having a thickness of 40 μm and having a concave surface shape was formed in the opening 13 under the plating conditions of 13.8 minutes.

  Next, the protective layer on the conductor layer 21 is stripped to form a resist on the conductor layer 21, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 41. A protective layer 42 was formed on the 31st surface with a mending tape or the like (see FIG. 3 (e)).

  Next, using the resist pattern 41 as an etching mask, the conductor layer 21 is etched with an etching solution made of second copper chloride, the resist pattern 41 and the protective layer 42 are peeled off, and the land 21 and the wiring layer (in particular, FIG. And electrode pads 21b for connecting the semiconductor chip (see FIG. 3F).

  Next, a resist layer 43 for preventing Au / Ni plating was formed at a predetermined position on the surface on which the land 21 was formed (see FIG. 3G).

Next, using the resist layer 43 as a plating mask, the surface of the raised conductor layer 31 and the electrode pad 21b is Au plated to form an Au layer having a thickness of 0.5 μm, and Ni is further plated on the Au layer to form a Ni layer having a thickness of 0.5 μm. The Au / Ni plating layer 51 was formed.
Through the above steps, an electrode pad 21b for connecting the land 21a and the semiconductor chip to one surface of the insulating base 11, and a raised conductor layer for forming a solder ball electrically connected to the land 21a on the other surface BGA type carrier substrate 100 of the present invention in which 31 and Ni / Au plating layer 51 were formed was obtained (see FIG. 3 (h)).

It is a schematic structure sectional view showing one example of a BGA type carrier substrate of the present invention. It is a partial expansion schematic block diagram which shows the surface shape of the raising conductor layer. (A)-(h) is typical structure sectional drawing which shows one Example of the manufacturing method of the BGA type | mold carrier substrate of this invention. It is a schematic cross section showing an example of a semiconductor device manufactured using the BGA type carrier substrate of the present invention. (A) is a schematic top view which shows an example of the conventional conventional tape carrier for semiconductor devices. (B) is a schematic cross-sectional view taken along line A-A ′ of (a). It is a schematic cross section showing an example of a tape carrier for a semiconductor device in which solder balls are formed. (A) is explanatory drawing which shows the enlarged view of the opening part 112 which forms a raising conductor layer. (B) is explanatory drawing which shows an example of the surface shape of the raising conductor layer 151 in an opening part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Insulating base material 12 ... Adhesive material layer 13 ... Opening part 20 ... Laminated base material 21 ... Conductive layer 21a ... Bump 21b ... Electrode pad 31 ... Raised conductive layer 41 ... Resist pattern 42 ... ... Protective layer 43 ... Resist layer 44 ... Die attach agent 45 ... Solder resist 46 ... Mold resin 51 ... Au / Ni layer 61 ... Solder ball 71 ... Semiconductor chip 72 ... Bonding wire 100 ... BGA Type carrier substrate 110 ... semiconductor device 111 ... insulating film 112 ... opening 113 ... device hole 121a ... land 121b ... wiring layer 121c ... inner lead 131 ... solder ball electrode 141 ... solder ball 151 …… Raised conductor layer

Claims (2)

In a method for manufacturing a BGA type carrier substrate in which a pad for mounting a semiconductor chip on one surface and a solder ball electrode and a raised conductor layer are formed on the other surface,
When the raised conductor layer of the solder ball connection pad is formed by DC electrolytic copper plating, the copper plating solution used for electrolytic copper plating is disulfide (disulfide) copper plating additive (accelerator) as 3-sulfo Producing a BGA type carrier substrate characterized in that the surface of the raised conductor layer in contact with the solder ball connection pad is made concave by adding propyl-disulfide in a compounding concentration of 0.04 to 0.15 ml / L. Method.   A BGA type carrier substrate produced by the method for producing a BGA type carrier substrate according to claim 1.