TW201635876A - Circuit board and manufacturing method thereof - Google Patents

Abstract

A circuit board and a manufacturing method thereof are provided. The circuit board includes a dielectric layer, a first circuit layer, a second circuit layer, a conductive through via and a metal bump. The dielectric layer has a first surface and a second surface opposite to each other. The first circuit layer is embedded in the first surface, and the second circuit layer is disposed on the second surface. The conductive through via is disposed in the dielectric layer and connects the first circuit layer and the second circuit layer. The metal bump has a first portion and a second portion, wherein the first portion is disposed in the dielectric layer and the second portion protrudes from the first surface, and a width of the first portion and a width of the second portion are the same.

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board having a width of a top and a bottom of a metal bump and a method of fabricating the same.

In recent years, with the rapid development of electronic technology, more humanized technology products have been introduced, and these technology products are designed to be light, thin, short and small. In order to save costs and increase the degree of integration of circuits on a package substrate, a technique of replacing a conventional package substrate with a buried circuit package substrate has been proposed.

As the bump pitch of electronic products will become smaller and smaller in the future, in the current circuit board process, the configuration of the metal bumps may limit the wiring space of the circuit pattern, which is not conducive to the design of electronic products. . Therefore, how to increase the wiring space is a goal that those skilled in the art are eager to achieve.

The invention provides a circuit board in which the top and bottom of the metal bump The width is the same.

The invention provides a method for manufacturing a circuit board, which can produce metal bumps with the same width of the top and the bottom.

The invention provides a circuit board comprising a first dielectric layer, a first circuit layer, a second circuit layer, a via hole and a metal bump. The first dielectric layer has a first surface and a second surface opposite to each other. The first circuit layer is buried in the first surface, and the second circuit layer is disposed on the second surface. The via hole is disposed in the first dielectric layer and connects the first circuit layer and the second circuit layer. The metal bump has a first portion and a second portion, wherein the first portion is disposed in the first dielectric layer and the second portion is convex from the first surface, and the difference in width between the first portion and the second portion is the second portion Less than 4% of the width.

According to the circuit board of the embodiment of the invention, the circuit board further includes a second dielectric layer disposed on a sidewall of the second portion of the metal bump.

According to the circuit board of the embodiment of the invention, the end surface of the first portion of the metal bump is selectively coplanar with the interface between the first circuit layer and the via hole, and is not limited thereto.

The circuit board according to the embodiment of the present invention, wherein an end surface of the first circuit layer exposed to the first surface of the first dielectric layer is selectively coplanar with the first surface of the first dielectric layer, instead of This is limited.

A wiring board according to an embodiment of the present invention, wherein an edge of the first portion is outside a range enclosed by, for example, an edge of the second portion.

A wiring board according to an embodiment of the invention, wherein an edge of the first portion is, for example, within a range enclosed by an edge of the second portion.

The present invention provides a method of fabricating a wiring board comprising the steps of first forming a sacrificial metal layer having a plurality of first openings of an exposed portion of the carrier plate on the carrier board. Then, a first etch barrier layer covering the sacrificial metal layer is formed on the carrier substrate. Next, a first patterned resist layer is formed on the first etch stop layer, the first patterned resist layer has a plurality of second openings corresponding to the plurality of first openings and a portion exposing a portion of the first etch stop layer An intaglio pattern, wherein a difference in width between the second opening and the first opening is less than 4% of the width of the first opening. Then, metal bumps are formed in the first opening and the second opening, and a first wiring layer is formed in the first intaglio pattern. Then, the first patterned resist layer is removed. Thereafter, a dielectric layer covering the metal bumps and the first wiring layer is formed on the first etch barrier layer. Then, a via hole is formed in the dielectric layer, and a second circuit layer is formed on the dielectric layer, wherein the via hole connects the first circuit layer and the second circuit layer. Thereafter, a second etch stop layer covering the second wiring layer is formed on the dielectric layer. The carrier plate is then separated from the sacrificial metal layer. Thereafter, the sacrificial metal layer, the first etch stop layer and the second etch stop layer are removed.

According to the method of fabricating a circuit board according to the embodiment of the invention, the method of removing the sacrificial metal layer, the first etch stop layer and the second etch stop layer comprises: first performing a first etching process to remove the sacrificial metal layer . Next, a second etching process is performed to remove the first etch stop layer and the second etch stop layer.

A method of fabricating a wiring board according to an embodiment of the present invention, wherein an edge of the second opening is outside a range enclosed by, for example, an edge of the first opening.

A method of fabricating a wiring board according to an embodiment of the present invention, wherein an edge of the second opening is, for example, within a range enclosed by an edge of the first opening.

The present invention provides a method of fabricating a wiring board comprising the steps of first forming a sacrificial metal layer having a plurality of first openings of an exposed portion of the carrier plate on the carrier board. Then, a first etch barrier layer covering the sacrificial metal layer is formed on the carrier substrate. Then, a first patterned resist layer is formed on the first etch stop layer, the first patterned resist layer covers the sidewall of the first opening to form a second opening, and the first patterned resist layer has a exposed portion first A first intaglio pattern of the barrier layer is etched. Then, a metal bump is formed in the second opening, and a first wiring layer is formed in the first intaglio pattern. Then, the first patterned resist layer is removed. Thereafter, a dielectric layer covering the metal bump and the first wiring layer is formed on the first etch barrier layer, and the dielectric layer fills the gap between the first opening and the metal bump. Then, a via hole is formed in the dielectric layer, and a second circuit layer is formed on the dielectric layer, wherein the via hole connects the first circuit layer and the second circuit layer. Thereafter, a second etch stop layer covering the second wiring layer is formed on the dielectric layer. The carrier plate is then separated from the sacrificial metal layer. Thereafter, the sacrificial metal layer, the first etch stop layer and the second etch stop layer are removed.

According to the method of fabricating a circuit board according to the embodiment of the invention, the method of removing the sacrificial metal layer, the first etch stop layer and the second etch stop layer comprises: first performing a first etching process to remove the sacrificial metal layer . Next, a second etching process is performed to remove the first etch stop layer and the second etch stop layer.

Based on the above, in the embodiment of the present invention, the metal bumps having the widths of the top and the bottom are formed, and thus the wiring space of the wiring layer can be effectively increased. In addition, in the embodiment of the present invention, the patterned resist layer covering the sidewall of the opening of the sacrificial metal layer is formed, so that metal bumps having the same width and a small width of the top and the bottom can be formed. Piece. In this way, in addition to effectively increasing the wiring space of the circuit layer, the requirements for component miniaturization can be further met.

The above described features and advantages of the invention will be apparent from the following description.

10, 20‧‧‧ circuit board

100‧‧‧ carrying board

102, 104‧‧‧ copper foil layer

108, 188‧‧‧ etching barrier layer

110‧‧‧Sacrificial metal layer

112, 122‧‧‧ openings

120, 160, 220‧‧‧ patterned resist

124, 164‧‧ ‧ intaglio pattern

130, 230‧‧‧ metal bumps

130a, 230a‧‧‧ part one

130b, 230b‧‧‧ part two

140, 180‧‧‧ circuit layer

150, 150a‧‧‧ dielectric layer

152‧‧‧metal layer

152a‧‧‧ patterned metal layer

154‧‧‧Blind hole

154a, 154b‧‧‧ surface

170‧‧‧through holes

222‧‧‧ openings

W‧‧‧Width

W1, W2‧‧‧ width difference

1A to FIG. 1F are schematic cross-sectional views showing a manufacturing process of a circuit board according to a first embodiment of the present invention.

2A and 2B are enlarged cross-sectional views showing a metal bump according to a first embodiment of the present invention.

3A to 3E are schematic cross-sectional views showing a manufacturing process of a circuit board according to a second embodiment of the present invention.

1A to FIG. 1F are schematic cross-sectional views showing a manufacturing process of a circuit board according to a first embodiment of the present invention. 2A and 2B are enlarged cross-sectional views showing a metal bump according to a first embodiment of the present invention.

First, referring to FIG. 1A, a sacrificial metal layer 110 is formed on the carrier board 100. In this embodiment, the carrier layer 100 may be formed with a copper foil layer 102 and 104, and a peeling layer (not shown) disposed between the copper foil layers 102 and 104, but the invention is not limited thereto. In other embodiments, the carrier board 100 may not have the copper foil layer 102 and 104. The thickness of the copper foil layer 102 is, for example, between 5 μm and 40 μm, and the thickness of the copper foil layer 104 is, for example, between 1 μm and 10 μm. The copper foil layers 102 and 104 may facilitate separation of the carrier sheet 100 from the circuit board to be formed in a subsequent process. The sacrificial metal layer 110 has a plurality of openings 112. Metal bumps are formed in the openings 112 in subsequent processes. The sacrificial metal layer 110 is, for example, a copper layer, but the invention is not limited thereto. The formation method of the sacrificial metal layer 110 is, for example, an electroplating process. In the present embodiment, the opening 112 exposes a portion of the carrier plate 100.

Then, an etch stop layer 108 is formed on the carrier board 100. The etch stop layer 108 covers the sacrificial metal layer 110 and the carrier plate 100 exposed by the opening 112. The etch stop layer 108 is, for example, a nickel layer. The method of forming the etch stop layer 108 is, for example, an electroplating process. In the present embodiment, the etch rate of the etch stop layer 108 needs to be less than the etch rate of the sacrificial metal layer 110. Therefore, the etch stop layer 108 can be protected from being formed on the etch stop layer 108 in the subsequent step of removing the sacrificial metal layer 110 by an etch process. The metal bumps covered are covered with the wiring layer so that they are not etched.

Next, referring to FIG. 1B, a patterned resist layer 120 is formed on the etch stop layer 108. The patterned resist layer 120 is, for example, a dry film or a liquid photoresist. The patterned resist layer 120 has a plurality of openings 122 corresponding to the plurality of openings 112. Due to the process tolerance when forming the patterned resist layer 120, the width of the opening 122 and the width of the opening 112 may be slightly different. For example, the edge of each opening 122 may be slightly convex compared to the edge of the opening 112 below (ie, the width of each opening 122 is slightly larger than the width of the opening 112, the opening 122 The edge is outside the range enclosed by the edge of the opening 112; or the edge of each opening 122 and the edge of the opening 112 below The edge may also be slightly retracted (i.e., the width of each opening 122 is slightly smaller than the width of the opening 112, and the edge of the opening 122 is within the range enclosed by the edge of the opening 112). However, regardless of whether the width of the opening 122 is larger than the width of the opening 112 or smaller than the width of the opening 112, the difference in width between the opening 122 and the opening 112 is less than 4% of the width of the opening 112.

In addition, since the difference in width between the opening 122 and the opening 112 is only 4% or less of the width of the opening 112, it can be considered that the edge of the opening 122 is aligned with the edge of the opening 112 (as shown in FIG. 1B, The edge of the opening 122 is aligned with the etch stop layer 108, but since the thickness of the etch stop layer 108 is small, it can be considered that the edge of the opening 122 is aligned with the edge of the opening 112. In addition, the patterned resist layer 120 also has an intaglio pattern 124 exposing a portion of the etch stop layer 108.

Thereafter, a metal layer is formed in the openings 112, 122 and the recess pattern 124, thereby forming metal bumps 130 in the openings 112 and 122, and forming the wiring layer 140 in the recess patterns 124. The metal layer is, for example, a copper layer. The method of forming the metal layer is, for example, an electroplating process. The formed metal bump 130 has a first portion 130a and a second portion 130b, wherein the first portion 130a is formed in the opening 122 and the second portion 130b is formed in the opening 112.

As shown in FIG. 2A, when the edge of the opening 122 slightly protrudes from the edge of the opening 112, the width of the first portion 130a is slightly larger than the width of the second portion 130b, and the edge of the first portion 130a is at the second. The edge of the portion 130b is outside the range enclosed. What is important is that the difference in width between the opening 122 and the opening 112 is less than 4% of the width of the opening 112, and therefore, the first portion 130a and the second portion 130b The total difference between the width differences W1 and W2 is 4% or less of the width W of the second portion 130b. As shown in FIG. 1B, the formed metal bumps 130 may have a cross-section of a "|" shape whose overall width is nearly uniform.

As shown in FIG. 2B, when the edge of the opening 122 is slightly retracted from the edge of the opening 112, the width of the first portion 130a is slightly smaller than the width of the second portion 130b, and the edge of the first portion 130a is at the second. The edge of the portion 130b is enclosed within the range. It is important that the difference in width between the opening 122 and the opening 112 is less than 4% of the width of the opening 112. Therefore, the total difference between the widths W1 and W2 between the first portion 130a and the second portion 130b is the same. The width W of the two portions 130b is 4% or less. As shown in FIG. 1B, the formed metal bumps 130 may have a cross-section of a "|" shape whose overall width is nearly uniform.

Then, referring to FIG. 1C, after the patterned resist layer 120 is removed, a dielectric layer 150 is formed on the etch stop layer 108. The dielectric layer 150 covers the etch stop layer 108, the first portion 130a, and the wiring layer 140. The dielectric layer 150 is, for example, a prepreg. In the present embodiment, the dielectric layer 150 is formed on the etch stop layer 108 by press bonding. In addition, in the embodiment, the dielectric layer 150 may also be attached with a metal layer 152. The metal layer 152 is, for example, a copper layer. however. The invention is not limited thereto. In other embodiments, the metal layer 152 may not be attached to the dielectric layer 150.

Next, a blind via 154 exposing a portion of the wiring layer 140 is formed in the dielectric layer 150 and the metal layer 152. A method of forming the blind holes 154 is, for example, a laser drilling. Thereafter, a patterned resist layer 160 is formed on the dielectric layer 150 and the metal layer 152. The patterned resist layer 160 has exposed the blind vias 154 and a portion of the metal layer 152 (if the metal layer 152 is not formed, Then, an intaglio pattern 164 exposing a portion of the dielectric layer 150) is exposed. Thereafter, a metal layer is formed in the blind via 154 and the recessed pattern 164, thereby forming a via hole 170 in the blind via 154, and forming a wiring layer 180 in the recess pattern 164, wherein the via 170 connects the wiring layer 140 and the wiring Layer 180. The metal layer is, for example, a copper layer. The method of forming the metal layer is, for example, an electroplating process.

Next, referring to FIG. 1D, the patterned resist layer 160 is removed. Thereafter, an etch stop layer 188 is formed on the dielectric layer 150 and the metal layer 152, and the etch stop layer 188 covers the circuit layer 180 and the portion of the metal layer 152. The formation method and effect of the etch stop layer 188 are similar to those of the etch stop layer 108 described above, and thus the description thereof will not be repeated.

Then, referring to FIG. 1E, the carrier board 100 is separated from the sacrificial metal layer 110. In the present embodiment, since the carrier sheet 100 has the copper foil layers 102 and 104 thereon, the copper foil layer can be easily passed through the peeling layer (not shown) during the process of separating the carrier sheet 100 from the sacrificial metal layer 110. The copper foil layer 104 is detached to separate the carrier sheet 100 from the sacrificial metal layer 110.

Thereafter, referring to FIG. 1F, a first etching process is performed to remove the sacrificial metal layer 110. In the present embodiment, in addition to removing the sacrificial metal layer 110, the copper foil layer 104 underlying the sacrificial metal layer 110 is simultaneously removed to expose the etch stop layer 108. Since the etching rate of the etching resist layer 108 is smaller than the etching rate of the sacrificial metal layer 110 and the copper foil layer 104, only the sacrificial metal layer 110 and the copper foil layer 104 are removed during the first etching process, and the etching is not performed. The barrier layer 108 is etched. Therefore, the etch stop layer 108 has a protective effect on the metal bumps 130 and the wiring layer 140 covered thereby, so that it is not etched.

Thereafter, a second etching process is performed to remove the etch stop layer 108 and the etch stop layer 188. In the second etch process, the etchant used etches only the etch stop layer 108 and the etch stop layer 188 without damaging the circuit layers 140, 180 and the metal bumps 130. In this embodiment, after the etch stop layer 108 and the etch stop layer 188 are removed, a third etch process is performed to remove a portion of the metal layer 152 to form a patterned metal layer 152a. In this way, the production of the circuit board 10 can be completed.

The circuit board of the present invention will be described below by taking FIG. 1F as an example. Referring to FIG. 1F , the circuit board 10 includes a dielectric layer 150 , circuit layers 140 and 180 , via holes 170 , and metal bumps 130 . The dielectric layer 150 has surfaces 154a and 154b opposite to each other. The circuit layer 140 is buried in the surface 154a, and the end surface of the circuit layer 140 exposed to the first surface 154a is selectively coplanar with the surface 154a, and is not limited thereto. In addition, the wiring layer 180 is disposed on the surface 154b. The via hole 170 is disposed in the dielectric layer 150 and connects the wiring layers 140 and 180.

As shown in FIG. 1F, the metal bump 130 has a first portion 130a disposed in the dielectric layer 150 and a second portion 130b protruding from the surface 154a. In addition, the end surface of the first portion 130a is selectively coplanar with the interface between the circuit layer 140 and the via 170, and is not limited thereto. What is important is that the cross section of the metal bumps 130 can have a nearly uniform "|" shape, thereby avoiding the metal bumps 130 occupying the space around them, thereby effectively increasing the wiring space of the circuit layers.

3A to 3E are schematic cross-sectional views showing a manufacturing process of a circuit board according to a second embodiment of the present invention. It must be stated here that Figure 3A to Figure 3E The embodiment shown in the drawings is similar to the embodiment shown in FIG. 1A to FIG. 1F. Therefore, the following embodiments will use the same reference numerals and parts in the foregoing embodiments, and the same reference numerals will be used to refer to the same or similar elements. A description of the same technical content. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

Referring to FIG. 3A, after the step of FIG. 1A, a patterned resist layer 220 is formed on the etch stop layer 108. The patterned resist layer 220 also has an intaglio pattern 124 that exposes a portion of the etch stop layer 108. However, the difference from the patterned resist layer 120 is that the patterned resist layer 220 covers the sidewalls of the openings 112 to form the openings 222. As shown in FIG. 3A, the width of the opening 222 is smaller than the width of the opening 112.

Thereafter, a metal layer is formed in the opening 222 and the recessed pattern 124, thereby forming the metal bumps 230 in the openings 222 and forming the wiring layer 140 in the recess patterns 124. The metal layer is, for example, a copper layer. The method of forming the metal layer is, for example, an electroplating process. The formed metal bump 230 has a first portion 230a and a second portion 230b, wherein the first portion 230a protrudes from the surface of the sacrificial metal layer 108 and the second portion 230b is located within the opening 112. Importantly, since the opening 222 is formed by covering the sidewall of the opening 112 by the patterned resist layer 220, the first portion 230a and the second portion 230b are formed to have the same width. In other words, the formed metal bumps 230 may have a "|" shape with a uniform overall width.

In addition, since the width of the opening 222 is smaller than the width of the opening 112, the width of the metal bump 230 is relatively smaller than the width of the metal bump 130 in the first embodiment described above. However, it is not limited thereto, and the width and the opening of the opening 112 can be adjusted according to actual needs. The case resist layer 220 covers the thickness of the sidewall of the opening 112 to adjust the width of the formed opening 222, thereby adjusting the width of the metal bump 230 formed in the opening 222.

Next, referring to FIG. 3B, after the patterned resist layer 220 is removed, the dielectric layer 150 is formed on the etch stop layer 108. The dielectric layer 150 covers a portion of the etch stop layer 108, the first portion 230a and the wiring layer 140, and fills the gap between the second portion 230b and the opening 112 (hereinafter referred to as the dielectric layer 150a). In other words, the dielectric layer 150a is disposed on the sidewall of the second portion 230b and covers a portion of the etch stop layer 108. In more detail, the thickness of the sidewall of the opening 112 can be covered by adjusting the patterned resist layer 220 to adjust the thickness of the dielectric layer 150a. In this way, the thickness of the dielectric layer 150a can be selectively minimized as needed, so that the performance of the circuit board formed in the subsequent process is not affected. The dielectric layer 150 is, for example, a semi-cured film. In the present embodiment, the dielectric layer 150 is formed on the etch stop layer 108 by press bonding. In addition, similar to the first embodiment described above, the dielectric layer 150 may also be provided with a metal layer 152.

Next, a via hole 170 is formed in the dielectric layer 150, and a wiring layer 180 is formed on the dielectric layer 150, wherein the via hole 170 connects the wiring layer 140 and the wiring layer 180. The process for forming the via hole 170 and the wiring layer 180 has been described in detail in the above first embodiment, and thus the detailed description thereof will not be repeated here.

Thereafter, referring to FIG. 3C, similar to the steps described in FIG. 1D, the patterned resist layer 160 is removed. Thereafter, an etch stop layer 188 is formed on the dielectric layer 150 and the metal layer 152, and the etch stop layer 188 covers the circuit layer 180 and the portion of the metal layer 152.

Then, referring to FIG. 3D, similar to the steps described in FIG. 1E, the bearer will be carried. The board 100 is separated from the sacrificial metal layer 110.

Thereafter, referring to FIG. 3E, the sacrificial metal layer 110 is removed similarly to the steps described in FIG. 1F. Similar to the first embodiment described above, in addition to removing the sacrificial metal layer 110, the copper foil layer 104 underlying the sacrificial metal layer 110 is simultaneously removed, exposing the etch stop layer 108. Thereafter, a second etching process is performed to remove the etch stop layer 108 and the etch stop layer 188. In this embodiment, after the etch stop layer 108 and the etch stop layer 188 are removed, a third etch process can be performed to form the patterned metal layer 152a. In this way, the production of the circuit board 20 can be completed.

The circuit board of the present invention will be described below by taking FIG. 3E as an example. Referring to FIG. 3E, similar to the circuit board 10 shown in FIG. 1F, the circuit board 20 includes a dielectric layer 150, circuit layers 140 and 180, via holes 170, and metal bumps 230. The width of the first portion 230a of the metal bump 230 is the same as the width of the second portion 230b, and the cross section of the metal bump 230 may have a "|" shape with a uniform overall width. However, the difference from the wiring board 10 is that the width of the metal bumps 230 is smaller than the width of the metal bumps 130 in the wiring board 10. Therefore, in addition to effectively increasing the wiring space of the circuit layer, the requirements for component miniaturization can be further met. In addition, the circuit board 20 also has a dielectric layer 150a disposed on a sidewall of the second portion 230b.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ circuit board

130‧‧‧Metal bumps

130a‧‧‧Part 1

130b‧‧‧Part II

140, 180‧‧‧ circuit layer

150‧‧‧ dielectric layer

152a‧‧‧ patterned metal layer

154a, 154b‧‧‧ surface

170‧‧‧through holes

Claims (12)

A circuit board comprising: a first dielectric layer having first and second surfaces opposite to each other; a first circuit layer buried in the first surface; and a second circuit layer disposed in the second a via hole disposed in the first dielectric layer and connecting the first circuit layer and the second circuit layer; and a metal bump having a first portion and a second portion, wherein the first portion Arranged in the first dielectric layer and the second portion protrudes from the first surface, and a difference in width between the first portion and the second portion is a width of the second portion 4% or less. The circuit board of claim 1, further comprising a second dielectric layer disposed on a sidewall of the second portion. The circuit board of claim 1, wherein an end surface of the first portion is coplanar with an interface between the first circuit layer and the via hole. The circuit board of claim 1, wherein an end surface of the first circuit layer exposed to the first surface is coplanar with the first surface. The circuit board of claim 1, wherein an edge of the first portion is outside a range enclosed by an edge of the second portion. The circuit board of claim 1, wherein an edge of the first portion is within a range enclosed by an edge of the second portion. A method for manufacturing a circuit board, comprising: Forming a sacrificial metal layer on the carrier plate, the sacrificial metal layer having a plurality of first openings exposing a portion of the carrier plate; forming a first etch barrier layer on the carrier plate, the first etch barrier layer covering a sacrificial metal layer; forming a first patterned resist layer on the first etch stop layer, the first patterned resist layer having a plurality of second openings corresponding to the plurality of first openings and Exposing a portion of the first indentation pattern of the first etch stop layer, wherein a difference in width between the second opening and the first opening is less than 4% of a width of the first opening; Forming a metal bump in the first opening and the second opening, and forming a first wiring layer in the first intaglio pattern; removing the first patterned resist layer; Forming a dielectric layer on the first etch barrier layer, the dielectric layer covering the metal bump and the first circuit layer; forming a via hole in the dielectric layer and forming on the dielectric layer a second circuit layer, wherein the via hole connects the first circuit layer and the second circuit layer; Forming a second etch stop layer on the dielectric layer, the second etch stop layer covering the second circuit layer; separating the carrier plate from the sacrificial metal layer; and removing the sacrificial metal layer, The first etch stop layer and the second etch stop layer. The method for manufacturing a circuit board according to claim 7 of the patent application, wherein The method of removing the sacrificial metal layer, the first etch stop layer and the second etch stop layer includes: performing a first etching process to remove the sacrificial metal layer; and performing a second etching process to remove the The first etch stop layer and the second etch stop layer are described. The method of fabricating a circuit board according to claim 7, wherein an edge of the second opening is outside a range enclosed by an edge of the first opening. The method of fabricating a circuit board according to claim 7, wherein an edge of the second opening is within a range enclosed by an edge of the first opening. A method for fabricating a circuit board, comprising: forming a sacrificial metal layer on a carrier plate, the sacrificial metal layer having a plurality of first openings exposing a portion of the carrier plate; forming a first etch barrier layer on the carrier plate The first etch barrier layer covers the sacrificial metal layer; forming a first patterned resist layer on the first etch stop layer, the first patterned resist layer covering the sidewall of the first opening to form a second opening, and the first patterned resist layer has a first intaglio pattern exposing a portion of the first etch stop layer; a metal bump is formed in the second opening, and Forming a first circuit layer in a recessed pattern; removing the first patterned resist layer; forming a dielectric layer on the first etch stop layer, the dielectric layer covering the a metal bump and the first circuit layer, and filling a gap between the first opening and the metal bump; forming a via hole in the dielectric layer, and on the dielectric layer Forming a second wiring layer, wherein the via hole connects the first circuit layer and the second circuit layer; forming a second etch barrier layer on the dielectric layer, the second etch barrier layer covering the a second wiring layer; separating the carrier plate from the sacrificial metal layer; and removing the sacrificial metal layer, the first etch stop layer, and the second etch stop layer. The method of fabricating a circuit board according to claim 11, wherein the method of removing the sacrificial metal layer, the first etch stop layer and the second etch stop layer comprises: performing a first etching process, Removing the sacrificial metal layer; and performing a second etching process to remove the first etch stop layer and the second etch stop layer.