TWI643534B - Circuit board structure and manufacturing method thereof - Google Patents

Abstract

A circuit board structure includes an insulating substrate, a first circuit layer, a capacitor dielectric layer, a first dielectric layer and a second circuit layer. The insulating substrate has a plurality of first through holes and a second through hole. The first circuit layer includes a first capacitor electrode, an inductor line, a plurality of first conductive vias, and a second conductive via. The inductor line and the first conductive via define a three-dimensional inductance in a spiral form through the insulating substrate. A third via of the first dielectric layer penetrates the first dielectric layer and is located within the second conductive via. The second conductive via defines a coaxial via with a third conductive via. The first capacitor electrode, the capacitor dielectric layer, and a second capacitor electrode of the second circuit layer define a capacitor.

Description

Circuit board structure and manufacturing method thereof

The present invention relates to a circuit board structure and a method of fabricating the same, and more particularly to a circuit board structure having a plurality of applications and a method of fabricating the same.

Multilayer circuit boards having at least two wiring layers today typically have conductive via structures to allow these circuit layers to be electrically conductive. At present, most methods for forming a conductive via structure are first to form a via hole by mechanical drilling or laser drilling, and then through a via plating process to complete the conductive via structure. However, the space in the through hole is an ineffective area. In addition to being easy to cause space waste, it cannot increase the wiring density and provide better design flexibility.

The present invention provides a circuit board structure which has better design flexibility, a thin overall thickness, and can be used in various applications.

The invention also provides a method for manufacturing a circuit board structure, which is used for making The circuit board structure described.

The circuit board structure of the present invention comprises an insulating substrate, a first circuit layer, a capacitor dielectric layer, a first dielectric layer and a second circuit layer. The insulating substrate has a first surface and a second surface opposite to each other and a plurality of first through holes and a second through hole connecting the first surface and the second surface. The first circuit layer is disposed on the insulating substrate and exposes a portion of the first surface and the second surface. The first circuit layer includes a first capacitor electrode, an inductor line, a plurality of first conductive vias and a second conductive via. The first capacitor electrode is located on the first surface. The inductor line is located on the first surface and the second surface. The first conductive via covers the inner wall of the first via. The second conductive via covers the inner wall of the second via. The inductor line and the first conductive via define a three-dimensional inductance in a spiral form through the insulating substrate. The capacitor dielectric layer is disposed on a portion of the first capacitor electrode. The first dielectric layer covers the first circuit layer and the first surface and the second surface of the insulating substrate exposed by the first circuit layer, and fills the first conductive via and the second conductive via. The first dielectric layer has a third through hole, a first blind hole and a first opening. The third via hole penetrates through the first dielectric layer and is located in the second conductive via. The first opening exposes a capacitive dielectric layer. The first blind via exposes a portion of the first wiring layer. The second circuit layer is disposed on the first dielectric layer and includes a second line, a third conductive via, a first conductive via and a second capacitor. The second line is disposed on a portion of the first dielectric layer. The third conductive via covers the inner wall of the third via. The first conductive blind via fills the first blind via and connects the first wiring layer and the second wiring layer. The second capacitor electrode fills the first opening. The second conductive via defines a coaxial via with the third conductive via. The first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode define a capacitor.

In an embodiment of the invention, the circuit board structure further includes a second dielectric layer and a third circuit layer. The second dielectric layer is disposed on the second circuit layer, covers the second circuit layer, and fills the third conductive via. The second dielectric layer has a plurality of second blind vias and the second blind vias expose a portion of the second trace layer. The third circuit layer is disposed on a portion of the second dielectric layer and fills the second blind via, wherein the third circuit layer is electrically connected to the second circuit layer.

In an embodiment of the invention, the circuit board structure further includes a solder resist layer disposed on the second dielectric layer, covering the second dielectric layer, and exposing a portion of the third circuit layer, and defining at least A pad.

In an embodiment of the invention, the circuit board structure further includes a sub-layer disposed between the third circuit layer and the second dielectric layer.

In an embodiment of the invention, the circuit board structure further includes a sub-layer disposed between the second circuit layer and the first dielectric layer.

The manufacturing method of the circuit board structure of the present invention comprises the following steps. An insulating substrate is provided. The insulating substrate has a first surface and a second surface opposite to each other and a plurality of first through holes and a second through hole connecting the first surface and the second surface. A first wiring layer is formed on the insulating substrate. The first circuit layer exposes a portion of the first surface and the second surface, and includes a first capacitor electrode, an inductor line, a plurality of first conductive vias and a second conductive via. The first capacitor electrode is located on the first surface. The inductor line is located on the first surface and the second surface. The first conductive via covers the inner wall of the first via. The second conductive via covers the inner wall of the second via. The inductor line and the first conductive via define a three-dimensional inductance in a spiral form through the insulating substrate. Form an electric The dielectric layer is on a portion of the first capacitor electrode. Pressing a first dielectric layer on the first circuit layer. The first dielectric layer covers the first circuit layer and the first surface and the second surface of the insulating substrate exposed by the first circuit layer, and fills the first through hole and the second through hole. Forming a third via, a first via, and a first opening in the first dielectric layer. The third via hole penetrates through the first dielectric layer and is located in the second conductive via. The first opening exposes a capacitive dielectric layer. The first blind via exposes a portion of the first wiring layer. Forming a second wiring layer on the first dielectric layer. The second circuit layer covers a portion of the first dielectric layer and the inner wall of the third via hole and fills the first blind via and the first opening. The second circuit layer includes a second line, a third conductive via, a first conductive via and a second capacitor. The second line is disposed on a portion of the first dielectric layer. The third conductive via covers the inner wall of the third via. The first conductive blind via fills the first blind via and connects the first wiring layer and the second wiring layer. The second capacitor electrode fills the first opening. The second conductive via defines a coaxial via with the third conductive via. The first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode define a capacitor.

In an embodiment of the invention, the method for fabricating the circuit board structure further includes: forming a second dielectric layer on the second circuit layer. The second dielectric layer covers the second wiring layer and fills the third via. A plurality of second blind vias are formed on the second dielectric layer, wherein the second blind vias expose a portion of the second wiring layer. Forming a third circuit layer on a portion of the second dielectric layer and filling the second blind via, wherein the third circuit layer is electrically connected to the second circuit layer.

In an embodiment of the invention, the method for fabricating the circuit board structure further includes forming a solder resist layer on the second dielectric layer. The solder mask covers the second dielectric The layer, and exposing the third circuit layer, defines at least one pad.

In an embodiment of the invention, the method for fabricating the circuit board structure further includes forming a sub-layer between the third circuit layer and the second dielectric layer.

In an embodiment of the invention, the method for fabricating the circuit board structure further includes forming a sub-layer between the second circuit layer and the first dielectric layer.

Based on the above, in the design of the circuit board structure of the present invention, the second conductive via covers the inner wall of the second via, and the third via penetrates the first dielectric layer and is located in the second conductive via, and The three conductive vias cover the inner wall of the third via, wherein the second conductive via defines a coaxial via with the third conductive via. That is to say, the circuit board structure of the present invention can effectively utilize the space in the second through hole to make a coaxial through hole suitable for high frequency communication, and can have better design flexibility. Furthermore, the circuit board structure of the present invention has three structural components of three different characteristics, such as a three-dimensional inductor, a coaxial through hole, and a capacitor, which can be diversified and have a thin overall thickness. Further, in the method of fabricating the wiring board structure of the present invention, the coaxial via hole and the capacitor are simultaneously defined when the second wiring layer is formed. That is to say, in the same process step, the coaxial via hole and the capacitor are completed at the same time, which can effectively reduce the process time and the production cost.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Three-dimensional inductance

20‧‧‧Coaxial through hole

30‧‧‧ Capacitance

100‧‧‧Circuit board structure

110‧‧‧Insulating substrate

112‧‧‧ first surface

114‧‧‧ second surface

116‧‧‧First through hole

118‧‧‧Second through hole

120‧‧‧First line layer

122‧‧‧First Capacitance Electrode

124‧‧‧Inductance line

126‧‧‧First conductive via

128‧‧‧Second conductive via

130‧‧‧Capacitive dielectric layer

140‧‧‧First dielectric layer

142‧‧‧ third through hole

144‧‧‧ first opening

146‧‧‧First blind hole

150‧‧‧second circuit layer

152‧‧‧second line

154‧‧‧ Third conductive via

156‧‧‧First conductive blind hole

158‧‧‧Second capacitor electrode

160‧‧‧Second dielectric layer

162‧‧‧ second blind hole

170‧‧‧ third circuit layer

172‧‧‧ third line

174‧‧‧Second conductive column

180‧‧‧ solder mask

S1, S2‧‧‧ seed layer

P‧‧‧ pads

1A to 1J illustrate a circuit board structure according to an embodiment of the present invention. A schematic cross-sectional view of the fabrication process.

2A is a top plan view showing the three-dimensional inductor of the circuit board structure of FIG. 1B.

2B is a perspective view of the three-dimensional inductor of FIG. 2A.

1A to 1J are schematic cross-sectional views showing a method of fabricating a circuit board structure according to an embodiment of the invention. 2A is a top plan view showing the three-dimensional inductor of the circuit board structure of FIG. 1B. 2B is a perspective view of the three-dimensional inductor of FIG. 2A. Regarding the manufacturing method of the circuit board structure of the present embodiment, first, referring to FIG. 1A and FIG. 2A, an insulating substrate 110 is provided, wherein the insulating substrate 110 is, for example, a glass substrate, a ceramic substrate, or a polymer glass fiber composite substrate. , a polyimide (PI) glass fiber composite substrate, a dielectric layer having a single layer or a plurality of dielectric materials, a single layer or a multilayer circuit board having a dielectric material and an inner layer buried with an inner layer, but the present invention Not limited to this. Here, the insulating substrate 110 has a first surface 112 and a second surface 114 opposite to each other and a plurality of first through holes 116 and a second through holes 118 connecting the first surface 112 and the second surface 114 .

Next, referring to FIG. 1B, FIG. 2A and FIG. 2B, a first wiring layer 120 is formed on the insulating substrate 110. The first circuit layer 120 exposes a portion of the first surface 112 and a portion of the second surface 114 of the insulating substrate 110, and includes a first capacitor electrode 122, an inductor line 124, a plurality of first conductive vias 126 and a second Conductive through hole 128. That is, the first circuit layer 120 is a patterned circuit layer. The first capacitor electrode 122 is located on the first surface 112, and the inductor line 124 is located on the first surface 112. With the second surface 114. The first conductive via 126 covers the inner wall of the first via 116 while the second conductive via 128 covers the inner wall of the second via 118. In particular, the inductor circuit 124 and the first conductive via 126 extend through the insulating substrate 110 in a spiral form to define a three-dimensional inductor 10. Here, the maintenance of the three-dimensional inductor 10 can be preferably performed by using the insulating substrate 110.

Next, referring to FIG. 1C, a capacitor dielectric layer 130 is formed on a portion of the first capacitor electrode 122. Here, the capacitor dielectric layer 130 covers only a portion of the first circuit layer 120. The material of the capacitor dielectric layer 130 includes aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN). , samarium oxide (SiO ₂ ), tantalum nitride (Si ₃ N ₄ ), hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), lanthanum oxide (Lanthanum oxide; La ₂ O ₃ ), other similar metal oxide materials, metal nitride materials or other suitable high-k materials.

Next, referring to FIG. 1D, a first dielectric layer 140 is pressed onto the first circuit layer 120 by thermal compression bonding. Here, the first dielectric layer 140 covers the first surface 112 and the first surface 112 and the second surface 114 of the insulating substrate 110 exposed by the first circuit layer 120 and the first circuit layer 120, and fills the first through holes 116 and the first Two through holes 118.

Referring to FIG. 1D again, a third through hole 142, a first opening 144 and a first blind hole 146 are formed on the first dielectric layer 140 by laser drilling. The third via 142 extends through the first dielectric layer 140 and is located in the second conductive via 128, and the first opening 144 exposes the capacitor dielectric layer 130 and the first blind via 146 is exposed. A portion of the first circuit layer 120 is exited. Here, as shown in FIG. 1D , the aperture of the third through hole 142 is gradually reduced from the first surface 112 of the insulating substrate 110 to the second surface 114 , but is not limited thereto. In other embodiments not shown, the aperture of the third through hole 142 may also be gradually reduced from the second surface 114 of the insulating substrate 110 toward the first surface 112; or, from the first surface of the insulating substrate 110. Both 112 and second surface 114 maintain a certain value, which is still within the scope of the present invention.

Next, referring to FIG. 1E, a sub-layer S1 is formed on the first dielectric layer 140 by electroless plating or other means, wherein the material of the seed layer S1 is, for example, copper. Here, the seed layer S1 completely covers the first dielectric layer 140, the inner wall of the third through hole 142, the inner wall of the first opening 144, and the inner wall of the first blind hole 146, and is directly exposed to the first opening 144. The capacitor dielectric layer 130 and the other portion of the first circuit layer 120 exposed by the first blind via 146.

Next, referring to FIG. 1F, a second wiring layer 150 is formed on the first dielectric layer 140 by, for example, a semi-additive process (SAP), wherein the seed layer S1 can serve as a plating seed layer. The second circuit layer 150 covers a portion of the first dielectric layer 140 and the inner wall of the third through hole 142 and fills the first opening 144 and the first blind hole 146. Furthermore, the second circuit layer 150 includes a second line 152, a third conductive via 154, a first conductive via 156 and a second capacitor electrode 158. The second line 152 is disposed on a portion of the first dielectric layer 140, and the third conductive via 154 covers the inner wall of the third via 142. The first conductive via 156 fills the first blind via 146 and connects the first wiring layer 120 and the second wiring layer 150. The second capacitor electrode 158 fills the first opening 144. In particular, the second conductive vias 128 and the third conductive vias 154 A coaxial via 20 is defined, and the first capacitor electrode 122, the capacitor dielectric layer 130 and the second capacitor electrode 158 define a capacitor 30.

The second conductive via 128 of the present embodiment covers the inner wall of the second via 118, and the third via 142 penetrates the first dielectric layer 140 and is located in the second conductive via 128, and the third conductive via 154 covers the inner wall of the third through hole 142 , wherein the second conductive through hole 128 and the third conductive through hole 154 define a coaxial through hole 20 . That is to say, the present embodiment can effectively utilize the space in the second through hole 118 to fabricate the coaxial through hole 20 suitable for high frequency communication (for example, at least 90 GHz or more), which can have better design flexibility. Further, when the second wiring layer 150 is formed, the coaxial via 20 and the capacitor 30 are simultaneously defined. That is to say, in the same process step, the fabrication of the coaxial via 20 and the capacitor 30 is completed at the same time, which can effectively reduce the processing time and the production cost.

Next, referring to FIG. 1G, a second dielectric layer 160 is formed on the second circuit layer 150 by thermal compression. Here, the second dielectric layer 160 covers the second line 152 of the second circuit layer 150 and the first dielectric layer 140 and fills the third via 142.

Next, referring to FIG. 1H, a plurality of second blind vias 162 are formed on the second dielectric layer 160 by laser drilling, wherein the second blind vias 162 expose a portion of the second wiring layer 150, that is, the exposed A portion of the second line 152 of the second circuit layer 150.

Thereafter, referring to FIG. 1H and FIG. 1I, a sub-layer S2 is formed on the second dielectric layer 160, and then a third wiring layer 170 is formed on the second dielectric layer 160, for example, by a semi-additive method. Fill the second blind hole 162. Here, the third circuit layer 170 A third line 172 and a plurality of second conductive pillars 174 are disposed, wherein the third line 172 is disposed on the second dielectric layer 160, and the second conductive pillars 174 fill the second blind vias 162, and the third wiring layer 170 The third line 172 is electrically connected to the second circuit layer 150 via the second conductive pillar 174 and the second wiring layer 152 exposed by the second blind via 162 of the second dielectric layer 160. The seed layer S2 is located between the third line 172 and the second dielectric layer 160 of the third circuit layer and between the second conductive pillar and the second dielectric layer 160.

Finally, referring to FIG. 1J, a solder resist layer 180 is formed on the second dielectric layer 160. The solder resist layer 180 covers the second dielectric layer 160 and exposes a portion of the third line 172 of the third circuit layer 170, and defines at least one pad P (two are schematically depicted in FIG. 1J). So far, the fabrication of the circuit board structure 100 has been completed.

Structurally, referring again to FIG. 1J, the circuit board structure 100 includes an insulating substrate 110, a first wiring layer 120, a capacitor dielectric layer 130, a first dielectric layer 140, and a second wiring layer 150. The insulating substrate 110 has a first surface 112 and a second surface 114 opposite to each other and a first through hole 116 and a second through hole 118 that connect the first surface 112 and the second surface 114. The first circuit layer 120 is disposed on the insulating substrate 110 and exposes a portion of the first surface 112 and the second surface 114. The first circuit layer 120 includes a first capacitor electrode 122, an inductor line 124, a first conductive via 126 and a second conductive via 128. The first capacitor electrode 122 is located on the first surface 112, and the inductor line 124 is located on the first surface 112 and the second surface 114. The first conductive via 126 covers the inner wall of the first via 116 while the second conductive via 128 covers the inner wall of the second via 118. The inductor line 124 and the first conductive via 126 extend through the insulating substrate 110 in a spiral form to define a three-dimensional inductor 10. The capacitor dielectric layer 130 is disposed on the first capacitor electrode 122 Part of it. The first dielectric layer 140 covers the first surface 112 and the second surface 114 of the insulating substrate 110 exposed by the first circuit layer 120 and the first circuit layer 120, and fills the first conductive via 126 and the second conductive Through hole 128. The first dielectric layer 140 has a third through hole 142 , a first opening 144 , and a first blind hole 146 . The third via 142 extends through the first dielectric layer 140 and is located within the second conductive via 128. The first opening 144 exposes the capacitive dielectric layer 130. The first blind via 146 exposes a portion of the first wiring layer 120. The second circuit layer 150 is disposed on the first dielectric layer 140 and includes a second line 152 , a third conductive via 154 , a first conductive via 156 and a second capacitor electrode 158 . The second line 152 is disposed on a portion of the first dielectric layer 140. The third conductive via 154 covers the inner wall of the third via 142. The first conductive via 156 fills the first blind via 146 and connects the first wiring layer 120 and the second wiring layer 150. The second capacitor electrode 158 fills the first opening 144. The second conductive vias 128 and the third conductive vias 154 define a coaxial via 20 . The first capacitor electrode 122, the capacitor dielectric layer 130 and the second capacitor electrode 158 define a capacitor 30. That is to say, the circuit board structure 100 of the present embodiment can effectively utilize the space in the second through hole 118 to fabricate the coaxial through hole 20 suitable for high frequency communication, which can have better design flexibility. In addition, the circuit board structure 100 of the embodiment has three structural components of three different characteristics, such as a three-dimensional inductor 10, a coaxial through hole 20, and a capacitor 30, which can be diversified and have a thin overall thickness.

In addition, the circuit board structure 100 of the present embodiment further includes a second dielectric layer 160 and a third circuit layer 170. The second dielectric layer 160 is disposed on the second circuit layer 150 , covers the second circuit layer 150 and fills the third conductive via 154 . The second dielectric layer 160 has a plurality of second blind vias 162, and the second blind vias 162 expose a portion of the second trace layer 150. The third circuit layer 170 is disposed on the portion of the second dielectric layer 160 and fills the second via hole 162 , wherein the third circuit layer 170 is electrically connected to the second circuit layer 150 .

In addition, the circuit board structure 100 of the present embodiment further includes a solder resist layer 180 disposed on the second dielectric layer 160, covering the second dielectric layer 160, and exposing a portion of the third circuit layer 170, and defining a pad. P, for electrically connecting with an external circuit (not shown). Referring to FIG. 1J again, in order to increase the structural reliability of the circuit board structure 100, the circuit board structure 100 of the present embodiment further includes seed layers S1 and S2, wherein the seed layer S1 is disposed on the second circuit layer 150 and the first dielectric layer. The adhesion between the second wiring layer 150 is increased between the 140 layers, and the seed layer S2 is disposed between the third wiring layer 170 and the second dielectric layer 160 to increase the adhesion of the third wiring layer 170.

In short, the circuit board structure 100 of the present embodiment has three structural components of three different characteristics, such as a three-dimensional inductor 10, a coaxial through hole 20, and a capacitor 30, which can be diversified and have a thin overall thickness. When the circuit board structure 100 is used as a loading board, it can have a thin package thickness, which can meet the requirements of thinning and lightening of the package structure. In addition, the circuit board structure 100 can also be regarded as an interposer, and can be electrically connected to an external circuit (not shown).

In summary, in the design of the circuit board structure of the present invention, the second conductive via covers the inner wall of the second via, and the third via penetrates the first dielectric layer and is located in the second conductive via. And the third conductive via covers the inner wall of the third via, wherein the second conductive via defines a coaxial via with the third conductive via. That is to say, the circuit board structure of the present invention can effectively utilize the space in the second through hole to make a coaxial through hole suitable for high frequency communication, and can have better design flexibility. Furthermore, the line of the present invention The road board structure has three structural components of three different characteristics: three-dimensional inductance, coaxial through hole and capacitor, which can be diversified and the overall thickness is thin. Further, in the method of fabricating the wiring board structure of the present invention, the coaxial via hole and the capacitor are simultaneously defined when the second wiring layer is formed. That is to say, in the same process step, the coaxial via hole and the capacitor are completed at the same time, which can effectively reduce the process time and the production cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

Claims (10)

A circuit board structure comprising: an insulating substrate having a first surface and a second surface opposite to each other; and a plurality of first through holes and a second through hole connecting the first surface and the second surface; a first circuit layer disposed on the insulating substrate and exposing a portion of the first surface and the second surface, the first circuit layer including a first capacitor electrode, an inductor line, and a plurality of first conductive vias And a second conductive via, the first capacitor is located on the first surface, the inductor is located on the first surface and the second surface, and the first conductive vias cover the first vias An inner wall, the second conductive via covers an inner wall of the second through hole, wherein the inductor line and the first conductive vias extend through the insulating substrate in a spiral form to define a three-dimensional inductor; a layer disposed on a portion of the first capacitor electrode; a first dielectric layer covering the first circuit layer and the first surface and the second surface of the insulating substrate exposed by the first circuit layer And filling the first conductive vias and the second An electric via, the first dielectric layer has a third via, a first via, and a first opening, the third via extending through the first dielectric layer and located in the second conductive via The first opening exposes the capacitor dielectric layer, and the first blind hole exposes a portion of the first circuit layer; and a second circuit layer is disposed on the first dielectric layer and includes a second a second conductive via, a first conductive via, and a second capacitor, the second trace being disposed on a portion of the first dielectric layer, the third conductive via covering the third via An inner wall, the first conductive blind hole fills the first blind hole and connects the first circuit layer with The second circuit layer fills the first opening, wherein the second conductive via defines a coaxial via and the third conductive via, the first capacitor electrode and the capacitor dielectric layer A capacitance is defined with the second capacitor electrode. The circuit board structure of claim 1, further comprising: a second dielectric layer disposed on the second circuit layer, covering the second circuit layer and filling the third conductive via, The second dielectric layer has a plurality of second blind holes, and the second blind holes expose a portion of the second circuit layer; and a third circuit layer is disposed on a portion of the second dielectric layer and fills the And a second blind via, wherein the third circuit layer is electrically connected to the second circuit layer. The circuit board structure of claim 2, further comprising: a solder resist layer disposed on the second dielectric layer, covering the second dielectric layer, and exposing a portion of the third circuit layer, And define at least one pad. The circuit board structure of claim 2, further comprising: a sub-layer disposed between the third circuit layer and the second dielectric layer. The circuit board structure of claim 1, further comprising: a sub-layer disposed between the second circuit layer and the first dielectric layer. A method of fabricating a circuit board structure includes: providing an insulating substrate having a first surface and a second surface opposite to each other and a plurality of first passes connecting the first surface and the second surface And a second via hole; forming a first circuit layer on the insulating substrate, the first circuit layer exposing a portion of the first surface and the second surface, and comprising a first capacitor electrode and an inductor line a first conductive via and a second conductive via, the first capacitor is located on the first surface, the inductor is located on the first surface and the second surface, and the first conductive The hole covers the inner wall of the first through hole, and the second conductive through hole covers the inner wall of the second through hole, wherein the inductor line and the first conductive through holes are defined in a spiral form through the insulating substrate Forming a three-dimensional inductor; forming a capacitor dielectric layer on a portion of the first capacitor electrode; pressing a first dielectric layer on the first circuit layer, the first dielectric layer covering the first circuit layer and The first surface and the second surface of the insulating substrate exposed by the first circuit layer fill the first through holes and the second through holes; form a third through hole, a first a blind via and a first opening in the first dielectric layer, wherein the third via extends through the first dielectric layer and is located in the second conductive via, and the first opening exposes the capacitive dielectric a layer, and the first blind via exposes a portion of the first wiring layer; and forms a second wiring layer On the first dielectric layer, the second circuit layer covers a portion of the first dielectric layer and an inner wall of the third via hole and fills the first blind via and the first opening, and the second circuit layer includes a second line, a third conductive via, a first conductive via and a second capacitor, the second line is disposed on a portion of the first dielectric layer, and the third conductive via covers the third An inner wall of the through hole, the first conductive blind hole fills the first blind hole and connects the first circuit layer and the second circuit layer, and the second capacitor electrode fills the first opening, wherein the second conductive The via hole and the third conductive via define a coaxial via, and the first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode define a capacitor. The method for fabricating a circuit board structure according to claim 6, further comprising: forming a second dielectric layer on the second circuit layer, the second dielectric layer covering the second circuit layer and filling a third via hole; forming a plurality of second blind vias on the second dielectric layer, wherein the second blind vias expose a portion of the second wiring layer; and forming a third wiring layer in the portion of the second And filling the second blind vias on the dielectric layer, wherein the third circuit layer is electrically connected to the second circuit layer. The method for fabricating a circuit board structure according to claim 7, further comprising: forming a solder resist layer on the second dielectric layer, the solder resist layer covering the second dielectric layer, and exposing the The third circuit layer defines at least one pad. The method for fabricating a circuit board structure according to claim 7, further comprising: forming a sub-layer between the third circuit layer and the second dielectric layer. The method for fabricating a circuit board structure according to claim 6, further comprising: forming a sub-layer between the second circuit layer and the first dielectric layer.