TWI501706B - Circuit board and manufacturing method thereof - Google Patents

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board including a fine circuit and having high reliability and a method of fabricating the same.

In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products constantly innovating and designing towards light, thin, short and small trends. A circuit board having conductive lines is usually disposed in these electronic products.

In order to increase the wiring density in the wiring board, the circuit layer in the wiring board is generally made to have a line width of 40 μm or more by a substrative process. However, for a line width of 40 μm or less (generally referred to as a thin line), the use of a subtractive process to fabricate a wiring layer results in a decrease in product yield. In the process of the reduction process, if the thickness of the conductive layer forming the wiring layer is too thick, the etching time is too long, so that the etching liquid may stagnate into a pool shape between the line patterns to affect the etching ability. In addition, in the etching process, if the thickness of the conductive layer is too thick, a long etching time is often required, so that the etching liquid will have a serious side etching effect on the sidewall of the wiring pattern, thereby affecting the quality and reliability of the circuit, and is disadvantageous. In the production of fine lines.

In order to fabricate a wiring layer having a line width of 40 μm or less, an ultra-thin copper foil having a low roughness is often used as a conductive layer to avoid corrosion The engraving time is too long and affects the quality and reliability of the line.

However, the ultra-thin copper foil having a low roughness causes the adhesion between the wiring layer and the dielectric layer to be lowered, resulting in the outermost wiring layer being easily peeled off from the dielectric layer, thereby reducing the reliability of the wiring board.

The present invention provides a method of fabricating a circuit board for fabricating a circuit board including fine wiring and having high reliability.

The present invention further provides a wiring board that includes fine wiring and has high reliability.

The invention provides a method for fabricating a circuit board, which is to press a first pre-layer and a first conductive layer on a dielectric core layer, wherein a surface of the first conductive layer facing the dielectric core layer The roughness is less than or equal to 1.5 μm. Then, a first via hole is formed in the first conductive layer, the first pre-adhesive layer and the dielectric core layer. Next, the first conductive layer is patterned to form a first wiring layer. Then, the first dielectric layer, the second pre-adhesive layer and the second conductive layer are pressed onto the first circuit layer, wherein the surface of the second conductive layer facing the first dielectric layer has a roughness greater than 1.5 μm and less than 3 μm. . Then, a second via hole is formed in the second conductive layer, the second pre-adhesive layer and the first dielectric layer. Thereafter, the second conductive layer is patterned to form a second wiring layer.

According to the method of fabricating a circuit board according to the embodiment of the invention, the center line average roughness and the ten point average roughness of the surface of the first conductive layer facing the dielectric core layer are, for example, less than or equal to 1.5 μm.

A method for manufacturing a circuit board according to an embodiment of the present invention, the above The center line average roughness and the ten point average roughness of the surface of the second conductive layer facing the first dielectric layer are, for example, greater than 1.5 μm and less than 3 μm.

According to the manufacturing method of the circuit board according to the embodiment of the present invention, after the forming the first circuit layer and before pressing the first dielectric layer, the second pre-adhesive layer and the second conductive layer, the first circuit may be At least one wiring structure is formed on the layer.

According to the method for fabricating a circuit board according to the embodiment of the invention, the method for forming the circuit structure and the method is, for example, first laminating the second dielectric layer, the third pre-adhesive layer and the third conductive layer on the first circuit layer. Wherein the roughness of the surface of the third conductive layer facing the second dielectric layer is less than or equal to 1.5 μm. Then, a third via hole is formed in the third conductive layer, the third pre-gel layer, and the second dielectric layer. Thereafter, the third conductive layer is patterned to form a third wiring layer.

According to the method of fabricating a circuit board according to the embodiment of the invention, the center line average roughness and the ten point average roughness of the surface of the third conductive layer facing the second dielectric layer are, for example, less than or equal to 1.5 μm.

The invention further provides a circuit board comprising a dielectric core layer, a first circuit layer, a first pre-adhesive layer, a first via hole, a first dielectric layer, a second circuit layer, a second pre-adhesive layer and a first Two vias. The first pre-adhesive layer is disposed on the dielectric core layer. The first circuit layer is disposed on the first pre-glue layer. The first wiring layer includes a first conductive layer, wherein a roughness of a surface of the first conductive layer facing the dielectric core layer is less than or equal to 1.5 μm. The first via hole is disposed in the dielectric core layer and the first pre-adhesive layer, and is electrically connected to the first circuit layer. The first dielectric layer is disposed on the dielectric core layer and covers the first circuit layer. The second pre-adhesive layer is disposed on the first dielectric layer. The second circuit layer is disposed in the second On the pre-adhesive layer. The second wiring layer includes a second conductive layer, wherein a roughness of a surface of the second conductive layer facing the first dielectric layer is greater than 1.5 μm and less than 3 μm. The second via is disposed in the first dielectric layer and the second pre-bond layer, and electrically connects the first circuit layer and the second circuit layer.

According to the circuit board of the embodiment of the invention, the center line average roughness and the ten point average roughness of the surface of the first conductive layer facing the dielectric core layer are, for example, less than or equal to 1.5 μm.

According to the circuit board of the embodiment of the invention, the center line average roughness and the ten point average roughness of the surface of the second conductive layer facing the first dielectric layer are, for example, greater than 1.5 μm and less than 3 μm.

The circuit board according to the embodiment of the invention further includes at least one line structure disposed between the first circuit layer and the first dielectric layer.

According to the circuit board of the embodiment of the invention, the circuit structure includes a second dielectric layer, a third circuit layer, a third pre-adhesive layer, and a third via hole. The second dielectric layer is disposed on the dielectric core layer and covers the first circuit layer. The third pre-adhesive layer is disposed on the second dielectric layer. The third circuit layer is disposed on the third pre-glue layer. The third circuit layer includes a third conductive layer, wherein a surface of the third conductive layer facing the second dielectric layer has a roughness of less than or equal to 1.5 μm. The third via hole is disposed in the third pre-adhesive layer and the second dielectric layer, and electrically connected to the first circuit layer and the third circuit layer, and the second via hole is electrically connected to the second circuit layer and the third circuit layer .

According to the circuit board of the embodiment of the invention, the center line average roughness and the ten point average roughness of the surface of the third conductive layer facing the second dielectric layer are, for example, less than or equal to 1.5 μm.

Based on the above, the present invention forms a pre-adhesive layer between the conductive layer and the dielectric layer for forming the wiring layer, so that the above-mentioned conductive layer can have a lower roughness, and thus can have a thinner thickness, thereby facilitating formation. A wiring layer having a line width of 40 μm or less. Further, in the present invention, the roughness of the conductive layer forming the outermost wiring layer is greater than the roughness of the conductive layer forming the inner wiring layer, so that the outermost wiring layer can withstand a large pulling force, thereby improving the wiring board Reliability.

The above described features and advantages of the present invention will be more apparent from the following description.

1A-1D are cross-sectional views showing a manufacturing process of a circuit board according to an embodiment of the invention. In the present embodiment, a wiring board having a wiring layer on both opposite sides of the core layer will be described, but the present invention is not limited thereto. First, referring to FIG. 1A, a dielectric core layer 100 is provided. The dielectric core layer 100 has a first surface 100a and a second surface 100b that are opposite to each other. Then, the pre-adhesive layer 102a and the conductive layer 104a are pressed on the first surface 100a, and the pre-adhesive layer 102b and the conductive layer 104b are pressed on the second surface 100b. The material of the pre-adhesive layers 102a and 102b is, for example, a B-stage resin which is semi-cured before press-bonding and is cured after being subjected to thermocompression bonding. Therefore, after the press-bonding, the pre-adhesive layer 102a can firmly press the conductive layer 104a against the first surface 100a, and the pre-adhesive layer 102b can firmly press the conductive layer 104b against the second surface 100b. In this way, the conductive layers 104a, 104b having a lower roughness can be used. In addition, due to The electrical layers 104a, 104b have a lower roughness, and the thickness thereof can be reduced accordingly, so that the etching time can be reduced in the subsequent fabrication of the wiring layer by the subtractive process, and over-etching can be avoided. Therefore, the quality and reliability of the formed wiring layer can be improved, and it is advantageous to produce a fine wiring having a line width of 40 μm or less.

Therefore, in the present embodiment, the roughness of the surface of the conductive layers 104a, 104b facing the dielectric core layer 100 is less than or equal to 1.5 μm. Further, the center line average roughness (Ra) and the ten point average roughness (Rz) of the surfaces of the conductive layers 104a, 104b facing the dielectric core layer 100 are, for example, less than or equal to 1.5 μm. For the definition and measurement method of the above roughness, reference may be made to the contents of Japanese Industrial Standard JIS B 0601. The conductive layers 104a, 104b are, for example, copper foil layers

Then, referring to FIG. 1B, via holes 106 are formed in the conductive layer 104a, the pre-adhesion layer 102a, the dielectric core layer 100, and the pre-adhesive layer 102b. The via hole 106 is formed by, for example, performing a laser drilling process to form a blind via which exposes a portion of the conductive layer 104b in the conductive layer 104a, the pre-adhesive layer 102a, the dielectric core layer 100, and the pre-adhesive layer 102b. Then, a conductive material is filled in the blind via by electroplating. In addition, during the electroplating process, the conductive layer 108a is formed on the conductive layer 104a, and the conductive layer 108b is formed on the conductive layer 104b. Thereafter, a patterning process is performed to remove portions of the conductive layers 108a, 104a to form the wiring layer 110a, and to remove portions of the conductive layers 108b, 104b to form the wiring layer 110b. The circuit layer 110a and the wiring layer 110b are electrically connected by the via holes 106. The above step of removing a portion of the conductive layer is generally referred to as a subtractive process.

As described above, in the process of removing portions of the conductive layers 108a, 104a, 108b, 104b, since the conductive layers 104a, 104b have a small thickness, the etching time can be reduced, and thus it is advantageous to fabricate a line having a thickness of 40 μm or less. A wide thin line, that is, circuit layers 110a, 110b.

Next, referring to FIG. 1C, the dielectric layer 112a, the pre-adhesion layer 114a and the conductive layer 116a are laminated on the circuit layer 110a, and the dielectric layer 112b, the pre-adhesion layer 114b and the conductive layer 116b are laminated on the wiring layer 110b. The material of the pre-adhesive layers 114a, 114b may be the same as the material of the pre-adhesive layers 102a, 102b for firmly bonding the conductive layers 116a, 116b to the dielectric layers 112a, 112b, respectively. Similarly, by the pre-adhesive layers 102a, 102b, the conductive layers 116a, 116b can have a lower roughness and a smaller thickness, thereby reducing the etching time in the subsequent fabrication of the circuit layer by the subtractive process, and avoiding over-etching. The situation occurs, and thus it is advantageous to fabricate a thin line having a line width of 40 μm or less.

In addition, in this embodiment, the conductive layers 116a, 116b are used to form the outermost circuit layer of the circuit board. In order to prevent the outermost circuit layer from being detached from the dielectric layers 112a, 112b, the roughness of the conductive layers 116a, 116b is higher. Preferably, it is greater than the roughness of the conductive layers 104a, 104b. In the present embodiment, the surface of the conductive layers 116a, 116b facing the dielectric layers 112a, 112b has a roughness greater than 1.5 [mu]m and less than 3 [mu]m. Further, the center line average roughness and the ten point average roughness of the surfaces of the conductive layers 116a, 116b facing the dielectric layers 112a, 112b are, for example, greater than 1.5 μm and less than 3 μm. In this way, the circuit layer formed by the conductive layers 116a, 116b can withstand a large pulling force, thereby improving the reliability of the circuit board. The tensile force that the conductive layers 116a, 116b can withstand is, for example, greater than 1 kgf/cm ² .

Thereafter, referring to FIG. 1D, a via hole 118a is formed in the conductive layer 116a, the pre-adhesion layer 114a and the dielectric layer 112a, and a via hole 118b is formed in the conductive layer 116b, the pre-adhesion layer 114b, and the dielectric layer 112b. The method of forming the via holes 118a and 118b is the same as that of the via hole 106, and will not be described here. Further, in the process of forming the via holes 118a, 118b, the conductive layers 120a, 120b are also formed on the conductive layers 116a, 116b, respectively. Then, a patterning process is performed to remove portions of the conductive layers 120a, 116a to form the wiring layer 122a, and to remove portions of the conductive layers 120b, 116b to form the wiring layer 122b. The circuit layer 122a and the circuit layer 110a are electrically connected by the via hole 118a, and the circuit layer 122b and the circuit layer 110b are electrically connected by the via hole 118b. As a result, the wiring board 10 having four wiring layers is formed.

In the circuit board 10, since the pre-adhesive layer 102a is disposed between the circuit layer 110a and the dielectric core layer 100, the pre-adhesive layer 102a has a high bonding force and is in the circuit layer 110a and the dielectric core layer 100. In the case where a certain degree of bonding force is maintained, the conductive layer 104a constituting the wiring layer 110a may have a lower roughness (roughness is less than or equal to 1.5 μm), and thus the thickness of the conductive layer 104a may be reduced to facilitate fabrication. The wiring layer 110a has a line width of 40 μm or less. Therefore, the circuit layer 110a can have better quality and reliability. Similarly, since the pre-adhesive layer 102b is disposed between the circuit layer 110b and the dielectric core layer 100, a pre-adhesion layer 114a is disposed between the circuit layer 122a and the dielectric layer 112a, and a wiring layer 122b is disposed between the dielectric layer 112b and the dielectric layer 112b. There is a pre-adhesive layer 114b, and thus the conductive layer 104b constituting the wiring layer 110b, the conductive layer 116a constituting the wiring layer 122a, and the conductive layer 116b constituting the wiring layer 122b may have a lower roughness and a smaller thickness. The degree, and thus the formed wiring layer having a line width of 40 μm or less, can have better quality and reliability.

Further, in the wiring board 10, in order to prevent the outermost wiring layers 122a, 122b from being separated from the dielectric layers 112a, 112b, respectively, the roughness of the conductive layers 116a, 116b is larger than the roughness of the conductive layers 104a, 104b, so that the wiring layer The 122a, 122b can withstand a large pulling force (e.g., greater than 1 kgf/cm ² ), and thereby the reliability of the wiring board 10 is improved.

In the present embodiment, the wiring board 10 is a wiring board having four wiring layers, but the present invention is not limited thereto. In other embodiments, a circuit board having more layers of wiring layers can also be formed in a similar manner.

2A-2B are cross-sectional views showing a manufacturing process of a circuit board according to another embodiment of the present invention. First, referring to FIG. 2A, after the step described in FIG. 1B, the dielectric layer 124a, the pre-adhesive layer 126a and the conductive layer 128a are pressed onto the circuit layer 110a by using steps similar to those of FIGS. 1C to 1D, and The dielectric layer 124b, the pre-adhesion layer 126b and the conductive layer 128b are pressed onto the wiring layer 110b. The conductive layers 128a, 128b are, for example, identical to the conductive layers 104a, 104b, and have a roughness of a surface facing the dielectric layers 124a, 124b of less than or equal to 1.5 [mu]m. Then, a via hole 130a is formed in the conductive layer 128a, the pre-adhesive layer 126a and the dielectric layer 124a, and a conductive layer 132a is formed on the conductive layer 128a, and is formed in the conductive layer 128b, the pre-adhesive layer 126b and the dielectric layer 124b. The via hole 130b and the conductive layer 132b are simultaneously formed on the conductive layer 128b. Next, a patterning process is performed to form wiring layers 134a, 134b.

Of course, depending on actual needs, the steps described in FIG. 2A can be continued to form more layers of inner layer wiring layers.

Thereafter, referring to FIG. 2B, the same steps as in FIGS. 1C to 1D are performed. To obtain a circuit board 20 having six wiring layers.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20‧‧‧ circuit board

100‧‧‧ dielectric core layer

100a‧‧‧ first surface

100b‧‧‧ second surface

102a, 102b, 114a, 114b, 126a, 126b‧‧‧ pre-adhesive layer

104a, 104b, 108a, 108b, 116a, 116b, 120a, 120b, 128a, 128b, 132a, 132b‧‧‧ conductive layer

106‧‧‧through holes

110a, 110b, 122a, 122b, 134a, 134b‧‧‧ circuit layer

112a, 112b, 124a, 124b‧‧‧ dielectric layer

118a, 118b, 130a, 130b‧‧‧ vias

1A-1D are cross-sectional views showing a manufacturing process of a circuit board according to an embodiment of the invention.

2A-2B are cross-sectional views showing a manufacturing process of a circuit board according to another embodiment of the present invention.

10‧‧‧ circuit board

100‧‧‧ dielectric core layer

102a, 102b, 114a, 114b‧‧‧ pre-adhesive layer

104a, 104b, 108a, 108b, 116a, 116b, 120a, 120b‧‧‧ conductive layer

106‧‧‧through holes

110a, 110b, 122a, 122b‧‧‧ circuit layer

112a, 112b‧‧‧ dielectric layer

118a, 118b‧‧‧ vias

Claims (12)

A method of fabricating a circuit board, comprising: pressing a first pre-adhesive layer (102a, 102b) and a first conductive layer (104a, 104b) on a dielectric core layer (100), wherein the first conductive layer The roughness of the surface of the dielectric core layer (100) of (104a, 104b) is less than or equal to 1.5 μm; at the first conductive layer (104a, 104b), the first pre-gel layer (102a, 102b) and Forming a first via hole (106) in the dielectric core layer (100); patterning the first conductive layer (104a, 104b) to form a first circuit layer (110a, 110b); a dielectric layer (112a, 112b), a second pre-adhesive layer (114a, 114b) and a second conductive layer (116a, 116b) on the first circuit layer (110a, 110b), wherein the second conductive layer The roughness of the surface of the layer (116a, 116b) facing the first dielectric layer (112a, 112b) is greater than the roughness of the surface of the first conductive layer (104a, 104b) facing the dielectric core layer (100) and is less than 3μm; forming a second via hole (118a, 118b) in the second conductive layer (116a, 116b), the second pre-adhesive layer (114a, 114b) and the first dielectric layer (112a, 112b); And the second conductive layer (116a, 116b) patterned to form a second wiring layer (122a, 122b). The method for fabricating a circuit board according to claim 1, wherein the first conductive layer (104a, 104b) has a center line average roughness of the surface facing the dielectric core layer (100) and an average roughness of ten points. Small Or equal to 1.5 μm. The method for fabricating a circuit board according to claim 1, wherein a center line average roughness of the surface of the second conductive layer (116a, 116b) facing the first dielectric layer (112a, 112b) is ten The point average roughness is greater than 1.5 μm and less than 3 μm. The method of fabricating a circuit board according to claim 1, wherein after forming the first circuit layer (110a, 110b) and pressing the first dielectric layer (112a, 112b), the second pre- The glue layer (114a, 114b) and the second conductive layer (116a, 116b) further comprise at least one line structure formed on the first circuit layer (110a, 110b). The method for fabricating a circuit board according to claim 4, wherein the method for forming the circuit structure comprises: forming a second dielectric layer (124a, 124b) and a third pre-gel layer (126a, 126b). And a third conductive layer (128a, 128b) is pressed onto the first circuit layer (110a, 110b), wherein the third conductive layer (128a, 128b) faces the second dielectric layer (124a, 124b) The roughness of the surface is less than or equal to 1.5 μm; forming a first layer in the third conductive layer (128a, 128b), the third pre-bond layer (126a, 126b) and the second dielectric layer (124a, 124b) Three via holes (130a, 130b); and the third conductive layer (128a, 128b) are patterned to form a third wiring layer (134a, 134b). The method for fabricating a circuit board according to claim 5, wherein the third conductive layer (128a, 128b) faces the second dielectric The center line average roughness and the ten point average roughness of the surface of the layers (124a, 124b) are less than or equal to 1.5 μm. A circuit board comprising: a dielectric core layer (100); a first pre-adhesive layer (102a, 102b) disposed on the dielectric core layer (100); a first circuit layer (110a, 110b), Disposed on the first pre-adhesive layer (102a, 102b), the first circuit layer (110a, 110b) includes a first conductive layer (104a, 104b), wherein the first conductive layer (104a, 104b) faces The surface of the dielectric core layer (100) has a roughness of less than or equal to 1.5 μm; a first via hole (106) is disposed on the dielectric core layer (100) and the first pre-adhesive layer (102a, 102b) And electrically connected to the first circuit layer (110a, 110b); a first dielectric layer (112a, 112b) disposed on the dielectric core layer (100) and covering the first circuit layer ( 110a, 110b); a second pre-adhesive layer (114a, 114b) disposed on the first dielectric layer (112a, 112b); a second circuit layer (122a, 122b) disposed in the second pre-glue On the layer (114a, 114b), the second circuit layer (122a, 122b) includes a second conductive layer (116a, 116b), wherein the second conductive layer (116a, 116b) faces the first dielectric layer ( The surface roughness of 112a, 112b) is greater than the first The roughness of the faces of the dielectric core layer (100) of the surface of the dielectric layer (104a, 104b) to less than 3 m; and a second via hole (118a, 118b), disposed on the first dielectric layer (112a, 112b) and the second pre-adhesive layer (114a, 114b), and electrically connected to the first circuit layer (110a, 110b) and the second circuit layer (122a, 122b). The circuit board of claim 7, wherein a center line average roughness and a ten point average roughness of the surface of the first conductive layer (104a, 104b) facing the dielectric core layer (100) is less than or Equal to 1.5 μm. The circuit board of claim 7, wherein a center line average roughness of the surface of the second conductive layer (116a, 116b) facing the first dielectric layer (112a, 112b) is ten-point average roughness. The degree is greater than 1.5 μm and less than 3 μm. The circuit board of claim 7, further comprising at least one line structure disposed between the first circuit layer (110a, 110b) and the first dielectric layer (112a, 112b). The circuit board of claim 10, wherein the circuit structure comprises: a second dielectric layer (124a, 124b) disposed on the dielectric core layer (100) and covering the first circuit layer (110a, 110b); a third pre-adhesive layer (126a, 126b) disposed on the second dielectric layer (124a, 124b); a third circuit layer (134a, 134b) disposed in the third pre- On the glue layer (126a, 126b), the third circuit layer (134a, 134b) includes a third conductive layer (128a, 128b), wherein the third conductive layer (128a, 128b) faces the second dielectric layer The roughness of the surface of (124a, 124b) is less than or equal to 1.5 μm; a third via hole (130a, 130b) disposed in the third pre-adhesive layer (126a, 126b) and the second dielectric layer (124a, 124b), and electrically connected to the first circuit layer (110a, 110b) and the third circuit layer (134a, 134b), and the second via holes (118a, 118b) are electrically connected to the second circuit layer (122a, 122b) and the third circuit layer (134a, 134b). The circuit board according to claim 11, wherein a center line average roughness of the surface of the third conductive layer (128a, 128b) facing the second dielectric layer (124a, 124b) is ten-point average roughness. The degree is less than or equal to 1.5 μm.