CN113286439A

CN113286439A - Method for manufacturing electroplated circuit board with built-in lead

Info

Publication number: CN113286439A
Application number: CN202110828230.7A
Authority: CN
Inventors: 康孝恒; 蔡克林
Original assignee: Shenzhen Zhijin Electronics Co ltd
Current assignee: Shenzhen Zhijin Electronics Co ltd
Priority date: 2021-07-22
Filing date: 2021-07-22
Publication date: 2021-08-20

Abstract

The invention provides a method for manufacturing an electroplating circuit board with a built-in lead, which relates to the circuit board technology and is characterized in that a connection point is manufactured on the outer side of a first conductor layer; sequentially superposing a substrate layer and a second conductor layer on the outer side of the first conductor layer, and connecting the first conductor layer and the second conductor layer through a connecting point according to requirements to form a circuit; the technical scheme of removing the carrier and the first conductor layer to obtain two circuit boards is achieved, and the cost is low while the space is saved.

Description

Method for manufacturing electroplated circuit board with built-in lead

Technical Field

The invention relates to a circuit board technology, in particular to a method for manufacturing an electroplated circuit board with a built-in lead.

Background

Along with the gradual progress of chip technology into the post-Mole's law era, the chip technology is smaller, thinner, denser and more integrated, and becomes the struggle direction of the integrated circuit manufacturers.

In order to meet the higher requirements of chips, circuit boards are also faced with more intensive challenges, and the current main ideas are to continuously shrink the sizes and the distances between circuits/pads and fingers, and to avoid the problem of space waste caused by designing leads by adopting a non-lead electrogilding manner such as nickel-palladium-gold, however, the cost of the non-lead electrogilding manner is higher, and further application of the non-lead electrogilding manner is limited.

Disclosure of Invention

The embodiment of the invention provides a method for manufacturing a plated circuit board with a built-in lead, which saves space and has lower cost.

The embodiment of the invention provides a method for manufacturing a built-in lead electroplating circuit board, which comprises the following steps:

manufacturing connection points on the outer side of the carrier;

sequentially superposing a substrate layer and a second conductor layer on the outer side of the first conductor layer, and connecting the first conductor layer and the second conductor layer through a connecting point according to requirements to form a circuit;

removing the carrier to obtain two circuit boards;

wherein the carrier is a separable material.

Optionally, in one possible implementation, the carrier includes an inner fiberglass layer and an outer first conductor layer.

Optionally, in a possible implementation manner, the fabricating the connection point outside the first conductor layer includes:

applying a resistance plating layer on the outer side of the first conductor layer;

and windowing the resistance plating layer according to requirements, and plating a conductor material at the windowing position to form the connecting point.

Optionally, in a possible implementation manner, after the fabricating the connection point outside the first conductor layer, the method further includes:

and removing the plating resisting layer by adopting an alkaline material.

Optionally, in a possible implementation manner, the connecting the first conductor layer and the second conductor layer through the connection point according to a requirement to form a circuit includes:

blind holes are formed in the positions, corresponding to the connection points, of the substrate layer and the second conductor layer;

and filling conductor materials in the blind holes to connect the adjacent first conductor layer and the second conductor layer to form a circuit.

Optionally, in a possible implementation manner, after the forming the line, the method further includes:

and selectively windowing the second conductor layer according to requirements, and etching and removing the unnecessary conductor.

Optionally, in a possible implementation manner, the method further includes:

removing the area corresponding to the conductor on the substrate layer, and selectively coating an insulating layer according to requirements;

the insulating layer is an ink layer.

plating an inert protective metal layer on the outer side of the second conductor layer;

the inert protective metal layer is one of a nickel silver layer, a nickel gold layer, a nickel silver gold layer or an electric tin layer.

Optionally, in a possible implementation manner, after removing the carrier, the method further includes:

and adopting OSP protection at the side of the connection point far away from the second conductor layer.

Optionally, in a possible implementation manner, before the removing the carrier, the method further includes:

and repeatedly executing the steps of sequentially superposing the substrate layer and the second conductor layer on the outer side of the first conductor layer, connecting the first conductor layer and the second conductor layer through the connecting point according to requirements, forming a circuit, and obtaining the multilayer substrate layer.

The technical effects are as follows:

the invention adopts a separable material as a carrier material, thereby improving the manufacturing efficiency by 100%; meanwhile, a mode of internally arranging a lead is adopted, so that only bonding pads required by a chip and a packaging link are reserved on the circuit on the outermost layer, the space is greatly saved, and a novel structure, thought and method are provided for realizing a circuit board with low cost, high efficiency and high integration.

Drawings

FIG. 1 is a schematic diagram of a structure for embodying a carrier in accordance with an embodiment of the present invention;

FIG. 2 is a schematic structural view of a barrier coating embodying the present invention;

FIG. 3 is a schematic diagram of a structure for embodying a connection point according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram for embodying a substrate layer according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a blind via according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another embodiment of the present invention for embodying a blind via;

FIG. 7 is a schematic structural diagram of a second conductive layer according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an embodiment of the present invention for embodying an insulating layer;

FIG. 9 is a schematic structural diagram of an embodiment of the present invention for embodying an inert protective metal layer;

FIG. 10 is a schematic structural diagram of a circuit board for embodying the invention after separation;

FIG. 11 is a schematic structural diagram illustrating the removal of a first conductive layer according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram for embodying OSP protection according to an embodiment of the present invention.

In the figure, 1, vector; 2. a first conductor layer; 3. a connection point; 4. a second conductor layer; 5. a substrate layer; 6. a plating resist layer; 7. blind holes; 8. an insulating layer; 9. the inert protective metal layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.

It should be understood that, in various embodiments of the present invention, the sequence numbers of the processes do not mean the execution sequence, and the execution sequence of the processes should be determined by the functions and the internal logic of the processes, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Examples

A method for manufacturing a built-in lead electroplating circuit board comprises steps S101 to S103, and specifically comprises the following steps:

s101, see fig. 1, 2 and 3, the connection points 3 are made on the outside of the carrier 1.

Wherein the carrier 1 is a separable material, in some embodiments, the carrier 1 comprises an inner fiberglass layer and an outer first conductor layer 2.

Specifically, the first conductor layer 2 may be vacuum-applied on both sides of the glass fiber layer, the first conductor layer 2 may be made of a copper material, and in practical application, the thickness of the first conductor layer 2 may be 1 to 10 μm, for example, 1 μm, or 5 μm, or 10 μm. Specifically, a resistance plating layer 6 is applied on the outer side of the first conductor layer 2, then a window is formed on the resistance plating layer 6 according to requirements, and a conductor material is plated at the window position to form the connection point 3.

It will be appreciated that the plating resist layer 6 is made of a plating resist material, for example an insulating material such as ink, which covers the outside of the first conductor layer 2 to assist in making the connection points 3.

When the connection point 3 is manufactured, a window needs to be formed on the plating-resistant layer 6, and then a conductor material is plated at the window-opening position to form the connection point 3, wherein the conductor material can be a copper material or other conductor materials. It will be appreciated that after the window is opened, a recess is formed in the barrier coating 6, and the connection point 3 is formed by filling the recess with a conductive material. The connection point 3 is connected to the outside of the first conductor layer 2, and can conduct electricity.

The thickness of the conductor material may be 10 to 100 μm, for example, 10 μm, 50 μm, or 100 μm.

In some embodiments, after the fabricating the connection point 3 outside the first conductor layer 2, the method further includes removing the plating resist layer 6 with an alkaline material to perform a subsequent step to prevent the influence of the plating resist layer 6.

S102, referring to fig. 4, sequentially overlapping the substrate layer 5 and the second conductor layer 4 outside the first conductor layer 2, and connecting the first conductor layer 2 and the second conductor layer 4 through the connection point 3 as required to form a circuit.

Specifically, the substrate layer 5 may be formed by laminating a PP material outside the first conductor layer 2 and then performing high temperature vacuum lamination and curing, and meanwhile, the second conductor layer 4 may also be laminated onto the substrate layer 5 by high temperature vacuum lamination and bonded to the substrate layer 5.

And after the lamination is finished, starting to form a circuit:

referring to fig. 5, blind holes 7 are formed in positions of the substrate layer 5 and the second conductor layer 4 corresponding to the connection points 3, and a conductor material is filled in the blind holes 7 to connect the adjacent first conductor layer 2 and the second conductor layer 4, so as to form a circuit.

Referring to fig. 6, wherein the blind via 7 can be drilled by a laser device at a designated position, referring to the drawing, the blind via 7 penetrates through the substrate layer 5 and the second conductor layer 4 at the same time, and then the blind via 7 can be filled with a conductor material, which can be a copper material, to connect the first conductor layer 2 and the second conductor layer 4 to form a circuit.

Referring to fig. 7, in practical applications, the second conductor layer 4 is located on the surface of the substrate layer 5, and not all of the second conductor layer 4 may be used, and the second conductor layer 4 is selectively windowed according to the design drawing to remove the unwanted conductor by etching.

It can be understood that the step S103 of sequentially stacking the substrate layer 5 and the second conductor layer 4 outside the first conductor layer 2 and connecting the first conductor layer 2 and the second conductor layer 4 through the connection point 3 as required to form a circuit is repeatedly performed to obtain the multilayer substrate layer 5.

For example, 2 substrate layers 5 stacked on each other, or 3 and more substrate layers 5 stacked on each other may be formed.

S103, referring to fig. 10 and 11, removing the carrier 1 to obtain two circuit boards;

it can be understood that, by separating the carrier 1, which is a separable material, and separating the first conductor layer 2, two identical circuit boards can be obtained, and the manufacturing efficiency of the circuit board is improved by 100%.

In practical applications, after removing the carrier 1, the OSP protection is further adopted on the side of the connection point 3 far away from the second conductor layer 4.

Referring to fig. 8 and 9, in the above embodiment, it is necessary to perform a solder mask process on the substrate layer 5, and selectively coat a layer of insulating material on the surface of the substrate layer 5 to form an insulating layer 8, which is usually ink.

In other embodiments, referring to fig. 12, after the forming of the circuit, an inert protective metal layer 9 is further plated on the outer side of the second conductor layer 4, where the inert protective metal layer 9 is one of a nickel-silver layer, a nickel-gold layer, a nickel-silver-gold layer, or an electrical tin layer.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing an electroplating circuit board with a built-in lead is characterized by comprising the following steps:

manufacturing a connection point (3) on the outer side of the carrier (1);

a substrate layer (5) and a second conductor layer (4) are sequentially superposed on the outer side of the first conductor layer (2), and the first conductor layer (2) and the second conductor layer (4) are connected through a connecting point (3) according to requirements to form a circuit;

removing the carrier (1) to obtain two circuit boards;

wherein the carrier (1) is a separable material.

2. A method according to claim 1, characterized in that the carrier (1) comprises an inner fiberglass layer and an outer first conductor layer (2).

3. Method according to claim 2, characterized in that the making of the connection points (3) outside the first conductor layer (2) comprises:

applying a plating resist (6) on the outer side of the first conductor layer (2);

and windowing the anti-plating layer (6) according to requirements, and plating conductor materials at the windowing position to form the connecting point (3).

4. A method according to claim 3, characterized in that after said making of the connection points (3) outside the first conductor layer (2), it further comprises:

and removing the plating resist layer (6) by using an alkaline material.

5. Method according to claim 1, characterized in that said connecting a first conductor layer (2) and a second conductor layer (4) by means of connection points (3) on demand, forming a line, comprises:

blind holes (7) are formed in the positions, corresponding to the connecting points (3), of the substrate layer (5) and the second conductor layer (4);

and filling conductor materials in the blind holes (7) to connect the adjacent first conductor layer (2) and the second conductor layer (4) to form a circuit.

6. The method of claim 1 or 5, further comprising, after said forming a line:

selectively windowing the second conductor layer (4) according to requirements, and etching away the unwanted conductor.

7. The method of claim 6, further comprising:

removing the corresponding area of the conductor on the substrate layer (5), and selectively coating an insulating layer (8) according to requirements;

the insulating layer (8) is an ink layer.

8. The method of claim 1, further comprising, after said forming a line:

plating an inert protective metal layer (9) on the outer side of the second conductor layer (4);

the inert protective metal layer (9) is one of a nickel-silver layer, a nickel-gold layer, a nickel-silver-gold layer or an electric tin layer.

9. The method according to claim 1, further comprising, after removing the carrier (1):

and OSP protection is adopted on the side of the connecting point (3) far away from the second conductor layer (4).

10. The method according to claim 1, further comprising, prior to said removing said carrier (1):

and repeatedly executing the steps of sequentially superposing the substrate layer (5) and the second conductor layer (4) on the outer side of the first conductor layer (2), connecting the first conductor layer (2) and the second conductor layer (4) through the connecting point (3) according to requirements, forming a circuit, and obtaining the multilayer substrate layer (5).