TWI606763B - Circuit board and manufacturing method for same - Google Patents

Description

Circuit board and manufacturing method thereof

The invention relates to a circuit board and a manufacturing method thereof.

Due to the significant increase in wafer design complexity, thin circuitization of circuit board products carrying wafers has become a trend. At present, when designing the circuit board circuit distribution, the wiring density on the same plane is large, the operation space on the circuit board is limited, and the technical difficulty in production is large, and it is difficult to control. It is often the case that the wiring density is reduced by increasing the number of board layers, which increases the thickness of the board.

In view of this, in the embodiment of the present invention, a circuit board having a small wiring density and a small thickness and a manufacturing method thereof are provided.

A method of manufacturing a circuit board, comprising the steps of: providing a carrier substrate and a first copper foil layer formed on the carrier substrate; forming a plurality of metal conductive bumps on the first copper foil layer; conducting the metal conductive Forming a first insulating layer on the bump, forming a second copper foil layer on the first insulating layer to form a second multi-layer substrate; removing the carrier substrate to form a first substrate; and first forming the first substrate The copper foil layers are all etched away, and the plurality of metal conductive bumps are etched and thinned to space the plurality of metal conductive bumps by the first insulating layer to form an inner layer conductive trace, and the second copper foil is simultaneously a second insulating layer is formed on the inner conductive line, and the second insulating layer covers the surface of the first insulating layer, and a third copper foil layer is formed on the second insulating layer; And forming the second copper foil layer The first conductive circuit layer forms the third copper foil layer to form a second conductive circuit layer, thereby forming a circuit board.

a circuit board comprising a first insulating layer, an inner conductive line, a second insulating layer, a first conductive circuit layer and a second conductive circuit layer, wherein the inner conductive line is covered in the first insulating layer, The second insulating layer covers the first insulating layer and the inner conductive circuit layer, and the first conductive circuit layer is formed on a surface of the first insulating layer away from the second insulating layer, the second conductive line A layer is formed on the second insulating layer.

Compared with the prior art, in the embodiment of the present invention, the second copper foil layer is thinned by a half etching method, and an inner layer conductive line is formed in the first insulating layer, and then a second insulating layer is formed on the inner layer conductive line. A first conductive circuit layer and a second conductive circuit layer are also formed on both sides of the insulating layer, so that a circuit is formed inside the insulating layer, and a blind hole is formed to make both the first conductive circuit layer and the second conductive circuit layer and the inner layer The conductive lines are electrically connected, that is, the wiring density is reduced without thickening the circuit board or increasing the number of circuit boards.

10‧‧‧ boards

101‧‧‧First multilayer substrate

110‧‧‧Loading substrate

111‧‧‧bearing core

112‧‧‧First layer

113‧‧‧ release film

120‧‧‧First copper foil layer

130‧‧‧Second copper foil layer

131‧‧‧Metal conductive bumps

132‧‧‧First dry film

140‧‧‧First insulation

141‧‧‧ Groove

150‧‧‧Second copper foil layer

160‧‧‧Second insulation

102‧‧‧Second multilayer substrate

200‧‧‧First substrate

201‧‧‧second substrate

2100‧‧‧Second dry film

220‧‧‧Inner conductive lines

230‧‧‧ Third copper foil layer

2300‧‧‧ third dry film

211‧‧‧ first blind hole

231‧‧‧ second blind hole

212‧‧‧First conductive blind hole

232‧‧‧Second conductive blind hole

240‧‧‧First conductive circuit layer

241‧‧‧First conductive bump

260‧‧‧Second conductive circuit layer

261‧‧‧Second conductive bump

270‧‧‧First solder mask

280‧‧‧Second solder mask

290‧‧‧ conductive paste

1 is a schematic cross-sectional view of a first multilayer substrate provided in the embodiment.

Figure 2 is a schematic cross-sectional view showing the formation of a first dry film layer in Figure 1.

Figure 3 is a schematic cross-sectional view showing the formation of a second copper foil layer in Figure 1.

4 is a schematic cross-sectional view showing the formation of a first insulating layer and a second copper foil layer on the second copper foil layer of FIG.

Figure 5 is a cross-sectional view showing the edge of the multilayer substrate of Figure 4 cut.

6 is a schematic cross-sectional view showing the carrier substrate removed in FIG. 5 and forming a first substrate.

Figure 7 is a schematic cross-sectional view showing the formation of a third copper foil layer and an inner layer conductive line.

Figure 8 is a schematic cross-sectional view showing the formation of a second insulating layer and a fifth copper foil layer on the inner layer conductive line of Figure 7.

Figure 9 is a schematic cross-sectional view showing the first blind hole and the second blind hole formed in Figure 8.

Figure 10 is a schematic cross-sectional view showing the formation of the second dry film and the third dry film in Figure 9.

11 is a schematic cross-sectional view showing the first conductive via and the second conductive via in FIG.

Figure 12 is a schematic cross-sectional view showing the formation of a first conductive wiring layer and a second conductive wiring layer.

Figure 13 is a schematic cross-sectional view showing the formation of a first solder resist layer, a second solder resist layer, and a conductive paste in Figure 12 .

The present creative embodiment will be further described in detail below with reference to the accompanying drawings.

Embodiments of the present invention provide a method for fabricating a circuit board 10, including the steps of:

In a first step, referring to FIG. 1, a first multi-layer substrate 101 is provided. The first multi-layer substrate 101 includes a carrier substrate 110 and a first copper foil layer 120 formed on opposite sides of the carrier substrate 110.

The carrier substrate 110 includes a carrier core layer 111, a first adhesive layer 112 formed on opposite sides of the carrier core layer 111, and a release film 113 formed on the first adhesive layer 112 away from the side of the carrier core layer 111. The first adhesive layer 112 completely covers the release film 113, and the first adhesive layer 112 does not cover the portion of the release film 113 and is bonded to the first copper foil layer 120.

In the second step, referring to FIG. 2-3, a plurality of metal conductive bumps 131 are formed on each of the first copper foil layers 120.

In this embodiment, the method for fabricating the metal conductive bumps 131 includes the steps of: forming a patterned first dry film layer 132 on the first copper foil layer 120 as shown in FIG. 2; Forming a plurality of metal conductive bumps 131 on the first copper foil layer 120 exposed from the patterned first dry film layer 132; removing the first dry film layer 132.

In a third step, referring to FIG. 4, a first insulating layer 140 covering the first metal bump 131 is formed on the first copper foil layer 120, and the first insulating layer 140 is away from the first A second copper foil layer 150 is formed on one side of a copper foil layer 120, thereby forming a second multilayer substrate 102.

In the fourth step, referring to FIG. 5-6, the carrier substrate 110 is removed to obtain two first substrates 200.

Since only the edge portion of the first adhesive layer 112 is bonded to the first copper foil layer 120, the second multilayer substrate 102 is cut along the edge of the release film 113 to remove the first The portion of the adhesive layer 112 bonded to the first copper foil layer 120 can separate the first copper foil layer 120 on both sides of the carrier substrate 110 from the release film 113, thereby obtaining two A substrate 200. Each of the first substrates 200 includes a first insulating layer 140, a first copper foil layer 120 and a second copper foil layer 150 formed on both sides of the first insulating layer 140, and a surface formed on the surface of the first copper foil layer 120. A plurality of metal conductive bumps 131.

In the fifth step, referring to FIG. 7, the first copper foil layer 120 and the second copper foil layer 150 of the first substrate 200 are half-etched.

In this embodiment, by controlling the concentration of the etching solution and the etching time, the entire etching of the first copper foil layer 120 is removed, the second copper foil layer 150 is etched and thinned, and the plurality of metal conductive bumps 131 are removed. The etching is thinned so that a plurality of grooves 141 are formed on the first insulating layer 140 at positions corresponding to the plurality of metal conductive bumps 131 that are etched away. The plurality of metal conductive bumps 131 that are thinned are directly spaced apart by the insulating layer to form the inner layer conductive traces 220.

In a sixth step, referring to FIG. 8, a second insulating layer 160 is formed on the inner conductive line 220, and then a third copper foil layer 230 is formed on the second insulating layer 160 to obtain a second substrate 201.

In this embodiment, the second insulating layer 160 is formed on the surface of the first insulating layer 140 away from the second copper foil layer 150 and fills the recess 141, and the third copper foil layer 230 is formed on the second insulating layer 140. The second insulating layer 160 is away from the surface of the first insulating layer 140.

In order to make the circuit board thinner, in other embodiments, the second insulating layer 160 may also be formed only in the recess 141. At this time, the third copper foil layer 230 is simultaneously formed on the first layer. Absolutely The edge layer 140 is away from the surface of the second copper foil layer 150 and the second insulating layer 160 is away from the surface of the second copper foil layer 150.

In a seventh step, referring to FIG. 9, a plurality of blind holes are formed on the second substrate 201.

Specifically, at least one first blind via 211 is formed from the second copper foil layer 150 toward the inner conductive trace 220, and the first blind via 211 sequentially penetrates the second copper foil layer 150 and the first insulation. Layer 140 exposes a portion of the inner conductive trace 220. Forming at least one second blind hole 231 from the third copper foil layer 230 toward the inner conductive line 220, the second blind hole 231 sequentially penetrating the third copper foil layer 230 and the second insulating layer 160, A portion of the inner conductive trace 220 is exposed.

The eighth step, referring to FIGS. 10~12, the blind via is formed to form a conductive blind via; a first conductive trace layer 240 is formed on the first insulating layer 140, and a second conductive layer 160 is formed on the second insulating layer 160. Two conductive circuit layers 260.

In this embodiment, the first conductive wiring layer 240 and the second conductive wiring layer 260 are formed by a method of exposure, development, electroplating, stripping, etching, etc., specifically: first, referring to FIG. 10, in the second copper A second dry film layer 2100 is formed on the foil layer 150, and the pattern of the second copper foil layer 150 exposed from the patterned second dry film layer 2100 is the same as the pattern in which the first conductive wiring layer 240 is to be formed, The third copper foil layer 230 forms a patterned third dry film layer 2300, the pattern of the third copper foil layer 230 exposed from the patterned third dry film layer 2300 and the second conductive wiring layer 260 to be formed. The pattern is the same; secondly, referring to FIG. 11 , electroplating, forming a first conductive blind via 212 at a position around the first blind via 211 and the first blind via 211 and a plurality of protruding from the second copper foil layer 150 a first conductive bump 241, a second conductive blind via 232 and a plurality of second conductive protrusions protruding from the third copper foil layer 230 at positions around the second blind via 231 and the second blind via 231 a bump 261; thereafter, removing the second dry film layer 2100 and the third dry film layer 2300; then, Referring to FIG. 12, the first conductive bump 241 and the second conductive bump 261 are respectively covered with a patterned fourth dry film layer (not shown), and the pattern of the fourth dry film layer and the corresponding The patterns of the conductive bumps are the same, and the second copper foil layer 150 and the third copper foil layer 230 not covered with the fourth dry film layer are removed by etching to form the first conductive wiring layer 240 and the second conductive line. Layer 260.

In a ninth step, referring to FIG. 13, a first solder resist layer 270 and a second solder resist layer 280 are formed on the first conductive wiring layer 240 and the second conductive wiring layer 260, respectively, and the first solder resist layer 270 And the second solder resist layer 280 are each formed with at least one solder mask opening, the first conductive trace layer 240 and the second conductive trace layer 260 being exposed from the solder resist opening; and then exposed to the solder resist layer A conductive paste 290 is formed on the first conductive wiring layer 240 and the second conductive wiring layer 260, and the conductive paste 290 is used to solder a part (not shown) to form the circuit board 10.

Referring to FIG. 13 , a circuit board 10 is further provided in the embodiment of the present invention. The circuit board 10 includes a first insulating layer 140 , an inner conductive line 220 , a second insulating layer 160 , a first conductive circuit layer 240 , and a second The conductive circuit layer 260, the first solder resist layer 270, the second solder resist layer 280, and the conductive paste 290. The inner conductive layer 220 is covered in the first insulating layer 140, the second insulating layer 160 covers the first insulating layer 140 and the inner conductive line 220, and the second conductive circuit layer 260 Formed on the second insulating layer 160, the first conductive circuit layer 240 is formed on a surface of the first insulating layer 140 away from the second insulating layer 160, and the first solder resist layer 270 is formed on the first a conductive circuit layer 240, the second solder resist layer 280 is formed on the second conductive circuit layer 260, the first solder resist layer 270 and the second solder resist layer 280 further include at least one solder mask opening, The first conductive wiring layer 240 and the second conductive wiring layer 260 are exposed from the solder resist layer opening, and the conductive paste 290 is formed on the first conductive wiring layer 240 and the second conductive trace exposed to the solder resist layer. On layer 260. The circuit board 10 further includes a first conductive blind via 212 and a second conductive via 232. The first conductive via 212 penetrates the second copper foil layer 150 and the first insulating layer 140, and is electrically connected. The first conductive circuit layer 240 and the inner conductive circuit 220 are disposed, and the second conductive blind via 232 extends through the third copper foil layer 230 and the second insulating layer 160, and is electrically connected to the second conductive circuit layer 260. And inner conductive line 220.

Compared with the prior art, in the embodiment, the second copper foil layer 130 is thinned by a half etching method, while the inner layer conductive line 220 is formed in the first insulating layer 140, and then the second layer is formed on the inner layer conductive line 220. The insulating layer 160 also forms a first conductive circuit layer 240 and a second conductive circuit layer 260 on both sides of the insulating layer, so that a circuit is formed inside the insulating layer, and a blind hole is formed to make the first conductive circuit layer. Both the 240 and the second conductive circuit layer 260 are electrically connected to the inner conductive line 220, that is, the wiring density is reduced without thickening the circuit board or increasing the number of circuit boards.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10‧‧‧ boards

140‧‧‧First insulation

160‧‧‧Second insulation

220‧‧‧Inner conductive lines

240‧‧‧First conductive circuit layer

260‧‧‧Second conductive circuit layer

270‧‧‧First solder mask

280‧‧‧Second solder mask

290‧‧‧ conductive paste

Claims (9)

A method of manufacturing a circuit board, comprising the steps of: providing a carrier substrate and a first copper foil layer formed on the carrier substrate; forming a plurality of metal conductive bumps on the first copper foil layer; conducting the metal conductive Forming a first insulating layer on the bump, forming a second copper foil layer on the first insulating layer to form a second multi-layer substrate; removing the carrier substrate to form a first substrate; and first forming the first substrate The copper foil layers are all etched away, and the plurality of metal conductive bumps are etched and thinned to space the plurality of metal conductive bumps by the first insulating layer to form an inner layer conductive trace, and the second copper foil is simultaneously a second insulating layer is formed on the inner conductive line, and the second insulating layer covers the surface of the first insulating layer, and a third copper foil layer is formed on the second insulating layer; And forming the second copper foil layer to form a first conductive circuit layer, and forming the third copper foil layer to form a second conductive circuit layer, thereby forming a circuit board. The method of manufacturing a circuit board according to claim 1, wherein the carrier substrate comprises a carrier core layer, a first adhesive layer formed on opposite sides of the carrier core layer, and is formed on the first adhesive layer away from the carrier core layer. Release film on one side. The method of fabricating a circuit board according to claim 1, wherein the method for fabricating the metal conductive bump comprises the steps of: forming a patterned first dry film layer on the first copper foil layer; A plurality of metal conductive bumps are plated on the exposed first copper foil layer in the dry film layer; and the first dry film layer is removed. The circuit board manufacturing method according to claim 1, wherein in the step of forming the inner layer conductive line, a plurality of grooves are formed on the first insulating layer at positions corresponding to the plurality of metal conductive bumps removed by etching. . The method of fabricating a circuit board according to claim 4, wherein the second insulating layer is formed on a surface of the first insulating layer away from the second copper foil layer and fills the recess. The method of fabricating a circuit board according to claim 1, wherein a plurality of first blind vias are formed in the second copper foil layer before the first and second conductive wiring layers are formed, the first blind via exposed portions The inner conductive line; the first blind via is plated to form a first conductive blind via, such that the first conductive trace layer is electrically connected to the inner conductive trace. The method of fabricating a circuit board according to claim 1, wherein a plurality of second blind holes are formed in the third copper foil layer before the first and second conductive circuit layers are formed, and the second blind holes are exposed The inner conductive line; the second blind via is plated to form a second conductive blind via, such that the second conductive trace layer is electrically connected to the inner conductive trace. The method of fabricating a circuit board according to claim 1, wherein the first conductive wiring layer and the second conductive wiring layer are formed by a method of exposure development, comprising the steps of: forming a second dry film on the second copper foil layer a layer, the pattern of the second copper foil layer exposed from the patterned second dry film layer is the same as the pattern of the first conductive wiring layer to be formed, and the patterned third dry film is formed on the third copper foil layer a layer, the pattern of the third copper foil layer exposed from the patterned third dry film layer is the same as the pattern of the second conductive wiring layer to be formed; electroplating, in the periphery of the first blind via and the first blind via a position of forming a first conductive blind hole and a plurality of first conductive bumps protruding from the second copper foil layer, and forming a second conductive blind hole at a position around the second blind hole and the second blind hole And a plurality of second conductive bumps protruding from the third copper foil layer; and covering the first conductive bumps and the second conductive bumps with the patterned fourth dry film layer, and removing by etching The second copper foil layer and the third copper foil layer not covered by the fourth dry film layer, Thereby, the first conductive wiring layer and the second conductive wiring layer are formed. The method of fabricating a circuit board according to claim 1, further comprising forming a first solder resist layer on the first conductive wiring layer and forming a second solder resist layer on the second conductive wiring layer.