JPH0427573B2 - - Google Patents

Info

Publication number
JPH0427573B2
JPH0427573B2 JP57222203A JP22220382A JPH0427573B2 JP H0427573 B2 JPH0427573 B2 JP H0427573B2 JP 57222203 A JP57222203 A JP 57222203A JP 22220382 A JP22220382 A JP 22220382A JP H0427573 B2 JPH0427573 B2 JP H0427573B2
Authority
JP
Japan
Prior art keywords
address
instruction
conditional branch
branch instruction
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57222203A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58125148A (ja
Inventor
Jan Rosuku Jatsuku
Seshajiri Rao Gururaji
Edowaado Satsuchaa Hawaado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS58125148A publication Critical patent/JPS58125148A/ja
Publication of JPH0427573B2 publication Critical patent/JPH0427573B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP57222203A 1982-01-15 1982-12-20 条件付きブランチ命令の予測装置 Granted JPS58125148A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/339,561 US4477872A (en) 1982-01-15 1982-01-15 Decode history table for conditional branch instructions
US339561 1982-01-15

Publications (2)

Publication Number Publication Date
JPS58125148A JPS58125148A (ja) 1983-07-26
JPH0427573B2 true JPH0427573B2 (cg-RX-API-DMAC7.html) 1992-05-12

Family

ID=23329604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57222203A Granted JPS58125148A (ja) 1982-01-15 1982-12-20 条件付きブランチ命令の予測装置

Country Status (5)

Country Link
US (1) US4477872A (cg-RX-API-DMAC7.html)
EP (1) EP0084114B1 (cg-RX-API-DMAC7.html)
JP (1) JPS58125148A (cg-RX-API-DMAC7.html)
DE (1) DE3271063D1 (cg-RX-API-DMAC7.html)
ES (1) ES518983A0 (cg-RX-API-DMAC7.html)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5742099A (en) * 1980-08-27 1982-03-09 Sharp Kk Voice informing device
US4604691A (en) * 1982-09-07 1986-08-05 Nippon Electric Co., Ltd. Data processing system having branch instruction prefetching performance
DE3382350D1 (de) * 1982-11-17 1991-08-29 Nec Corp Anordnung zum vorabholen von befehlen mit vorhersage einer verzweigungszieladresse.
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
US4764861A (en) * 1984-02-08 1988-08-16 Nec Corporation Instruction fpefetching device with prediction of a branch destination for each branch count instruction
JPS60168238A (ja) * 1984-02-10 1985-08-31 Hitachi Ltd パイプラインデータ処理装置
US4679141A (en) * 1985-04-29 1987-07-07 International Business Machines Corporation Pageable branch history table
JPS6341932A (ja) * 1985-08-22 1988-02-23 Nec Corp 分岐命令処理装置
DE3785897T2 (de) * 1986-02-28 1993-09-30 Nippon Electric Co Steuervorrichtung zum vorabruf von befehlen.
US4991080A (en) * 1986-03-13 1991-02-05 International Business Machines Corporation Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions
EP0239023B1 (de) 1986-03-21 1990-10-17 Siemens Aktiengesellschaft Anordnung zur Bearbeitung von Sprungbefehlen innach dem Fliessbandprinzip arbeitenden Datenverarbeitungsanlagen
JPH0731615B2 (ja) * 1986-04-18 1995-04-10 日本電気株式会社 情報処理装置
US5440704A (en) * 1986-08-26 1995-08-08 Mitsubishi Denki Kabushiki Kaisha Data processor having branch predicting function
US4722046A (en) * 1986-08-27 1988-01-26 Amdahl Corporation Cache storage priority
JP2603626B2 (ja) * 1987-01-16 1997-04-23 三菱電機株式会社 データ処理装置
US5175827A (en) * 1987-01-22 1992-12-29 Nec Corporation Branch history table write control system to prevent looping branch instructions from writing more than once into a branch history table
US5247627A (en) * 1987-06-05 1993-09-21 Mitsubishi Denki Kabushiki Kaisha Digital signal processor with conditional branch decision unit and storage of conditional branch decision results
US5134561A (en) * 1987-07-20 1992-07-28 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
US4942520A (en) * 1987-07-31 1990-07-17 Prime Computer, Inc. Method and apparatus for indexing, accessing and updating a memory
US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries
US4860199A (en) * 1987-07-31 1989-08-22 Prime Computer, Inc. Hashing indexer for branch cache
US4860197A (en) * 1987-07-31 1989-08-22 Prime Computer, Inc. Branch cache system with instruction boundary determination independent of parcel boundary
US5247628A (en) * 1987-11-30 1993-09-21 International Business Machines Corporation Parallel processor instruction dispatch apparatus with interrupt handler
US4943908A (en) * 1987-12-02 1990-07-24 International Business Machines Corporation Multiple branch analyzer for prefetching cache lines
GB8728493D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Jump prediction
US5522053A (en) * 1988-02-23 1996-05-28 Mitsubishi Denki Kabushiki Kaisha Branch target and next instruction address calculation in a pipeline processor
JPH081602B2 (ja) * 1988-02-23 1996-01-10 三菱電機株式会社 データ処理装置
JPH0769808B2 (ja) * 1988-02-23 1995-07-31 三菱電機株式会社 データ処理装置
JPH081599B2 (ja) * 1988-02-24 1996-01-10 三菱電機株式会社 データ処理装置
US5228131A (en) * 1988-02-24 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Data processor with selectively enabled and disabled branch prediction operation
US5136696A (en) * 1988-06-27 1992-08-04 Prime Computer, Inc. High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions
JP2570859B2 (ja) * 1989-05-25 1997-01-16 日本電気株式会社 データ処理装置
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
EP0404068A3 (en) * 1989-06-20 1991-12-27 Fujitsu Limited Branch instruction executing device
US5210831A (en) * 1989-10-30 1993-05-11 International Business Machines Corporation Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
JPH0460720A (ja) * 1990-06-29 1992-02-26 Hitachi Ltd 条件分岐命令制御方式
DE69130138T2 (de) * 1990-06-29 1999-05-06 Digital Equipment Corp., Maynard, Mass. Sprungvorhersageeinheit für hochleistungsfähigen Prozessor
JPH0820950B2 (ja) * 1990-10-09 1996-03-04 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチ予測型分岐予測機構
US5265199A (en) * 1991-05-22 1993-11-23 Silicon Graphics, Inc. Method and apparatus for accomplishing Z-buffering by prediction
JPH0628184A (ja) * 1991-08-26 1994-02-04 Internatl Business Mach Corp <Ibm> ブランチ予測方法及びブランチプロセッサ
US5333283A (en) * 1991-10-29 1994-07-26 International Business Machines Corporation Case block table for predicting the outcome of blocks of conditional branches having a common operand
US5434986A (en) * 1992-01-09 1995-07-18 Unisys Corporation Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction
AU665368B2 (en) * 1992-02-27 1996-01-04 Samsung Electronics Co., Ltd. CPU having pipelined instruction unit and effective address calculation unit with retained virtual address capability
US5434985A (en) * 1992-08-11 1995-07-18 International Business Machines Corporation Simultaneous prediction of multiple branches for superscalar processing
US5463746A (en) * 1992-10-30 1995-10-31 International Business Machines Corp. Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes
US5367703A (en) * 1993-01-08 1994-11-22 International Business Machines Corporation Method and system for enhanced branch history prediction accuracy in a superscalar processor system
KR100310581B1 (ko) * 1993-05-14 2001-12-17 피터 엔. 데트킨 분기목표버퍼의추측기록메카니즘
US5577217A (en) * 1993-05-14 1996-11-19 Intel Corporation Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions
BR9406606A (pt) * 1993-05-14 1996-01-02 Intel Corp Mecanismo para história especulativa em um buffer objeto de ramificação
TW261676B (cg-RX-API-DMAC7.html) * 1993-11-02 1995-11-01 Motorola Inc
US5634119A (en) * 1995-01-06 1997-05-27 International Business Machines Corporation Computer processing unit employing a separate millicode branch history table
US5905881A (en) * 1995-11-30 1999-05-18 Unisys Corporation Delayed state writes for an instruction processor
US5794024A (en) * 1996-03-25 1998-08-11 International Business Machines Corporation Method and system for dynamically recovering a register-address-table upon occurrence of an interrupt or branch misprediction
US5822577A (en) * 1996-05-01 1998-10-13 International Business Machines Corporation Context oriented branch history table
US5867699A (en) * 1996-07-25 1999-02-02 Unisys Corporation Instruction flow control for an instruction processor
US5875325A (en) * 1996-09-19 1999-02-23 International Business Machines Corporation Processor having reduced branch history table size through global branch history compression and method of branch prediction utilizing compressed global branch history
US6484256B1 (en) * 1999-08-09 2002-11-19 International Business Machines Corporation Apparatus and method of branch prediction utilizing a comparison of a branch history table to an aliasing table
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
EP1236097A4 (en) 1999-09-01 2006-08-02 Intel Corp BRANCH COMMAND TO THE PROCESSOR
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
KR20040045467A (ko) * 2001-10-02 2004-06-01 코닌클리케 필립스 일렉트로닉스 엔.브이. 자바 하드웨어 가속기에 대한 추론적 실행
US7437724B2 (en) 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
GB2506462B (en) * 2013-03-13 2014-08-13 Imagination Tech Ltd Indirect branch prediction
US11194575B2 (en) * 2019-11-07 2021-12-07 International Business Machines Corporation Instruction address based data prediction and prefetching

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS549456B2 (cg-RX-API-DMAC7.html) * 1972-07-05 1979-04-24
US3881173A (en) * 1973-05-14 1975-04-29 Amdahl Corp Condition code determination and data processing
CA1059639A (en) * 1975-03-26 1979-07-31 Garvin W. Patterson Instruction look ahead having prefetch concurrency and pipe line features
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4179738A (en) * 1978-06-23 1979-12-18 International Business Machines Corporation Programmable control latch mechanism for a data processing system
US4370711A (en) * 1980-10-21 1983-01-25 Control Data Corporation Branch predictor using random access memory
US4402042A (en) * 1980-11-24 1983-08-30 Texas Instruments Incorporated Microprocessor system with instruction pre-fetch

Also Published As

Publication number Publication date
DE3271063D1 (en) 1986-06-12
EP0084114A1 (en) 1983-07-27
EP0084114B1 (en) 1986-05-07
ES8403221A1 (es) 1984-03-01
US4477872A (en) 1984-10-16
JPS58125148A (ja) 1983-07-26
ES518983A0 (es) 1984-03-01

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