JPH04252345A - Single chip microcomputer with built-in memory having plural input/output ports - Google Patents

Abstract

PURPOSE:To apply an interruption to an internal CPU with no change of software required by providing an interruption request generating means. CONSTITUTION:An interruption request generating circuit 8 is provided between a dual port memory DPRAM 3 and an internal CPU 4. That is, a single chip microcomputer 2 containing a DPRAM 3 reads the data out of a port 5a of the DPRAM 3 through an internal data bus 6. Then an existing single chip microcomputer 1 performs the write and read of date through a port 5b of the DPRAM 3 via an internal. data bus 7. Under such conditions, the circuit 8 decides a fact that the data are written into the DPRAM 3 and gives an interruption request to the CPU 4.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention provides a single-chip microcomputer that has a built-in memory having multiple input/output ports and a central processing means, when data is written to the memory from an external CPU. The present invention relates to a single-chip microcomputer with a built-in memory and a plurality of input/output ports, such as a built-in interrupt request generation circuit that generates an interrupt request.

0002

[Prior Art] Figure 4 shows a dual port memory (hereinafter referred to as DPRAM) installed in an existing single-chip microcomputer.
1 is a schematic diagram showing a conventional example in which a single-chip microcomputer with a built-in microcomputer is connected. In FIG. 4, a single-chip microcomputer 2 with a built-in DPRAM is connected to an existing single-chip microcomputer 1 via an external data bus 7. DPR
AM built-in single chip microcomputer 2 is DP
It includes a RAM 3 and a built-in CPU 4, and one port 5a of the DPRAM 3 and the CPU 4 are connected by an internal data bus 6. The other port 5b of the DPRAM 3 is connected to the single-chip microcomputer 1 via the data bus 7. Built-in CPU 4 of single-chip microcomputer 2 with built-in DPRAM writes data to and reads data from DPRAM 3 via internal data bus 6 and port 5a.

On the other hand, the existing single-chip microcomputer 1 writes and reads data from the external data bus 7 to the DPRAM 3 via the other port 5b of the DPRAM 3. In this way, a multi-CPU system can be constructed by connecting the single-chip microcomputer 2 with a built-in DPRAM to the existing single-chip microcomputer 1 and sharing the DPRAM 3.

0004

Problem to be Solved by the Invention In the conventional multi-CPU system configured as described above, the internal CPU of the single-chip microcomputer 2 with built-in DPRAM
4, it is necessary to monitor whether the data in the DPRAM 3 has been updated. However, when the data in the DPRAM 3 is rewritten from the single-chip microcomputer 1 via the data bus 7, an interrupt is not given to the internal CPU 4, so the internal CPU 4 cannot determine whether the data in the DPRAM 3 has been updated. Can not.

In order for the single-chip microcomputer 1 to issue an interrupt to the internal CPU 4, it is necessary to connect one free port of the single-chip microcomputer 1 to the external interrupt terminal of the single-chip microcomputer 2 with built-in DPRAM. There is. And the single chip microcomputer 1 is DP
When writing data to the RAM 3, it is necessary to change the software of the single-chip microcomputer 1 so that the output is output to this port.

Therefore, the main object of the present invention is to provide a memory having multiple input/output ports that can interrupt the internal CPU without requiring any changes to the software of an existing single-chip microcomputer. Its purpose is to provide a built-in single-chip microcomputer.

[0007]

[Means for Solving the Problems] The present invention is a single-chip microcomputer that includes a memory having a plurality of input/output ports and an internal central processing means, the external central processing means being connected to one input/output port of the memory. The apparatus includes an interrupt request generating means for generating an interrupt request to the internal central processing means in response to data being written into the memory by the processing means.

[0008]

[Operation] The single-chip microcomputer with built-in memory and having multiple input/output ports according to the present invention requests an interrupt to the internal central processing means in response to data being written to the memory by the external central processing means. By providing the interrupt request generation means for generating the interrupt request, it is possible to issue an interrupt request to the internal central processing means without the need to change the software of the existing single-chip microcomputer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic block diagram showing an embodiment of the present invention. The embodiment shown in FIG. 1 is constructed in the same manner as in FIG. 4 described above except for the following points. That is, an interrupt request generation circuit 8 is provided between the DPRAM 3 and the internal CPU 4. This interrupt request generation circuit 8 is a DPR from an existing single-chip microcomputer 1.
When data is written to AM3, an interrupt request is generated to internal CPU4.

Next, the operation will be explained. DPRAM
Built-in single-chip microcomputer 2 is DPRA
Data is only read from port 5a of M3 via internal data bus 6. Next, the existing single-chip microcomputer 1 writes and reads data from the port 5b of the DPRAM 3 via the external data bus 7. At this time, the interrupt request generation circuit 8
It is determined that data has been written to the internal CPU 4, and an interrupt request is generated to the internal CPU 4.

Note that the single-chip microcomputer 2 with a built-in DPRAM only reads data from the DPRAM 3, but when attempting to write data as well, from the perspective of the existing single-chip microcomputer 1, the data is abnormally replaced. There is a danger that the vehicle may run out of control. For this reason, it is necessary to change the software and hardware of the single-chip microcomputer 1, and the gist of the present invention is to connect the single-chip microcomputer 2 with a built-in DPRAM to the existing single-chip microcomputer 1 to create a multi-CPU system. This is because it becomes impossible to configure.

Furthermore, for the above reasons, the single-chip microcomputer 2 with built-in DPRAM is
Since data will not be written to port 5a,
An interrupt request generation circuit is not required when data is written from . However, when constructing a new multi-CPU system, it may be necessary to interrupt the port 5a, but this can be easily handled by connecting one vacant port to the external interrupt terminal of the other party.

FIG. 2 is a block diagram showing another embodiment of the invention. The embodiment shown in FIG. 2 replaces the DPRAM 3 of the embodiment shown in FIG.
The internal data bus 6 is connected to the port 5a of the multi-port RAM 9, and the external data bus 7 is connected from the port 5b.
a to an external single-chip microcomputer 1a, a port 5c to an external single-chip microcomputer 1b via an external data bus 7b, and a port 5d to an external single-chip microcomputer 1b via an external data bus 7c. It is connected to computer 1c. The interrupt request generation circuit 8 generates an interrupt request signal when data is written into the multi-port RAM 9 from each single-chip microcomputer 1a, 1b, 1c. Therefore, even when a plurality of existing single-chip microcomputers 1a to 1c are connected to the multiport RAM 9, by providing such an interrupt request generation circuit 8, the software in each single-chip microcomputer 1a to 1c can be easily updated. No changes are required.

FIG. 3 is a schematic block diagram showing still another embodiment of the present invention. In the embodiment shown in FIG. 3, two DPRAM-incorporated single-chip microcomputers shown in FIG. Interrupt request generation circuit 8 of one single-chip microcomputer 2a with built-in DPRAM
A generates an interrupt request signal when data is written into the DPRAM 3a from the other DPRAM-equipped single-chip microcomputer 2b. Similarly, the interrupt request generation circuit 8b of the other single-chip microcomputer 2b with built-in DPRAM receives data from the single-chip microcomputer 2a with built-in DPRAM.
Generates an interrupt request signal when written to AM3b.

As described above, even when the single-chip microcomputers 2a and 2b with built-in DPRAM are connected to each other, it is not necessary to create any special software.

In the embodiment shown in FIG. 1, an existing single-chip microcomputer 1 is connected to a single-chip microcomputer 2 with a built-in DPRAM. You may also do so.

[0017]

As described above, according to the present invention, the interrupt request generating means generates an interrupt request to the internal central processing means in response to data being written to the memory from the external central processing means. Since it is built-in, a multi-CPU system can be constructed without the need to change the software of an existing single-chip microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention.

FIG. 2 is a schematic block diagram showing another embodiment of the invention.

FIG. 3 is a schematic block diagram showing still another embodiment of the invention.

FIG. 4 is a schematic block diagram showing a conventional multi-CPU system.

[Explanation of symbols]

1, 1a to 1c Single chip microcomputer 2, 2a, 2b Single chip microcomputer with built-in DPRAM 3, 3a, 3b DPRAM 4, 4a, 4b CPU 5a to 5d Ports 6, 6a, 6b Internal data bus 7, 7a to 7c External Data buses 8, 8a, 8b Interrupt request generation circuit 9 Multiport RAM

Claims (1)

[Claims] 1. A single-chip microcomputer incorporating a memory having a plurality of input/output ports and an internal central processing means, wherein data is written to the memory by an external processing means connected to one input/output port of the memory. A single-chip microcomputer having a built-in memory and having a plurality of input/output ports, the single-chip microcomputer having a plurality of input/output ports and comprising interrupt request generating means for generating an interrupt request to the internal central processing means in response to a request for an interrupt request to the internal central processing means.