JPH04235661A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To shorten the waiting time for the access given to a main memory by using both main memories for instructions and date. CONSTITUTION:The instruction caches 3 and 4 store the instructions, and the data caches 5 and 6 store the data respectively. Two pairs of system buses are provided as an instruction-only system bus 10 and a data-only system bus 11 respectively. Then two pairs of main memories as an instruction store main memory 8-1 and a data store main memory 8-2 respectively. The memory 8-1 is connected to the bus 10, and the memory 8-2 is connected to the bus 11 respectively. As a result, a processor 2 can have an access to the memory 8-2, for example, while the processor 1 has an access to the memory 8-1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system capable of rapidly transferring instructions and data.

0002

2. Description of the Related Art Some multiprocessor systems include each processor equipped with a cache memory in order to perform processing at high speed. FIG. 2 shows such a conventional multiprocessor system. 1 and 2 are processors, 3 and 4 are instruction caches, 5 and 6 are data caches, 7 is auxiliary memory, 8 is main memory, 12 is a system bus, AB is an address bus, DB is a data bus,
CB is a control bus.

Instruction caches 3 and 4 are cache memories for storing instructions, and data caches 5 and 6 are cache memories for storing data. Auxiliary memory 7
is a memory that temporarily stores instructions and data when they are changed as processing progresses. The contents of the auxiliary memory 7 are later copied to the main memory 8. Main memory 8 stores instructions and data.

When processor 1 executes a process, it obtains instructions from instruction cache 3 and data from data cache 5. If it is not stored in them, the system bus 12
The data is retrieved from the main memory 8 via .

[0005]

[Problems to be Solved by the Invention] However, in the conventional multiprocessor system described above, when the main memory 8 is being accessed because there is no required instruction or data in the cache memory, other processors are unable to access the main memory 8 until the access is completed. There was a problem in that the main memory 8 could not be accessed at all and the main memory 8 remained in the waiting state. The present invention aims to solve these problems.

[0006]

[Means for Solving the Problems] In order to solve the above problems, the present invention takes the following measures. That is, in a multiprocessor system that includes a plurality of processors each having an instruction cache and a data cache, two sets of system buses, one for instructions and one for data, are provided, and a main memory for instructions and a system bus for data are provided. It was decided to provide a main memory for instructions connected to a system bus and a main memory for data connected to the system bus for data.

[0007]

[Operation] If there are two types of cache memory attached to each processor, instruction cache and data cache, the system bus and main memory will also be dedicated to each type. This makes it possible to shorten the waiting time when accessing the main memory.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a multiprocessor system according to a first embodiment of the present invention. The symbols correspond to those in FIG. 2, 8-1 is the main memory for instructions, 8-1 is the main memory for instructions;
-2 is a main memory for data, 9 is a bus selector, 10 is a system bus for instructions, and 11 is a system bus for data. In this embodiment, two sets of system buses are provided, one dedicated to instructions (10) and the other dedicated to data (11). Two sets of main memories are also provided, one for storing instructions (8-1) and the other for storing data (8-2). The instruction main memory 8-1 is connected to the instruction system bus 10, and the data main memory 8-2 is connected to the data system bus 11. The bus selector 9 is used to switch connections between the auxiliary memory 7 and two system buses.

With this configuration, even when a certain processor is accessing the instruction main memory 8-1, other processors can access the data main memory 8-2. The reverse is also possible. For example, when there is no instruction required by the processor 1 in the instruction cache 3, the instruction main memory 8-1 is accessed via the instruction system bus 10. At this time, the data system bus 11 is not used, so if the processor 2 needs to access the data main memory 8-2 at the same time, it can access the data main memory 8-2 simultaneously without waiting for the access to the instruction cache 3 to be completed. The data main memory 8-2 can be accessed at any time. Therefore, the processing can proceed without waiting, and the processing speed becomes faster.

FIG. 3 shows a multiprocessor system according to a second embodiment of the present invention. The symbols correspond to those in FIG. 1, 7-1 is an auxiliary memory for instructions, 7
-2 is an auxiliary memory for data. In the example of FIG.
A bus selector 9 was attached to the auxiliary memory 7, but this bus selector 9 does not perform the complicated control of monitoring the signals flowing to each system bus and deciding which system bus the auxiliary memory 7 should be connected to. I need. Therefore, in order to make this unnecessary, in the second embodiment, two sets of auxiliary memories are provided, one for instructions and one for data.

FIG. 4 shows a multiprocessor system according to a third embodiment of the present invention. The symbols correspond to those in FIG. In this example, there is one set of system buses, but the main memories are divided into two main memories: an instruction main memory 8-1 and a data main memory 8-2, as in the first embodiment.
It is dedicated to Therefore, when accessing the main memory, there is no need for a procedure to distinguish between areas in the main memory where instructions are stored or data is stored, so the processing is faster than in the conventional example shown in Figure 2. speed increases. Further, the contents stored in the auxiliary memory 7 are often data, but if the contents are only data, when the contents are copied to the main data memory 8-2 after the processing of the processor is completed, Since the power to the instruction main memory 8-1 may be turned off, power is saved.

[0013]

As described above, according to the multiprocessor system of the present invention, if there are two types of cache memory attached to each processor, an instruction cache and a data cache, A dedicated system bus and main memory were also provided to accommodate this, reducing the waiting time when accessing the main memory.

[Brief explanation of the drawing]

FIG. 1: A multiprocessor system according to a first embodiment of the present invention.

[Figure 2] Conventional multiprocessor system

FIG. 3: Multiprocessor system according to a second embodiment of the present invention.

FIG. 4 A multiprocessor system according to a third embodiment of the present invention.

[Explanation of symbols]

1, 2 Processor 3, 4 Instruction cache 5, 6
Data cache 7 Auxiliary memory 7-1 Auxiliary memory for instructions 7-2
Auxiliary memory for data 8 Main memory 8-1 Main memory for instructions 8-2 Main memory for data 9 Bus selector 10 System bus for instructions 11
Data system bus 12 System bus AB Address bus DB Data bus CB Control bus

Claims (1)

[Claims] Claim 1: In a multiprocessor system comprising a plurality of processors each having an instruction cache and a data cache, two sets of system buses, an instruction system bus and a data system bus, are provided, and a main memory is used as a main memory. A multiprocessor system comprising: an instruction main memory connected to the instruction system bus; and a data main memory connected to the data system bus.