JPS62173562A - Bus switching system - Google Patents

Abstract

PURPOSE:To avoid a bus waiting state and to improve the throughput of a bus switching system by providing a bus switching means consisting of a timer and a latch to the following stage of a bus selecting means. CONSTITUTION:A bus selector 21 delivers the bus selection signals in response to the 1st and 2nd system buses and an internal bus according to the address signal received from a CPU 11. A bus switching means consisting of a fail-safe timer 31 and an F/F 32 is provided at the following stage of the selector 21. In case one of both system buses is occupied, the access to the occupied bus is discontinued after a fixed time. Then an access is given to the other system bus.

Description

Detailed Description of the Invention Technical Field The present invention relates to a bus switching system, and particularly to a computer system having two system buses, for example, a main bus and a local bus, to improve system throughput by eliminating bus wait states. It is possible to
This relates to a bus switching method.

Prior Art FIG. 6 shows a block diagram of a conventional general multiprocessor system.

In this system, the bus control of the processor (hereinafter referred to as "CPU") and the memory and input/output device control unit (hereinafter referred to as "En/○") was performed using addresses. The above address control is fixedly set in advance, for example, when accessing the memory, addresses A to B use local bus 1 and addresses C to F use main bus 2, and cannot be changed midway. could not.

As mentioned above, in the past, addresses were usually fixed, so if you went to access a certain bus and that bus was being used by another CPU, the bus would be released while the CPU was still accessing it. This causes a problem in that the processing efficiency of the CPU decreases and the performance of the entire system decreases.

Additionally, some systems have a bank selection function, and in this case, it is possible to change the above address, but in this case as well, it is necessary for the CPU to consciously change the address using a program. there were.

Purpose The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional bus switching system, eliminate the bus waiting state, and improve system throughput. The object of the present invention is to provide a bus switching method that enables

Configuration The above object of the present invention is to provide a multiprocessor system having two system buses and bus selection means for selecting one of the system buses, which comprises a timer and a latch at a stage subsequent to the bus selection means. A bus switching means is provided, and when one of the two system buses is occupied, access to the occupied system bus is terminated after a certain period of time, and access is made to the other system bus. This is achieved by a bus switching method characterized by:

Hereinafter, the configuration of the present invention will be explained in more detail based on examples.

FIG. 2 is a configuration diagram showing an example of a multiprocessor system to which the present invention is suitable. In the figure, 11.12 is a CPU, 13 to 15 are Ilo having input/output devices, 16 is a memory, 17 is a first system bus (hereinafter referred to as "bus 1"), and 18 is a second system bus (hereinafter referred to as "bus 1"). , "Bus 2").

FIG. 3 is a block diagram showing details of the CPU II and its surroundings. In FIG. 5, 11 is the CPU, 21 is a bus select, 22, 23 is a bus buffer, and BUSI, BUS2, . IBUS is the bus 1. Bus select signals corresponding to bus 2 and internal buses are shown.

The bus select 21 is configured using ROM or RAM and has the functions described below.

Further, FIG. 1 shows the above-mentioned CPU, which is an embodiment of the present invention.
2 is a diagram showing a detailed configuration around II and bus select 21. FIG. This embodiment is characterized in that a bus select control circuit, which will be described below, is provided between the CPU 11 and the bus select 21.

In FIG. 1, 31 is a fail-safe timer, 32 is a flip-flop (hereinafter referred to as rF/FJ), 33 is an AND gate, and 34 is an OR gate. The F/F 32 is set by turning off the output of the failsafe timer 31, and the 5ELECT signal of the bus select 21 is set by the output of the F/F 32.

Note that FIG. 4 is a functional diagram of the bus select 21, which will be described later.

The failsafe timer 31 turns off the output when the signal supplied from the CPU is interrupted for a certain period of time or more.
Normally, the output of this failsafe timer is supplied to the RDY circuit of the CPU, and the CPU is locked by forcibly terminating the currently executing command and moving to the next program execution. It is used to prevent this.

In this embodiment, a new operation is made possible by utilizing a fail-safe timer having the above-mentioned functions as described later.

The operation of this embodiment will be described below with reference to FIGS. 1 to 4.

In the system shown in FIG. 2, l10(1)13 has a direct memory access (DMA) circuit, and the CP
Consider the case where DMA transfer is performed using bus 1 according to instructions from U(1) or CPU(2). Here, C
It is assumed that the PU (1) or the CPU (2) accesses the memory 16 according to instructions from a program.

Inside the CPU board, as shown in FIG. 3, bus 1 and bus 2 of the system are separated from the inside of the CPU board by path buffer (1) 22 and path buffer (2) 23.

When the power is turned on, the F/F 32 is normally reset, so the bus select 21 is set to 5ELE shown in FIG.
The CT signal is "0".

Therefore, the address range of ADDR-A is set to bus select 2.
1, its output becomes the internal bus selection signal IBUS, as shown in FIG. Also, A
When the DDR-B address range is input, the bus 1 selection signal BUS 1 is output. This signal BUS
1 outputs the address and control signals input to the bus buffer (1) 22 and output from the CPU (1) 11 to the bus 1, as shown in FIG.

Now, when the CPU (1) 11 goes to access the memory 16, the select signal BUSI is output,
Path buffer (1) is activated, but as mentioned above, since l10 (1) 13 is performing DMA transfer using bus 1, CPU (1) cannot use bus 1 and waits. state.

When the CPUU enters the wait state, the signal supplied to the fail-safe timer 31, here the address latch signal (rALEJ), is no longer output from the CPU II, so after a certain period of time, the fail-safe timer 31 Turn off the output.

As mentioned above, the F/F32 is the failsafe timer 3.
1, and the output of this F/F 32 sets the 5ELE (1, T signal) of the bus select 21. Therefore, when the output of the failsafe timer 31 is turned OFF, the signal shown in FIG. Configuration D is established.

As a result, BUS1 is turned OFF, BUS2 is activated, the path buffer (2) 23 is activated, and bus 2 is accessed. It becomes possible to execute the

FIG. 5 shows another embodiment of the present invention, and shows the first embodiment.
The difference from the embodiment shown in the figure is that basically bus 1 is used.

That is, even if an access is made to bus 2, the timer 41 causes the access to return to bus 1 after a certain period of time, and bus 2 is immediately accessed when bus 1 becomes a bus neck. Usually, it is left open so that it can be migrated.

The operation of this embodiment is to set the F/F 32 again and reset the bus select 21 after a certain period of time after accessing the bus 2 by the timer 41. Other operations will be described earlier. This is similar to that of the embodiment described above.

According to this embodiment, when there is a difference in bus speed.

Alternatively, when the connected Ilo's are different, it becomes possible to preferentially use a high-speed bus or to preferentially use a specific bus, which further improves the efficiency of the system.

Effects As described above, according to the present invention, in a multiprocessor system having two system buses and bus selection means for selecting one of the system buses,
A bus switching means consisting of a timer and a latch is provided downstream of the bus selection means, and when one of the two system buses is occupied, the system bus is switched to the occupied system bus after a certain period of time. By aborting access and accessing the other system bus, it is now possible to automatically change bus access, eliminating bus wait states and improving system throughput. This has the remarkable effect of realizing a bus switching system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a multiprocessor system to which the present invention is preferably applied, and FIG. 3 is a block diagram showing peripheral details thereof. , FIG. 4 is a diagram showing the bus select function, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a block diagram of a conventional general multiprocessor system. 11.12: CPU, 13-15: Ilo, 16: Memory, 17: Bus 1.18: Bus 2.21: Bus select, 22, . 23: Pass buffer, 31: Fail-safe tie, MA, 32: F/F, 33: AND gate, 34
．． 42: 0R gate, 41: timer, BUSI, BUS
2. IBUS: Bus select signal. Figure 1 Figure 2 Q

Claims (1)

[Claims] (1) In a multiprocessor system having two system buses and a bus selection means for selecting one of the system buses, at a stage subsequent to the bus selection means,
A bus switching means consisting of a timer and a latch is provided, and when one of the two system buses is occupied, access to the occupied system bus is terminated after a certain period of time, and the access to the other system bus is terminated. A bus switching method characterized by accessing the bus.