JPH0354660A - Shared memory management system for multiprocessor system - Google Patents

Abstract

PURPOSE:To exclusively control the access to a shared memory with a simple circuit by connecting a memory bus to a bus gate circuit corresponding to the processor to which a memory acquisition response is returned. CONSTITUTION:When a CPU 1 turns on a memory request signal a0 because requiring the access to a shared memory 4, a priority control circuit 3 performs the exclusive control based on access requests from plural processors and returns the memory acquisition response to one processor. When the indication to connect a bus 7 to a bus gate circuit 5 or 6 corresponding to this processor to which the memory acquisition response is returned is issued, this bus gate circuit 5 or 6 connects the processor and the memory. Thus, the access request to the shared memory is exclusively controlled without degrading the performance of the whole of the multiprocessor system.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a shared memory management method in a multiprocessor system in which a single storage device is shared by multiple processors. (Prior Art) In order to increase processing power and efficiency in using computer resources, multiprocessor systems have been constructed in which multiple processors share a single storage device (shared memory). In this multi-processor system, exclusive control is performed to control which processor is given access rights to the storage device, and this exclusion method includes the following methods. ■A processor that requests access to shared memory stops all processors that may access this shared memory and prevents access requests from other processors before accessing shared memory. ■A dedicated processor (management processor) is provided to manage shared memory access requests, and a processor attempting to access shared memory issues an access request to this management processor. Then, this management processor performs exclusive control and grants access to only one processor. (Problems to be Solved by the Invention) As mentioned above, the conventional shared memory management method has the following problems to be solved. In conventional method (■), every time one processor accesses shared memory, all other processors are stopped, resulting in a decline in the performance of the entire multiprocessor system. Conventional method ■ also requires a large amount of overhead for communication with the management processor, which reduces the performance of the entire multiprocessor system. The present invention has been made in view of these circumstances, and its purpose is to provide shared memory in a multiprocessor system that performs exclusive control of access requests to shared memory without degrading the performance of the entire processor system. Its purpose is to provide a memory management method. <Measures Pi for Solving the Problems> In order to achieve the above object, the shared memory management method in the multiprocessor system of the present invention allows multiple processors and one storage device shared by the multiple processors to In a shared memory management method in a multiprocessor system that is connected to a bus and grants access to any one processor when there is an access request from the plurality of processors to the storage device, the processor and the memory bus a bus gate circuit that connects or disconnects the processor; and a bus gate circuit that performs exclusive control based on access requests from the plurality of processors, returns a memory acquisition response to any one of the processors, and sends the memory acquisition response to the processor. and a priority control circuit that issues an instruction to connect the memory bus to the bus gate circuit corresponding to the returned processor. (Operation) In the shared memory management method in the multiprocessor system of the present invention, the priority 1 control circuit performs exclusive control based on access requests from multiple processors to acquire memory for any one processor. A response is sent back and an instruction is issued to the bus gate circuit corresponding to the processor that returned this memory acquisition response to connect the memory bus. Then, the bus gate circuit connects the processor and the memory bus. (Example) Next, an example of the present invention will be described in detail with reference to the drawings. Figure 1 is a treetop view of one example of the present invention. In the figure, 1.2 is a processor (referred to as CPU), 3 is a priority control circuit that performs exclusive control, 4 is a shared memory, and 5.6
is a bus gate, and 7 is a memory bus. Next, in the embodiment of FIG. 1, from the CPU to the shared memory 4
The following describes the operation when an access request is made to the shared memory 4.When the CPU needs to access the shared memory 4, it turns on the memory request signal aO. Then, the priority control circuit 3 recognizes that the memory request signal aO is in the ON state and performs the following exclusive control. (2) When the memory request signal a1 from the CPU 2 is not in the ON state In such a case, the priority control circuit 3 outputs the memory acquisition response signal bOt. It turns on and notifies the CPU that access to the shared memory 4 is permitted, and turns the bus gate control signal CO on. The bus gate 5, which receives this ON-state bus gate control m signal, turns on the internal gate. As a result, CPUI and shared memory 4
are connected via a memory bus 7. The CPU that received the memory acquisition response signal bo in the ON state
1 accesses shared memory 4. Then, when the access is completed, the memory request signal aO is turned OFF. Therefore, the next new access request will be accepted. (2) When the memory request signal a1 from the CPU 2 is in the ON state In such a case, the priority control circuit 3 waits for the memory request signal a1 to change from the ON state to the OFF state.
When the memory request signal a1 becomes OFF, the memory acquisition response signal bO and bus gate control signal CO are turned ON, as described above. and CPU1
accesses the shared memory 4 when the memory acquisition response signal turns ON, and turns the memory request signal aO OFF when the access is completed. In this way, exclusive control over shared memory is performed. Similar processing is performed when the CPU 2 accesses the shared memory 4. In this embodiment, the multiprocessor system is configured with two CPUs, but it goes without saying that the number of CPUs may be three or more. (Effects of the Invention) As explained above, according to the shared memory management method in the multiprocessor system of the present invention, exclusive control of access to the shared memory can be realized with a simple circuit, and processing can be performed at high speed. Therefore, the time during which each processor in the multiprocessor can operate independently becomes longer, and the performance of the entire system can be improved.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of an embodiment of the present invention. 1, 2...
CPU, 3... Priority control circuit, 4... Shared memory, 5.6... Bus gate, 7... Memory bus.

Claims (1)

[Claims] A plurality of processors and a storage device shared by the plurality of processors are connected to a memory bus, and when the plurality of processors makes an access request to the storage device, one of the processors receives an access request from the plurality of processors. A shared memory management method in a multiprocessor system in which access is permitted in a multiprocessor system includes: a bus gate circuit that connects or disconnects a processor and the memory bus; and a bus gate circuit that performs exclusive control based on access requests from the plurality of processors. a priority control circuit that returns a memory acquisition response to any one processor and instructs the bus gate circuit corresponding to the processor that has returned the memory acquisition response to connect a memory bus; A shared memory management method in a multiprocessor system characterized by the provision of.