JPH02191057A - Multiplex processor system - Google Patents

Abstract

PURPOSE:To shorten a waiting time for an access to a main memory device by regulating plural central processing units (CPUs) to fix timing, with which the request of the access to the main memory device is executed to a system controller, and limiting the number of the CPUs which can execute simultaneous requests. CONSTITUTION:A timing regulating means A is provided to regulate the plural CPUs 1a-1d so that the timing to execute the request of the access to a main memory device 4 can be fixed to a system controller 3 and a request priority order deciding means B is provided to limit the number of the CPUs 1a-1d which can execute the simultaneous requests. A priority order deciding circuit 5a accepts one request at a maximum and a timing generator 6 generates a requestable signal to regulate the respective CPUs 1a-1d so that the timing to execute the request can be fixed. Thus, the number of the CPUs 1a-1d to be simultaneously requestable is limited and the waiting time for the access to the main storage device 4 can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multiprocessor system, and particularly to a multiprocessor system in which a plurality of central processing units can share a main memory.

[Conventional technology]

Figure 4 shows, for example, Nikkei Electronics 1986゜6.
2,396, p. 195. It is a configuration diagram showing the configuration of a conventional multiprocessor system shown in "Large-sized computer M-780 in which a CPU is mounted on one board."

This configuration diagram is an excerpt of this conventional example, and parts not directly related to the present invention are omitted.

In Figure 4, la and lb are separate central processing units (
Hereinafter, la and lb are CPU1a and CPU1b, respectively.
), 2a, and 2b are CPU1a and CPU1, respectively.
5 is a priority determination circuit that determines the order of requests, 4 is a main storage device shared by the CPU 1a and the CPU 1b, and the system control device 3 is set to the port 2a from each port 2b. , port 2
b, a priority order determination circuit 5;

Next, the operation of this conventional example will be explained using FIG. 4.

In FIG. 4, the CPU 1a or CPU 1b issues a request for access to the main storage device 4 to the system control device 3 at an arbitrary timing. The access request from the CPU 1a sent to the system control device 3 is sent to the port 2a,
An access request from CPU 1b is set to port 2b and stacked. The system control device 3 has a plurality of C
Access requests received from the PU 1a or the CPU 1b are processed in descending order of arrival time and priority of the requests. That is, the order of the requests is determined by the priority determination circuit 5, and either the CPU 1a or the CPU 1b selected by this determination performs a read or write operation to the main storage device 4.

[Problem to be solved by the invention]

As described above, in the conventional example, when there are access requests from multiple central processing units (CPUs) at the same time,
Since a request to access the main storage device 4 is granted based only on the priority order among the plurality of CPUs, a CPU with a lower priority will always have a longer waiting time for accessing the main storage device 4. However, there was a problem in that the efficiency of the entire system was reduced.

Furthermore, since each of the plurality of CPUs generates a request at an arbitrary time, the priority determination circuit 5 must have the ability to process a plurality of requests at the same time.
When the number of devices increases, the priority determination circuit 5 becomes complicated, and there is a problem in that the overhead thereof increases.

This invention was made in order to solve the problems of the conventional example as described above, and it limits the number of CPUs that can request at the same time, shortens the waiting time for accessing the main memory, and The purpose of this invention is to simplify the configuration of a ranking determination circuit, reduce overhead, reduce the amount of hardware, and improve the efficiency of the entire system.

[Means to solve the problem]

Therefore, in the present invention, a plurality of central processing units, a main storage device shared by the central processing units, and a system control device that controls data transfer between the central processing units and the main storage devices are provided. In the multi-processor system, the timing specifying means A specifies that each of the plurality of central processing units issues a request for access to the main storage device to the system control device at a fixed timing; The above object is achieved by providing a request priority determination means B that limits the number of possible central processing units.

[Effect]

The multiprocessor system according to the present invention is provided with a timing regulation means, so that the timing at which each of the plurality of central processing units makes a request to the system control unit for access to the main storage device is fixed, and Since the request priority determining means is provided, the number of central processing units that can make requests at the same time is limited.

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

Fig. 1 is a configuration diagram of a multiprocessor system that is an embodiment of the present invention, Fig. 2 is a timing diagram showing the timing of requests when there are four CPUs in this embodiment, and Fig. 3 is an embodiment of this invention. FIG. 2 is a timing diagram showing the timing of requests when there are six CPUs in the example; in each diagram, the same or equivalent components as in the conventional example are represented by the same symbols;
Some redundant explanations will be omitted. Further, in FIG. 1, A is a timing specifying means, and the timing specifying means A includes a timing generating device 6 and a request signal generation control device 7.
a, 7b, 7c, and 7d, and a plurality of central processing units 1a, lb, and lc.

1d are means for fixing the timing of requesting access to the main storage device 4 from the system control device 3, and B is a means for determining a priority level determination circuit 5a.
This is a request priority determining means that limits the number of central processing units that can make requests at the same time.

Hereinafter, some of the above constituent parts will be explained in duplicate.

la, lb, lc, and id are four central processing units,
CPU1a, CPU1b, CPU1c, CPU respectively
It is called 1d. 2a, 2b, 2c.

2d is a boat, which corresponds to the CPUs 1a to 1d, respectively. Further, the priority determination circuit 5a only needs to be able to accept a maximum of one request, and may have a simpler configuration than the prior art priority determination circuit 5 (FIG. 4). In the above case, only one CPU can make a request at the same time, but if the priority determination circuit 5a can accept a plurality of requests, for example two, the number of CPUs will be doubled. That is, in the above case, the number of CPUs can be eight, and the number of CPUs can be limited. Also, 6
is a timing generator, which generates a request enable signal to fix the timing at which each CPU can make a request. Also 7a, 7b,
7c.

Each of the request signal generation control devices 7d receives a request enable signal from the timing generation device 6 and controls the generation of the request signal. In addition, in FIG. 2, T is the time required for one data transfer including the time for request processing,
(a).

(b), (c), and (d) are each CPU1a.

The timing of each request enable signal of lb, lc, and ld is shown.

Next, the operation of this embodiment will be explained using FIGS. 1 to 3.

First, a case will be described in which there are four central processing units (CPUs) and only one main storage device that can make requests at the same time.

In FIG. 1, when the timing generator 6 generates a request enable signal to fix the timing at which each of the CPUs 1a, lb, lc, and ld can make a request, as described above, As shown in the timing diagram, for one hour between times 0 and 1, the CPU
Only CPU 1a can make requests, and only CPU 1b can make requests for one hour between times 1 and 2. Similarly, at times 2 and 3, only CPU 1 c is used, and at times 3 and 4, CPU 1 c is used only.
Only U1d is possible, and requests can always be made from a maximum of one CPU, which generates a quest enable signal. These request enable signals are transmitted to each of the request signal generation control devices 7a, 7b, 7c, and 7d via request enable signal lines 8, 9, and 10.11, respectively. Each of the request signal generation control devices 7a to 7d transmits a request from one of the CPUs 1a to 1d to the system control device 3 only when the request signal indicates that the request is possible.

As described above, each CPU can send a request to access the main storage device 4 to the system control device 3 only at the timing T when the request enable signal shown in FIG. 2 is set. Then, the request signal is transmitted to the priority determination circuit 5, the priority is determined, and the access request is transmitted from there to the main storage device 4.

This will be explained below using an example.

In FIG. 2, it is assumed that cpUla issues a request signal between time 0 and time 1. First, if the system control device 3 is not busy, the CP is used between time 0 and time 1.
Since no request comes from any of U1b, lc, and ld, the request from CPU1a is immediately accepted and the main storage device 4 can be accessed. This data transfer ends within one hour, so it ends between time 1 and time 2.

In addition, when the system control device 3 is busy for data transfer of the CPU 1d, the data transfer of the CPU 1d is
Since it starts before time 0, it ends by time 1. At the time when the data transfer of CPU1d is completed, CPU1d
Request a is accepted.

Further, the system control device 3 will not be busy for data transfer from the CPU 1b or the CPU 1c between time O and time 1. Therefore, requests from each CPU are always accepted within one hour, and requests from lower priority CPUs are always accepted within one hour.
The waiting time of the PU will not be long.

The above is a case in which there are four CPUs, but in other cases, for example, in a case where there are six CPUs, the same is true as above, and only the generation of timing by the timing generator 6 is changed.

FIG. 3 is a timing diagram showing the timing in the case of six devices. In FIG. 3, CPU1a, lb, lc
, ld, le, and if are times O~1.1~2.2, respectively.
~3, 3~4, 4~5° T corresponding to each of 5~6
- If the request enable signal is generated at the time, the same operation and effect as in the case of the above four units can be obtained. In addition, in the conventional example, only one CPU can make requests at the same time.
As mentioned above, if the priority determination circuit 5 can accept a plurality of requests, for example, two requests at most, the CPU
The configuration of four CPUs can be changed to a configuration of eight CPUs. Similarly, the number of CPUs can be changed.

〔Effect of the invention〕

As explained above, according to the present invention, the timing specifying means for specifying that each of the plurality of central processing units makes a request to the system control device for access to the main storage device and fixes the timing, and simultaneously By using a multiprocessor system equipped with a request priority determining means that limits the number of central processing units that can make requests, the number of CPUs that can make requests at the same time can be limited, and the waiting time for accessing the main memory can be reduced. This has the effect of reducing overhead, reducing the amount of hardware, and improving the efficiency of the entire system by shortening the structure and simplifying the configuration of the priority determination circuit.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a multiprocessor system which is an embodiment of the present invention, and FIG. 2 is a timing diagram showing request timing when there are four CPUs in this embodiment.
FIG. 3 is a timing diagram showing the timing of requests when there are six CPUs in this embodiment, and FIG. 4 is a configuration diagram showing the configuration of a conventional multiprocessor system. ld, le, if 2a, 2b 2c, 2d 3-----System control device 4--Main storage device 5, 5a-Priority determination circuit 6... Timing generation device 8.9.10.11...Request enable signal line A
・・・・・・Timing regulation means

Claims (1)

[Claims] In a multiprocessor system comprising a plurality of central processing units, a main storage device shared by the central processing units, and a system control device that controls data transfer between the central processing units and the main storage device, timing regulation means for prescribing to fix the timing at which each of the plurality of central processing units requests access to the main storage device to the system control unit; and limiting the number of central processing units that can make a request at the same time. A multiprocessor system characterized by comprising: request priority determination means for determining the priority level of a request.