JPS62262159A - Electronic computer - Google Patents

Abstract

PURPOSE:To decrease the frequency of making reference to a main memory, by loading an instruction and a data to a memory used exclusively for an arithmetic processing which requires them at the same time with the loading of the instruction and the data to a main memory from a secondary storage device. CONSTITUTION:Arithmetic processors 1-4, a main memory 13 and a secondary storage control device 15 are connected by a data bus 16 and an address but, and the memory 13 can be referred to by obtaining these buses. Also, in case a data to which the processors 1-4 execute an access does not exist in the memory, the processors 1-4 request a data existing in a secondary storage device 14, to the device 15. The device 15 outputs the requested data and the address to the bus 16 and the bus 17, respectively. From the device 14, the data is transferred by a page unit by which the memory 13 is managed, and a size of page memories 5-8 is set to this page size.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to data transfer between an arithmetic processing unit and a main memory, or between an arithmetic processing unit and a secondary storage device, for the purpose of improving the processing speed of an electronic computer. It relates to transfer, and is particularly effectively used in systems where a plurality of arithmetic processing units exist.

BACKGROUND OF THE INVENTION Data is usually stored in a main memory, and in order to perform one process, a processing unit fetches the data from the main memory. Also, if the data required by the processing unit does not exist in the main memory,
The data held on the secondary storage device is loaded from the secondary storage device to the main memory in physical units called pages, blocks, etc., as needed.

Problems to be Solved by the Invention Arithmetic processing units frequently fetch data stored in main memory, and especially in systems composed of multiple processing units, these arithmetic processing A specific arithmetic processing unit occupies the instruction and data transfer path between the device and the main memory, and during that time, other arithmetic processing units are unable to obtain data. Furthermore, if data required by the arithmetic processing unit does not exist in the main memory, the data held on the secondary storage device is loaded from the secondary storage device to the main memory as necessary.

The present invention has been made in view of this point, and an object of the present invention is to provide a means for reducing the frequency with which an arithmetic processing unit directly fetches data from the main memory.

Means for Solving the Problems In order to achieve the above object, the present invention simultaneously loads instructions and data into the memory dedicated to the arithmetic processing unit that requires them when loading instructions and data from the secondary storage device to the main memory. It is structured like this.

Effects of the present invention The present invention allows each of one or more arithmetic processing units to refer to its own page memory, and directly refers to the main memory only when the desired data does not exist in the page memory. You can reduce the frequency of reference.

Embodiment FIG. 1 shows an embodiment of the present invention in which there are four arithmetic processing units. 1 to 4 are arithmetic processing units that interpret and execute instructions, 5 to 8 are page memories provided corresponding to the arithmetic processing units 1 to 4, respectively, and 9 to 12 are one arithmetic processing unit and This is a processing block configured around one page memory. 14 is a secondary storage device realized by a magnetic disk device, etc. 15 is a storage device D
It is a secondary storage control device realized by a disk controller with MA function. The arithmetic processing units 1 to 4, the main memory 13, and the secondary storage control unit 15 are connected to the data bus 1.
6 and an address bus 17, and by acquiring these buses, the main memory 13 can be referenced. Furthermore, when the data that the processing units 1 to 4 attempt to access does not exist in the main memory 13, the processing units 1 to 4 request the secondary storage control device 16 for the data in the secondary storage device 14. The secondary storage control device 15 outputs the requested data to the data bus 16 and the address to the address bus 17Vc. Secondary storage device 14
Data is transferred from the main memory in units of pages managed by the main memory, and the size of the page memory is assumed to be this page size. The page size is realized, for example, from 4 bytes to 8 bytes.

Next, FIG. 2 shows a concrete example of the processing block. FIG. 2 shows a specific embodiment of the processing block 9, and the processing blocks 10 to 12 have a similar structure. The processing block 9 has an arithmetic processing unit 1, a page memory 6, and a page memory management unit 18.

The arithmetic processing unit 1 and the page memory management device 18 are connected to the page memory 6 and the page memory management device 18 via a data bus 19 and an address bus 20 (together referred to as bus A).
transmits signals through a data bus 21 and an address bus 22 (together referred to as bus B), and the page memory control device 18 transmits signals to the data bus 16 through data bus 2
3, the address bus 24 outputs signals to the address bus 17 (data bus 23 and artless bus 2).
4 together are called bus d).

If the data that the arithmetic processing unit 1 attempts to refer to exists in the page memory 5, the arithmetic processing unit 1 instructs the page memory management unit 18 to transfer the signal from the bus A to the bus B, and the signal from the bus B to the bus B. The arithmetic processing unit 1 requests the data bus 16 and the address bus 17Q51° to the page memory management unit 18 by referring to the page memory 5 and avoids accessing the main memory 13.

- When rewriting the contents of page memory 6, arithmetic processing unit 1 acquires data bus 16 and address bus 17 from page memory management unit e18, and transmits the signal from bus A to both bus B and bus C. The page memory 6 and the main memory 13 are rewritten at the same time.

If the required data does not exist in the page memory 5,
The arithmetic processing unit 1 requests the page memory management unit 18 to acquire the data bus 16 and address bus 17, and to transmit signals from bus A to bus C and signals from bus C to bus A. Refer to main memory 13.

If the required data does not exist in the main memory 13, the arithmetic processing unit 1 requests the page memory management unit 18 to
It acquires data bus 16 and address bus 17 and requests to transmit signals from bus A to bus C and signals from bus C to both bus A and bus B, respectively. Furthermore, the processing unit 1 requests the secondary storage control device 16 to access the secondary storage device 14, write data from the secondary storage device 14 to the data bus 16, and write the address of the data to the address bus 17. do.

The page memory management device 18 has the page number of the page in the page memory 6, and while the arithmetic processing device 1 is not requesting data in the secondary storage device 14, the page memory management device 18 takes in the address on the address bus 17 and stores the page memory 5 in the page memory 6. It is checked whether the page held in the page has been changed, and if it is found that the page has been changed, the page number is cleared and the contents of the page memory 5 are invalidated. Thereby, even if another arithmetic processing device changes the contents of the main memory 13, subsequent processing will not be hindered.

Although this embodiment deals with the case where the number of arithmetic processing units is four, it goes without saying that the present invention can be easily implemented without being limited to the number of arithmetic processing units.

More than just the effects of the invention, it is possible to reduce the number of times a processing unit uses the address bus and data bus, and this effect is even more effective when more processing units refer to a common main memory. It is very effective and exhibits extremely high effects when applied to computers such as multiprocessor systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a computer according to an embodiment of the present invention when there are four arithmetic processing units, and FIG. 2 is a block diagram showing a specific embodiment of processing blocks. 1-4... Arithmetic processing unit, 5-8...
Page memory, 9-12...Processing block, 1
3...Main memory, 14...-Secondary storage device, 16...Secondary storage control device, 16...
...Data bus, 17...Address bus,
18...Page memory management device, 19.21.
23...Data bus, 20, 22. 24...Address bus. Name of agent: Patent attorney Toshio Nakao and one other name
1 figure

Claims (1)

[Claims] one or more arithmetic processing units that interpret and execute instructions; a main memory that is commonly accessed by the arithmetic processing units; one or more page memories that have one-to-one correspondence with each of the arithmetic processing units; and a storage device;
In the process in which the arithmetic processing unit accesses data in the corresponding page memory or the main memory, the arithmetic processing unit accesses the main memory if the data to be accessed does not exist in the page memory. Further, if the data to be accessed does not exist in the main memory, the data to be accessed is loaded from the secondary storage device to the main memory, and at the same time, the data to be accessed is requested. An electronic computer characterized in that the page memory is loaded to the page memory corresponding to the arithmetic processing unit.