JPH04194681A - Large-scale integrated circuit - Google Patents

Abstract

PURPOSE:To enable readout of an internal memory in parallel to a scanning operation by outputting to an output pin the content of the internal memory of which an address is a value of a pointer register holding a counter value when a scan pass input is '1'. CONSTITUTION:When a scan mode signal 8 is made to be '1', LSI 10 is put in a scan mode and an output of a selector 5 is switched over to a value 13 of a pointer register 3, while an output of a selector 6 is switched over to an output 15 of a memory 1. When inputting of a clock signal 12 is started and a value of 31 in Fig. 3 is given as a scan pass input 7, a value 32 of a counter 2 is set in the pointer register 3 as indicated by 33 when the value 31 is 1, the set value turns to be an address of the memory 1, the content thereof is delivered as an output 9 of the LSI 10 to an output pin, and the content as indicated by 34 of Fig. 3 is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to large-scale integrated circuits (hereinafter referred to as LSI), and particularly to a method for reading internal memory during LSI diagnosis.

[Prior Art] Conventionally, when diagnosing an LSI, when reading an LSI memory to which an address cannot be given directly from an LSI input pin, it is necessary to associate a value that will generate a target address by an address generation circuit inside the LSI. register,
The contents of the memory were read by setting the flip-flop by a scan operation or a microinstruction to operate the address generation circuit.

[Problem U to be solved by the invention] In the conventional method described above, each time the memory address is changed, values must be reset in the registers and flip-flops necessary for address generation. The disadvantage is that it takes a lot of time to read out a word.

An object of the present invention is to provide an LSI that does not require much time to read internal memory during diagnosis.

[Means for Solving the Problems] The LSI of the present invention includes: a counter whose value is incremented by 1 every clock; a pointer register that holds the value of the counter when the scan canvas input is "1"; It has a first selector that switches the address for the internal memory to the value of the pointer register in the scan mode, and a second selector that switches the output to the output pin to the output of the internal memory in the scan mode.

[Operation] In scan mode, when the scan canvas input is "1", the contents of the internal memory whose address is the value of the pointer register that holds the counter value are output to the output pin, so the address of the internal memory can be changed. It is possible to read out the internal memory in parallel with the scan operation without requiring the trouble and time of operating the address generation circuit by resetting values in the necessary registers and flip 70 every time.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the LSI of the present invention, and FIG.
This figure shows the contents of the memory 1 in FIG. 1, and FIG. 3 shows the relationship between the scan path person cuff and the values of the counter 2, pointer register 3, and LSI output 9 in FIG.

The LSI10 includes a memory 1, a counter 2, a pointer register 3, a flip-flop (hereinafter referred to as F/F) 4, a selector 5, and a selector 6. In the memory 1, contents 21 are stored at a memory address 22, as shown in FIG. The counter 2 is incremented by 1 every clock by the clock signal 12, as shown at 32 in FIG. 3, and is reset to 0 by the reset signal II. Pointer register 3 is F/
When the scan path person cuff for the scan path configured by F4 is "1", it holds the value 32 of counter 2, as shown as 33 in FIG. The value 13 of the pointer register 3 and the address value 14 of the memory 1 for normal processing are input to the selector 5, and when the scan mode signal 8 is "1", that is, in the scan mode, the value 13 of the pointer register 3 is input. is selected and output to the memory 1 address. Selector 6 is the output of memory l! 5
and other outputs 16 are input, and the scan mode signal 8 or 1 is input.
When , output 15 of memory 1 is selected and LSI 1O
It is sent to the output pin as output 9 of .

Next, the operation of this embodiment will be explained.

First, by setting the scan mode signal 8 to "1", the LS
I10 is set to the scan mode, the output of the selector 5 is switched to the value 3 of the pointer selector 3, and the output of the selector 6 is switched to the output 15 of the memory 1.

Next, the counter 2 is reset by the reset signal 11. Next, input of the clock signal 12 is started, and when the value shown as 31 in FIG. 3 is given as the scan path person cuff, the value 31 of the input scan path 7 becomes "1".
When , E32 of counter 2 becomes 3 in pointer register 3.
3, this value becomes the address of memory 1, and the contents of memory 1 are sent to the output pin as output 9 of LSI 10, and the contents like 34 in FIG. 3 are read out.

[Effects of the Invention] As explained above, in the present invention, when the scan canvas input is "1" in the scan mode, the contents of the internal memory whose address is the value of the pointer register that holds the value of the counter are output to the output pin. This eliminates the hassle and time consuming task of resetting the registers and flip-flops to operate the address generation circuit each time the internal memory address is changed during LSI diagnosis.
Since the internal memory can be read and can be performed in parallel with the scan operation, if the number of words in the internal memory is smaller than the number of flip-flops that make up the scan canvas, the time required to read the contents of the internal memory is effectively reduced. This has the effect that it can be set to 0.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the LSI of the present invention, and FIG.
This figure shows the contents of the memory 1 in FIG. 1, and FIG. 3 shows the relationship between the scan path person cuff and the values of the counter 2, pointer register 3, and LSI output 9 in FIG. 1--Memory, 2--Counter, 3--Pointer register, 4-F/F, 5.6--Selector, 7--Scanvas input, 8--Scan mode signal, 9-L Output of SI, IO...LSI. 11--Reset signal, 12--Clock signal, 13--Value of pointer register 3, 14--Address value, 15--Output of memory 1, 16--Other outputs, 21-Memory Contents of 1, 22--address, 31--value of scan path person cuff, 32--value of counter 2, 33--value of pointer register 3, 34--value of LSI output 9. Patent applicant: NEC Corporation

Claims (1)

[Claims] 1. In a large-scale integrated circuit, a counter whose value is incremented by 1 every clock; a pointer register that holds the value of the counter when a scan path input is "1"; A first selector that switches the address for the memory to the value of the pointer register in the scan mode, and a second selector that switches the output to the output pin to the output of the internal memory in the scan mode. large-scale integrated circuits.