JPH05210995A - Device and method of shifting data - Google Patents

Abstract

PURPOSE: To provide a semi-static shift register operating like a static shift register and necessitating a small arrangement space like a dynamic shift register. CONSTITUTION: This device 30 includes a latch 32, a switch 35 and an inverter 36. The input of the latch 32 receives the data, and the output outputs the receiving data in response to a first clock pulse ϕ1 . The switch 35 is connected to the latch 32. The first terminal of the switch 35 is connected to the output of the latch 32, and the data are received from the output. The switch 35 passes the data through the second terminal in response to a second clock signal ϕ2 . The inverter 36 is connected to the switch 35. The input of the inverter 36 is connected to the second terminal of the switch 35, and the data are received from the terminal. The inverter 35 inverts the receiving data to output them.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to the field of integrated circuits, and more particularly to quasi-static shift registers.

[0002]

2. Description of the Related Art A shift register is probably the simplest structure in a circuit for sequentially moving data in the circuit. The simplest shift register is a dynamic shift register, which has a structure in which a level reproduction inverter is connected to a pass transistor. Two non-overlapping clock signals alternately enable the pass transistor to allow data to pass through the shift register. The dynamic shift register has fewer components and is suitable for integrated circuits with less available space. In the dynamic shift register, the input capacitance of the inverter acts as a storage unit, so that if the stored data is often refreshed, that is, if the stored data is not accessed, the stored charge is leaked, so that the stored data is affected or lost. It may happen. Therefore, the dynamic shift register is not suitable for applications where the refresh step cannot be used.

Another type of shift register is a static shift register. This structure generally consists of a series of static latches, with the output of one latch connected to the input of the next latch. Unlike dynamic shift registers, latches hold data indefinitely. Furthermore, the latches that are the basis of static shift registers can easily augment additional functions such as reset and preset. However, since the number of components is larger than that of the dynamic shift register, the static shift register requires a large area on the integrated circuit. Therefore, when the size of the integrated circuit is severely restricted by the application or the size of the mold, the static shift register cannot be used even if it is desirable.

[0004]

Specifically, for example, video image processing requires an array of shift registers to move or sequence the Vixel data. In this case, static operation of the shift register is desirable, for example for static testing of integrated circuits and systems. However, the space available for the integrated circuit is not sufficient to accommodate the static shift register.

Therefore, a need arises for a shift register which has the operational advantages of a static shift register and the advantages of the small size and space saving of a dynamic shift register.

Further, it would be desirable to enhance the testability of integrated circuits and systems by implementing a shift register that operates statically and dynamically and can hold data values indefinitely. In most circuits and systems, such as microprocessors and digital signal processors, the shift register is the basic building block, so if the shift register is easy to test, the whole system will be easy to test.

[0007]

According to the present invention, there is provided a shift register which eliminates or alleviates the drawbacks and problems associated with conventional circuits. The shift register of the present invention includes a latch having an input and an output. The input receives data and the output outputs the received data in response to the first clock signal. A switch having first and second terminals is connected to the latch. The first terminal of the switch is connected to the output of the latch and receives data from it. The switch transmits data to the second terminal in response to the second clock signal. Further, a buffer having an input and an output is connected to the switch. The input of the buffer is connected to the second terminal of the switch,
Receive data from it. The buffer receives the data and outputs the inverted data.

An important technical advantage of the present invention is that it offers the combination of advantages of being able to operate like a static shift register and occupying less space than a dynamic shift register. .. Another important technical advantage of the present invention is that it improves the testability of the shift register and the entire system in which it is incorporated.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a conventional dynamic shift register 10. The dynamic shift register 10 has two stages 12 and 13, and each stage 12,
13 are pass transistors 16 and 17 and an inverter 1 respectively.
It consists of 9 and 20 pairs. Non-overlapping clock signals φ ₁ and φ ₂ are alternately input to the stages 12 and 13.
The data received at the input 22 of the shift register passes through the stage 12 when the pass transistor 16 is enabled by the clock signal φ ₁ . Stage 13
Pass transistor 17 is not enabled, so data is held at the output of inverter 19 and output 23
Not transmitted until. When the crack signal φ ₂ rises, the pass transistor 17 is enabled and the inverted data at the output of the inverter 19 is passed to the input of the inverter 20. In this way, the clock signals φ ₁ and φ ₂
Is shifted to a predetermined level, the data is shifted to the output of the dynamic shift register 10.

FIG. 2 shows a circuit of a conventional static shift register 25. Static shift register 25
Consists of level sensitive latches 26 and 27, the output of which is connected to the input of latch 27. The data received at the input of the latch 26 is transmitted to the output of the latch 26 when φ ₁ reaches a predetermined level. Then, the latch 27 receives the data from the output of the latch 26 and transmits the data to the output when φ ₂ reaches a predetermined level. φ ₁ and φ
₂ is a non-overlapping clock signal. In this way the data is shifted through the static shift register 25.

FIG. 3 shows a quasi-static shift register 30 according to the present invention. Stage 3 of shift register 30
1, the output of the latch 32 is the pass transistor 35.
Is connected to the source terminal of. The drain terminal of pass transistor 35 is then connected to the input of inverter 36. Furthermore, since the enable input of latch 32 is connected to the clock signal phi _1, the clock signal phi ₁
When reaches a specified level, the data on the input is transmitted to the output. The pass transistor 35 is enabled by the clock signal φ ₂ supplied to the gate terminal. Here, the two clocks φ ₁ and φ ₂ do not overlap. Stage 31 of quasi-static shift register 30 is functionally comparable to a series connection of latches 26 and 27, such as 2-bit shift register 25 shown in FIG.
Moreover, the quasi-static shift register stage 31 can be connected to the next stage 37 as well.

In the quasi-static shift register 30,
Since all other latches are replaced with pass transistors and inverters, the number of parts is substantially smaller than that of the conventional static shift register 25.
Therefore, the quasi-static shift register 30 has the advantage of saving considerable space.

The operation of the quasi-static shift register 30 will be described. When the clock signal φ ₁ rises, the latch 3
2 is enabled so that the data on the input is transmitted to the output. Data until the clock signal phi ₂ rises is stored in the output of the latch 32, the data when the clock signal phi ₂ rises to pass through the pass transistor 35. The data is held as a charge by the input capacitance of the inverter 36 and is present at the output of the inverter 36 in the form of an inverted data signal. When the clock signal φ ₁ rises again, the data is transmitted through the latch 27 of the next stage 37 of the shift register. In this way, the quasi-static shift register 3
0 has the advantage of acting as a static shift register.

The quasi-static shift register 30 can also be operated in hold mode for inspection by manipulating the clock signals φ ₁ and φ ₂ . The quasi-static shift register can be used to hold data by keeping the clock signal φ ₁ low, ie non-enabled, and moving φ ₂ . Alternatively, the same holds true when the clock signal φ ₁ is kept low, that is, non-enabled, and φ ₂ is kept high, that is, enabled. The following table summarizes some operating modes of the quasi-static shift register.

[0015]

[Table 1] QSSR: Quasi-static shift register SR: Shift register

Although the present invention has been described in detail above, various changes, modifications and substitutions can be made without departing from the scope of the present invention. For example, interactive actions, sets, presets, clears, etc. can be added as options.

With respect to the above description, the following items will be further disclosed. (1) A memory unit having an input for receiving data and an output for outputting the received data in response to a first clock signal; and a memory unit connected to the output of the memory unit and responsive to a second clock signal. A switch adapted to allow the output data to pass therethrough, and a buffer connected to the switch to receive the passage data and generate output data when received. , Shift register.

(2) In the device according to the first aspect, the shift register is characterized in that the storage section is a latch.

(3) The shift register as set forth in claim 1, wherein the switch is a pass transistor having a gate terminal for receiving the second clock signal.

(4) The shift register as set forth in claim 1, wherein the buffer is an inverter, and the output of the inverter is an inversion type of the passing data.

(5) The shift register as set forth in claim 1, wherein the first and second clock signals do not overlap each other.

(6) In the device according to the first aspect, the storage section, the switch, and the buffer constitute one stage of a shift register, and the shift register is constructed by connecting a predetermined number of stages. A shift register, characterized in that

(7) A latch having an input for receiving data and an output for outputting the received data in response to a first clock signal; and a latch connected to an output of the latch for receiving data from the latch A switch for passing the data to the second terminal in response to the second clock signal, and a second terminal for the switch. A shift register which is connected to a terminal of the switch and has an input for receiving data from the switch and an output for outputting data, and an inverter for inverting the received data.

(8) The shift register as set forth in claim 7, wherein the switch is a pass transistor having a gate terminal for receiving the second clock signal.

(9) In the device described in the seventh item, the shift register 1 is constituted by the latch, the switch and the inverter.
The shift register is configured by connecting a predetermined number of stages including a latch, a switch, and an inverter connected as described in the first paragraph, and the output of the inverter of each stage is the next stage. A shift register, characterized in that it is connected to the input of the latch of.

(10) The shift register as set forth in claim 7, wherein the first and second clock signals do not overlap each other.

(11) Latching data and reproducing the data in response to a first clock signal; receiving the reproduced data and passing the data in response to a second clock signal And a step of buffering the passing data, the method of shifting data serially.

(12) The method of shifting data according to the eleventh aspect, wherein the latching step and the passing step do not occur at the same time.

(13) Device 30 for serially shifting data
Will be provided. The device includes a latch 32 having an input and an output. The input receives data and the output provides received data in response to the first clock pulse. A switch 35 having first and second terminals is connected to the latch 32. The first terminal of switch 35 is connected to the output of latch 32 and receives data from it. The switch 35 passes the data to the second terminal in response to the second clock signal. Furthermore, an inverter 3 having an input and an output
6 is connected to the switch 35. The input of the inverter 36 is connected to and receives data from the second terminal of the switch 35. The inverter 36 inverts the received data and outputs the inverted data from the output of the inverter.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional typical dynamic shift register.

FIG. 2 is a circuit diagram of a conventional typical static shift register.

FIG. 3 is a circuit diagram of a preferred embodiment of a quasi-static shift register according to the present invention.

[Explanation of symbols]

10 Dynamic shift register 16, 17 Pass transistor 19, 20 Inverter φ ₁ , φ ₂ Clock pulse 25 Static shift register 26, 27 Latch 30 Quasi-static shift register 32 Latch 35 Pass transistor 36 Inverter

Claims (2)

[Claims] 1. A storage unit having an input for receiving data and an output for outputting the reception data in response to a first clock signal, and a storage unit connected to the output of the storage unit for a second clock signal. A switch adapted to allow the output data to pass therethrough, and a buffer connected to the switch to receive the passage data and generate output data when received. , A device for shifting data serially. 2. Latching data and reproducing the data in response to a first clock signal; receiving the reproduced data and passing the data in response to a second clock signal. Buffering the passed data, a method of serially shifting data.