JPH04153784A - Digital image processor - Google Patents

Abstract

PURPOSE:To produce a shadow of an image without using a memory of large capacity by providing a shadow data generating means and a composing means which composes the image data inputted to an input means and the shadow data given from the shadow data generating means and outputs the composite data. CONSTITUTION:An OR circuit 306 secures an OR between the output of a shadow data generating circuit 302 and the image data (original image data) given to an image processing circuit 21A. Thus the output of the circuit 21A is turned into the composite image data including the original image data and the shadow data. Then a shadow image having the same contour as an original image is formed with an optional shift extent or a shadow image is obtained from the original image with an optional shift extent with use of a FIFO memory having the especially small capacity. As a result, various shadow production processing operation can be applied to an image with use of only a memory of small capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an image processing device that digitally processes image data. In particular, the present invention relates to an image processing apparatus for digital image forming apparatuses such as digital copying machines, digital printers, and digital facsimiles.

<Prior Art> Taking a digital copying machine as an example, a recent digital copying machine has a character "m1taJ" displayed as a thin check mark, which is displayed as hatching in the original image, as shown in FIG. There are devices that can output copies with shadow images.

In conventional digital copying machines, in order to process such shading, arrow X is the main scanning direction which is the reading direction of the line sensor, and arrow Y is the relative movement direction between the line sensor and the document. In the sub-scanning direction, at least Y
A line memory for the width of the shadow in the direction (the amount of shift of the shadow image in the Y direction), for example, a line memory for several tens of lines, is required.

Alternatively, a page memory capable of storing all the image data for one screen was required.

<Problems to be Solved by the Invention> As described above, in order to process shadowing in a conventional digital copying machine, a large number of line memories or page memories are required to store shadow data, and the memory The disadvantage was that the cost was high.

Other digital image processing apparatuses similarly have the disadvantage that a large capacity memory is required to perform shading processing.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital image processing device that can eliminate the drawbacks of the prior art and cast shadows on images without using a large capacity memory.

Means for Solving the Problems> A first invention is a digital image processing device for processing given digital image data, comprising an input means into which the digital image data is sequentially inputted in chronological order; Data change point detection means for determining whether or not subsequent image data has changed with respect to preceding image data input to the means and deriving an output when a change occurs; and image data input to the input means. address assigning means for sequentially assigning addresses, a shift amount setting means for setting the shift amount of the shadow image necessary for shadow casting, and an address assigning means each time there is an output from the data change point detecting means. The shading is obtained by adding a predetermined shift amount set in the shift amount setting means to the address at that time to obtain the address, and the shading is calculated by calculating the address and storing the address;
a match signal output means for comparing the address given by the address giving means and the shading address stored in the arithmetic storage means and outputting a match signal when the two match;
Shadow data generation means for always deriving either a level or a second level binary output and inverting the output level in response to the coincidence signal, and image data and shadow data input to the input means. The present invention is characterized in that it includes a synthesizing means for synthesizing and outputting the shadow data derived from the generating means.

The shadow data generation means in the first invention further includes a first
The present invention is characterized in that it includes an intermediate level signal output means for converting at least one of the output of the level and the second level into an output of an intermediate level between the first level and the second level.

A second aspect of the invention is a digital image processing device for processing given digital image data, comprising: input means for sequentially inputting the digital image data in chronological order; Data change point detection means for determining whether or not subsequent image data has changed with respect to the data, and deriving an output when a change has occurred;
An address assigning means for sequentially assigning addresses to the image data input to the input means, a shift amount setting means for setting a shift amount of the shadow image necessary for shadow casting, and a predetermined address are set. , when the address assigned by the address assigning means is within the set address range, the activation signal is output.The shaded area indicates the range specifying means, and the shaded area indicates the output of the range specifying means, and the output of the data change point detecting means. For each occurrence, the address is obtained by adding a predetermined shift amount set in the shift amount setting means to the current address given by the address assigning means, and the shadow is calculated by the calculation storage means for storing the address. , a match signal output means for comparing the address given by the address giving means and the shading address stored in the arithmetic storage means and outputting a match signal when the two match; It always derives one of the binary outputs,
The shadow data generation means for inverting the output level in response to the coincidence signal, and the synthesis means for synthesizing and outputting the image data input to the input means and the shadow data derived from the shadow data generation means. This is a characteristic feature.

The shadow data generation means in the second invention further includes the first shadow data generation means.
The present invention is characterized in that it includes an intermediate level signal output means for converting at least one of the output of the level and the second level into an output of an intermediate level between the first level and the second level.

Furthermore, a third invention is a digital image processing device for processing given digital image data, where the digital image data is two-dimensional data composed of a plurality of line data each consisting of a plurality of pixels. Yes, each pixel is processed sequentially in synchronization with a reference clock, and each line data is processed sequentially in synchronization with a line synchronization signal, where the digital image data is sequentially input pixel by pixel in time series. means, a data change point detection means for determining whether or not subsequent pixel data has changed with respect to a preceding pixel input to the input means, and deriving an output when a change occurs; a pixel input to the input means; an address assigning means for sequentially assigning addresses to the address assigning means, and an address assigning means for outputting an amount of shift of a shadow image necessary for shadow assignment,
The shift amount includes a shift amount in the line length direction, and the shift amount in the line length direction changes in synchronization with the reference clock and is reset to an initial value by the line synchronization signal. Each time there is an output from the shift amount output means and the data change point detection means, the shading is created by adding the current shift amount output from the shift amount output means to the address at that time assigned by the address assignment means. The address is calculated, and the shading is arithmetic storage means for storing the address, and the address assigned by the address assignment means and the shading stored in the arithmetic storage means are compared with the address, and when the two match, it is a match. a coincidence signal output means for outputting a signal; and a shadow data generation means for constantly deriving either a first level or a second level binary output, and inverting the output level in response to the coincidence signal. , and a synthesizing means for synthesizing and outputting the image data input to the input means and the shadow data generated from the shadow data generating means.

The shadow data generation means in the third invention further includes the first shadow data generation means.
The present invention is characterized in that it includes an intermediate level signal output means for converting at least one of the output of the level and the second level into an output of an intermediate level between the first level and the second level.

Further, the shift amount output by the shift amount output means in the third invention further includes a shift amount in the line alignment direction, and the shift amount in the line alignment direction may be a predetermined fixed amount. Alternatively, the line synchronization signal may be changed in proportion to the line synchronization signal.

A fourth invention is a digital image processing device for processing given digital image data, wherein the digital image data is composed of a plurality of line data lined up, and each line data is synchronized with a line synchronization signal. an input means for sequentially inputting the digital image data in chronological order, and determining whether or not subsequent image data has changed with respect to preceding image data input to the input means; data change point detection means for deriving an output when a change occurs; address assignment means for sequentially assigning addresses to image data input to the input means; and shifting of shadow images necessary for shadow casting. The shift amount includes at least the shift amount in the line alignment direction, and the shift amount in the line alignment direction changes in synchronization with a line synchronization signal. Each time there is an output from the amount output means and the data change point detection means, an address is calculated by adding the shift amount output from the shift amount output means to the current address given by the address assignment means, and the shadow is an arithmetic storage means for storing an address, and a match signal output that compares the address given by the address assigning means with the address stored in the arithmetic storage means and outputs a match signal when the two match. a means for constantly deriving either a first level or a second level binary output, and a shadow data generating means for inverting the output level in response to the coincidence signal; a shadow data for one line is stored; A determining means for determining whether it is necessary to repeatedly output shadow data based on the amount of shift in the line alignment direction output from the possible line data storage means and shift amount output means, and determining whether it is necessary. When the shadow data derived from the shadow data generation means is not stored in the line data storage means, and the shadow data already stored in the line data storage means is sequentially read out, and the determination means determines that it is not necessary. , sequentially reads out the shadow data stored in the line data storage means, and sequentially stores the shadow data stored in the storage means and the shadow data derived from the shadow data generation means in the line data storage means to store the stored contents. The apparatus is characterized in that it includes a storage control means for updating the image data, and a synthesis means for synthesizing and outputting the image data input to the input means and the shadow data read from the line data storage means.

The shadow data generation means in the fourth invention further comprises:
The present invention is characterized in that it includes an intermediate level signal output means for converting at least one of the output of the level and the second level into an output of an intermediate level between the first level and the second level.

Further, the shift amount output by the shift amount output means in the fourth invention further includes a shift amount in the line length direction, and the shift amount in the line length direction is a predetermined fixed amount. It is characterized by:

Furthermore, the line data in the fourth invention consists of a plurality of pixels, each pixel is processed sequentially in synchronization with a reference clock, and the shift amount output by the shift amount output means further includes: The amount of shift in the line length direction is included, and the shift amount in the line length direction changes in proportion to the reference clock, and is reset to an initial value by the line synchronization signal. It is characterized by this.

Effect> According to the first invention, when a change point occurs in the input image data, the change point is detected by the data change point detection means. Then, a change point address of the shadow image is calculated and stored by adding a predetermined shift amount to the address of the change point.

When the address of the input image data matches the calculated and stored change point address of the shadow image, a match signal is output, and the output level of the shadow data generation means is inverted. The shadow data generation means derives a binary output, for example, a white level or black level output, and the output is inverted at a shadow data change point. Therefore, the output of the shadow data generation means is shadow data obtained by shifting the image data by a predetermined shift amount. Then, in the compositing means, the shadow data is superimposed on the image data.

According to the second invention, for shading, the output of the data change point detecting means is enabled only within the range specified by the range specifying means. Therefore, shadow data can be obtained only for image data included within the predetermined shading range.

According to the third aspect of the invention, the amount of shift of the shadow image required for shadow casting is made variable in the line length direction in proportion to the reference clock. Therefore, the width of the shadow image in the line length direction can be changed with respect to the width of the original image,
It is possible to cast shadows in the shape of an expanded or contracted original image in the line length direction.

According to the fourth aspect of the invention, the amount of shift of the shadow image required for shadow casting can be changed in the line alignment direction in proportion to the line synchronization signal. Therefore, the width of the shadow image in the line arrangement direction can be changed with respect to the width of the original image.

<Embodiment> An embodiment of the present invention will be described below by taking a digital copying machine as an example.

FIG. 17 is a schematic diagram of the entire digital copying machine to which an image processing apparatus according to an embodiment of the present invention is applied.

The digital copying machine is equipped with a contact glass 13 for setting a document 12 on the top surface of a main body 11, and a document cover 14 that can be opened and closed is provided above the contact glass 13.

A light source 15 is provided inside and above the main body 11 and is movable along the lower surface of the contact glass 13 in the direction of arrow A1. The light source 15 has a long cylindrical shape extending perpendicular to the paper surface, and the document 12 illuminated by the light source 15
The reflected light is applied to the CCD line image sensor 20 via mirrors 16, 17, and 18 and a ninth condenser lens. Then, the image sensor 20 reads the original image.

The CCD line image sensor 20 is a longitudinal sensor extending perpendicularly to the plane of the paper, with its length direction being the main scanning direction X, and reads image data line by line.

The original image data read by the CCD line image sensor 20 is provided to an image processing circuit 21 and subjected to image processing described below. The output of the image processing circuit 21 is then applied to the laser diode 22, causing the diode 22 to emit light. The laser beam output from the laser diode 22 is scanned by a polygon mirror 23 and applied to a photosensitive drum 25 via a mirror 24.

Known members such as a charging charger 26, a developing device 27, a transfer 1 separation charger 28, and a cleaner 29 are arranged around the photoreceptor drum 25, and an electrostatic latent image is formed on the surface of the photoreceptor drum 25 by an electrophotographic method. The latent image is formed and the latent image is developed into a toner image.

Then, the toner image is taken in from the paper cassette 30 and transferred onto the paper applied to the photosensitive drum 25 with the timing adjusted by the registration rollers 31 . and,
The paper onto which the toner image has been transferred is transported by a transport belt 32 and sent to a fixing device 33. The fixing device 33 fixes the toner image on the paper, and the copied paper on which the fixing has been completed is discharged to the discharge tray 34.

FIG. 18 is a block diagram showing the configuration of image processing related parts in the digital copying machine described above. The original image data read by the CCD line image sensor 2o is
The signal is amplified by an amplifier 41, converted from analog data to digital data by an A/D converter 42, and provided to the image processing circuit 21. The output image data processed by the image processing circuit 21 is then applied to the laser diode 22, causing the laser diode 22 to emit light.

Furthermore, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is generated by the timing generation circuit 44.
, the A/D converter 42 and the image processing circuit 21, and the line synchronization signal Hsync output from the line synchronization signal generation circuit 45 is applied to the image processing circuit 21 and the timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 operates in synchronization with the reference clock CK output from the clock oscillator 46, and synchronizes each line with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. perform an action. The image processing circuit 21 similarly operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is placed under the control of a CPU 47 for controlling the overall operation of the digital copying machine.

Next, as a specific configuration example of the image processing circuit 21 shown in FIG. 18, an image processing circuit 21A will be described below.

21B, 21C, 21D, 21E, and 21F will be explained.

FIG. 1 is a block diagram showing the configuration of an image processing circuit 21A according to an embodiment. First, this image processing circuit 21
If we explain each component included in A block by block,
It is as follows.

101...X coordinate counter This counter is a circuit for counting the reference clock CK given from the clock oscillator 46 (see FIG. 18) and calculating the coordinate X in the X direction, which is the main scanning direction.

The X coordinate counter 101 is connected to the line synchronization signal generation circuit 45
Line synchronization signal Hsy given from (see Figure 18)
It is reset to 1 by nc. Thereby, the X coordinate counter 101 calculates the coordinate X from the predetermined start position for each line.

102...X coordinate addition circuit The coordinate x calculated by the X coordinate counter 101 (given as the A input) is given the shadow shift amount Kx in the
This is a circuit for adding (given as B input).

103...X-coordinate first-in-first-out memory (X-coordinate FIFO memory) X-coordinate addition circuit 10
This is a memory for storing the coordinate value (z + K x ) added by 2.

Note that the stored coordinate value (x+Kx) is the value (Xn+KX) obtained by adding the shift amount Kx to the coordinate Xn of the change point of the image data in the X direction, that is, the coordinate value of the change point of the shadow data, as described later. It is controlled by the write signal WCK.

104...X coordinate comparison circuit The coordinate value (X
This circuit compares the current coordinates (n+Kx) with the current coordinates X and outputs a match signal when they match.

105...X direction range detection circuit The coordinate X is within the range set in the CPU 501, which will be described later.
This is a circuit for determining whether or not the

201...X coordinate counter This counter is connected to the line synchronization signal generation circuit 45 (18th
This is a circuit for counting the line synchronization signal Hsync given from the sub-scanning direction (see figure) and calculating the coordinate y1 in the Y direction, which is the sub-scanning direction, that is, the line number y.

The Y coordinate counter 201 is reset to 1 by a vertical synchronization signal Vsync, which is a reading start signal for each page.

202...Y coordinate addition circuit The shadow shift amount Ky in the Y direction is calculated by the Y coordinate counter 201 (given as A input).
This is a circuit for adding (given as B input).

203...Y-coordinate first-in-first-out memory (Y-coordinate FIFO memory) Y-coordinate addition circuit 20
This is a memory for storing the coordinate value (y+Ky) added in step 2.

Note that the stored coordinate value (y + K y) is the value obtained by adding the shift amount Ky to the coordinate Yn of the change point of the image data in the Y direction, that is, only the coordinate value of the change point of the shadow data. , is controlled by a write signal WCK, which will be described later.

204...Y coordinate comparison circuit Coordinate value (Y
This circuit compares the current coordinate y (n+Ky) with the current coordinate y and outputs a match signal when they match.

205...Y direction range detection circuit The coordinate y is within the range set for the CPU 50, which will be described later.
This is a circuit for determining whether or not the

301 Coordinate matching logical product circuit This circuit is a circuit that calculates the logical product of the matching signals of the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204.

The following processing is performed by the X coordinate comparison circuit 104, the Y coordinate comparison circuit 204, and the coordinate coincidence AND circuit 301.

In other words, the current coordinates (x, y) are
It is determined whether or not the change point coordinate values of the shadow data stored in the memory 103 and the Y coordinate FIFO memory 203 have reached (Xn + Kx, Yn + Ky), and if so, an output is derived. It is.

302...Shadow data generation circuit This circuit is constituted by a D flip-flop in this example.

The signal output from the coordinate matching AND circuit 301 is a change point signal of shadow data.

Therefore, in this flip-flop 302, by using the change point signal as a clock input, the output signal changes from the first level (for example, low level) to the \&2 level (for example, high level) or from the second level to il. Invert it to a level and output the shadow data.

The shadow data generation circuit 302 generates a line synchronization signal Hsync.
The output is reset for each line to the initial state,
In other words, in this embodiment, it is returned to the ml level (low level).

306...OR circuit This circuit is a circuit for calculating the OR of image data and shadow data.

401: Image data latch circuit A circuit for sequentially latching minimum unit input image data (pixels) expressed in binary levels of high level or low level in synchronization with a reference clock.

402... Change point extraction circuit This is a circuit that outputs a signal when the input pixel changes, for example, from black to white (from high level to low level) or from white to black (from low level to high level).

More specifically, the current pixel is compared with the previous pixel latched by the image data latch circuit 401 one clock ago, and if the two do not match, the current pixel is changed from the previous pixel. Therefore, it is a circuit that outputs a change point signal.

403...Logic product circuit In this image processing circuit, the change point signal output from the change point extraction circuit is used as the write signal WCK of the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203. If it is outside the predetermined range, the AND circuit 403 prevents the write signal WCK from being output, thereby prohibiting the write.

That is, the aforementioned X direction range detection circuit 105 and Y
The direction range detection circuit 205 detects the current coordinates (x,
The gate is opened only when y) is within a predetermined range, and the change point signal is allowed to pass through the AND circuit 403.

Next, the operation of the image processing circuit 21A shown in FIG. 1 will be explained with reference to specific image data.

Now, the CCD line image sensor 20 (Fig. 17,
Consider the case where the data read by the computer (see FIG. 8) is the image data shown in FIG.

In FIG. 2, the horizontally extending X direction is the main scanning direction, and the vertically extending Y direction is the sub-scanning direction. Furthermore, in FIG. 2, one square indicated by a small square is the minimum unit of data, that is, a pixel. A white square indicates a state where the pixel is 0 (low level), and a black square indicates a state where the pixel is 1 (high level).

Further, the numerical values attached along the upper side and the left side represent the X coordinate value and Y coordinate value of each pixel, respectively.

Consider the case where the image data shown in FIG. 2 is shaded with a shift amount Kx-10 coordinate in the X direction and a shift amount Ky-5 coordinate in the Y direction. It is also assumed that shading is performed on the image in the area of coordinates (1 to 24) in the X direction and coordinates (1 to 28) in the Y direction.

The image data read by the CCD line image sensor 20, amplified by the amplifier circuit 41, and converted to a digital signal by the A/D converter 42 is time-series, pixel by pixel, as follows: D (1, 1), D ( 2,1), D (3,1)...
・D C1,2), D (2,2), D (3,,2)
...D (1,3), D (2,3), D (
3, 3) ... flows into the image processing circuit 21A.

Here, D (x, y) indicates image data at coordinates (x, y), and this image data is a pixel and has a value of "0" or "1".

The image processing circuit 21A shown in FIG. 1 is reset by a line synchronization signal Hsync and a vertical synchronization signal Vsync immediately before image data is input.

Therefore, the image data latch circuit 401 has been reset, and its Q output is "0".

Also, immediately before the first reference clock CK (hereinafter simply referred to as "clock CKJ") is given, the change point extraction circuit 4
The Q output "O" of the image data latch circuit 401 is set to the A input of 02, and the first image data D (1, 1) is set to the B input. Therefore, since the data of the A input and the data of the B input are ○, the change point extraction circuit 4
The output of 02 is inactive.

Furthermore, at this point, both the X coordinate counter 101 and the X coordinate counter 201 remain reset to "1".

Next, when the first clock CK is applied from the clock oscillator 46 (see FIG. 18), the image data latch circuit 4
Image data D (1, 1) is latched at 01.

Therefore, immediately before the next clock CK is applied, the image data latch circuit 40
Image data D (1°1) latched at 1 is set, and image data D (2°1) is set to the B input.

These image data D(11) and D(2,1) are
As shown in FIG. 2, since both are "0", the output of the change point extraction circuit 402 is inactive.

At this time, the X coordinate counter 101 counts one clock CK and becomes "2", and the second counter 201 counts "2".
1" remains.

Similarly, every time the clock CK is applied, the image data latch circuit 401 latches the image data D (x-], y), and the change point extraction circuit 402 changes the image data D (x, y). It is determined whether it is a point or not.

The first change point in the image data D (x, y) occurs at D (4, 2).

At this time, D (3, 2) latched by the image data latch circuit 401 is set to the input signal of the change point extraction circuit 402, and D (4° 2) is set to the B input.

Here, since D(32) is "0" and D(4,2) is "1", the output of the change point extraction circuit 402 becomes active.

Further, the values of the X coordinate counter 101 and the Y coordinate counter 102 at this time are "4" and "2", respectively.

Then, the X coordinate addition circuit 102 receives "4" given to the A input and "K x sw, 10" given to the B input.
The A + B output is "14". Also,
The Y coordinate addition circuit 202 adds "2" given to the A input and rKy-5J given to the B input, and calculates the A
+B output becomes "7".

Furthermore, “4” is input to C human power of the X direction range detection circuit 105.
is determined to be within the range of "1" and "24" given by the CPU 501 to the A input and B human power of the X-direction range detection circuit 105.

Furthermore, since "2" is given to the C input of the Y direction range detection circuit 205, this also applies to the A input and B input of the same circuit 205.
It is determined that it is within the range of "1" and "28" given to the input.

Therefore, the outputs of the X-direction range detection circuit 105 and the Y-direction range detection circuit 205 are each "1", and the output of the change point extraction circuit 402 passes through the AND circuit 403 and is stored in the X-coordinate FIFO. Memory 103 and Y coordinate F
It is given to the IFO memory 203 as a write signal WCK,
The X-coordinate FIFO memory 103 is the X-coordinate addition circuit 102
Take in the output "14" and store it in the Y-coordinate FIFO memory 20.
3 takes in the output “7” of the Y coordinate addition circuit 202.

Since the next image data D (5, 2) is not a changing point, the output of the changing point extraction circuit 402 is inactive, and the output from the X-coordinate FIFO memory 103 and Y-coordinate FIFO memory
Write signal WCK is not applied to O memory 203.

As the processing progresses and the next change point is reached, that is, when the image data D (9, 2) is reached, the image data D (4
, 2), the output of the change point extraction circuit 402 becomes active, and the write signal WCK is applied to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203, respectively, and the X-coordinate addition circuit 102 and the output of the Y coordinate addition circuit 202 are taken in.

In this way, the same process is repeated one after another, and only when a change point is reached, the X coordinate addition circuit 102 and the Y coordinate addition circuit 202 are stored in the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203, respectively. Output is captured.

As a result, in the X coordinate FIFO memory 103, (14th, 9th, 29th, 34th, 15th, 92933rd, 15th
,20,28,33,15,20,28,33,15,
21, 27, 331 are accumulated. In addition, FIFO memory 20 for Y coordinate
Among 3 are (7, 7, 7, 7, 8, 8, 8, 8, 9, 9゜9, 9
．． 10. 10. 10. 10. 11. , 11
゜ is accumulated.

In other words, if expressed differently, the FIFO memory 10 for the X coordinate
3 and Y coordinate FIFO memory 203.
Coordinate values (14, 7) (9th, 7) (29, 7) (34,
7) (15,8) (9th,8) (298) (33,8)
(15,9)(20,9)(28,9)(33,9)(
15,10)(20,10)(28,10)(33,1
0) (15, 11) (21, 11) (27, 11) (3
3, 11) are accumulated.

When the current coordinates to be counted reach (i4, 7), a coincidence signal is output from the X-coordinate comparison circuit 104 and the Y-coordinate comparison circuit 204, as described below.

Specifically, the operation when seat machine y-line number -7 will be explained in order. The coordinates (1, 7) (2, 7) (3, 7) are determined by the X coordinate counter 101 and the X coordinate counter 201.
(4,7) is counted, and a change point is reached at the coordinates (5,7). When a change point is reached, the coordinate values output from the X coordinate addition circuit 102 and the Y coordinate addition circuit 202 are (1
5,12). Therefore, FIFO memory 1 for X coordinate
Coordinate values (15, 12) are stored in the FIFO memory 203 for 03 and Y coordinates.

Furthermore, an X coordinate counter 101 and an X coordinate counter 2
The coordinates counted by 01 are (6, 7) (7,
7) (8, 7) (9, 7) (10, 7), and although the coordinates (11, 7) are the change points, the coordinate values are changed by the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203. (21, 12) is stored.

Then, the X coordinate counter 101 and the X coordinate counter 2
The coordinates counted by 01 further advance as (12, 7) (13, 7) (14, 7).

Here, when the current coordinate to be counted reaches the coordinate (14°7), a coincidence signal is output from the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204.

To explain more specifically, the coordinates to be counted are (14
, 7), the output “14” of the X-coordinate counter 101 is given to the B input of the X-coordinate comparison circuit 104. on the other hand,
The output of the X-coordinate FIFO memory 103 is “14”, which is stored first, and the output is
It is given to six people. Therefore, the X coordinate comparison circuit 1
The A input and B input of 04 match, and a match signal is output.

Similarly, the output "7" of the X coordinate counter 201 is
It is applied to the B input of the coordinate comparison circuit 204.

On the other hand, the output of the Y-coordinate FIFO memory 203 is "7", which is stored first, and is applied to the six inputs of the Y-coordinate comparison circuit 204. Therefore, the Y coordinate comparison circuit 20
The A input and B input of No. 4 match, and a match signal is output from the comparison circuit 204.

As a result, the output of the coordinate matching AND circuit 301 becomes active.

The output of the coordinate matching AND circuit 301 is fed back to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203, and is given to each memory as a read signal RCK. Therefore, the first data in the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 are discarded, and the next data "
9th" and "7", that is, the coordinate values (9th, 7th) are set.

Further, since the output of the coordinate matching AND circuit 301 is given as a clock input to the shadow data generation circuit 302, the Q output of the shadow data generation circuit 302 changes from "0" to "1".

Thereafter, when the current coordinate to be counted becomes the coordinate (9th degree 7th), the output of the coordinate coincidence AND circuit 301 becomes active, and the output from the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203 The read signal RCK is input to the memory 103.203, and the output of each memory 103.203 is the coordinate value (29
, 7), the Q output of the shadow data generation circuit 302 is “
It is inverted from “1” to “0”.

The same processing is performed thereafter.

Then, when the coordinate reaches y-10, the FI for the X coordinate
FO memory 103 and Y coordinate FIFO memory 203
are respectively (15, 20, 28, 33, 15, 21, 27°33.
15, 21, 27, 33, 15.17, 18.22.2
6,28,29,33,15,17゜18.22,26
,28.29,331(10,10,10,10,11
,11,11°11.12.12.12.12,13.
1B, 13.13.13, 13, 13, 13.14, 1
4°14.14, 14, 14, 14.141 are stored.

When the coordinate y-10, that is, the 10th line, reaches the coordinate x-29, that is, when the current coordinate to be counted is (29, 10), the image data D (29, 10
) reaches a changing point, but this changing point is outside the range determined by the X-direction range detection circuit 105, so as explained below, the Write signal WCK is not given, and the FIFO memory 103 for X coordinate and FIFO for Y coordinate
The FO memory 203 is connected to the X coordinate addition circuit 102, respectively.
and the output of the Y coordinate addition circuit 202 are not taken in.

Specifically, when the coordinates (29, 10) are reached, the output data D (28, 10) of the image data latch circuit 401 set to the A input of the change point extraction circuit 402.
and image data D (29,10
), the output of the change point extraction circuit 402 becomes active.

However, at the coordinate x-29, the output of the X direction range detection circuit 105 is "0", so the AND circuit 403
is in a non-active state, and the active output of the change point extraction circuit cannot pass through the AND circuit 403. Therefore, the FIFO memory 103 for the X coordinate and the FIFO memory for the Y coordinate
No write signal WCK is given to the memory 203, and the coordinate value (
39°14) is not accumulated.

As a result of the above-described processing being performed on the image data of FIG. 2, the output of the shadow data generation circuit 302 is arranged in chronological order as shown in FIG. 3.

Output of shadow data generation circuit 302 and image processing circuit 21
Since the image data (original image data) given to A is logically summed in the logical sum circuit 306, the output of this image processing circuit 21A is as shown in FIG. That is, the image data is obtained by superimposing the original image data of FIG. 2 and the shadow data of FIG. 3.

FIG. 5 is a block diagram showing the configuration of an image processing circuit 21B according to another embodiment of the invention.

A feature of the configuration of the image processing circuit 21B shown in FIG. 5 is that a series connection of a multi-value conversion circuit 303 and a dither comparison circuit 304 is inserted between the shadow data generation circuit 302 and the OR circuit 306. In addition, a dither matrix memory 305 is connected to the dither comparison circuit 304.

Data from the CPU 501 is provided to each of the eight inputs and eight inputs of the multi-value conversion circuit 303. These data are, for example, 8-bit data, and are expressed as “77h” and “00h” in hexadecimal notation (h is 16
A code is given to indicate that it is expressed in decimal notation.

The output “1” of the shadow data generation circuit 302 is output from the multi-value conversion circuit 30.
3, the output of the multi-level conversion circuit 303 becomes 77h'' which is the A input data.

On the other hand, when the output "0" of the shadow data generation circuit 302 is given to the multi-value quantization circuit 303, the output of the multi-value quantization circuit 303 becomes "ooh" which is B input data. From there, halftone density data "77h" or white data "00h" is output.

The dither comparison circuit 304 compares the output from the multi-level conversion circuit 303, which is given as an input signal, and the output from the dither matrix memory 305, which is given as the B input.
When the A input data is smaller than the B input data, that is, when the output data of the multilevel conversion circuit 303 is smaller than the output data of the dither matrix memory 305, "1" is output, otherwise "0" is output. do.

That is, in the dither comparison circuit 304, the halftone density data "77
h'' is converted into dithered halftone data by referring to the dither matrix memory 305.

Therefore, the data synthesized and output by the OR circuit 306 becomes the data shown in FIG. 6 in which the original image data and the halftone data are superimposed.

In FIG. 6, for convenience, the halftone data is not expressed in dithered form (it is simply expressed by reducing the minimum unit pixel size).

Furthermore, in the case of a display device such as a CRT display that is capable of expressing the smallest unit of data (pixel) in multiple values rather than a digital copying machine, the output of the multi-value conversion circuit 303 may be fed as is to the OR circuit 306. , dither comparison circuit 304 and dither matrix memory 305 can be omitted.

The rest of the configuration of the circuit 21B in FIG. 5 is similar to the configuration of the image processing circuit 21A shown in FIG. 1, so the same parts are given the same reference numerals and the explanation here will be omitted.

FIG. 7 is a block diagram showing the configuration of an image processing circuit 21C according to another embodiment of the invention.

The structural features of the image processing circuit 21C shown in FIG.
An x generation circuit 106 is provided. The Kx generation circuit 106 generates a shadow shift amount Kx in the X direction necessary to add a shadow to the image according to instructions from the CPU 501.
This is a circuit for calculating.

To explain in more detail, the clock CK is supplied to the Kx generation circuit 106, and the generation circuit 10
The shift amount Kx generated in step 6 is increased by, for example, 0.5 in synchronization with the clock CK. K
The shift amount Kx generated by the x generation circuit 106 is given to the B input of the X coordinate addition circuit 102.

The circuit configuration other than the above is the same as that of the image processing circuit 21A described with reference to FIG. 1, and the same parts are given the same numbers and the explanation here will be omitted.

Next, the operation of the image processing circuit 21C shown in FIG. 7 will be explained.

Image processing circuit 21 in FIG. The shading process will be explained when the image data shown in FIG. 2 described above is given to C.

With respect to the image data shown in FIG. 2, the shift amount Kx in the X direction is 0 in synchronization with the clock CK, in other words, the coordinate
．． Consider a case where shading is performed in increments of 5. That is, Kx-INT(x/2), where INT() is a function that means converting into an integer.

In this example, since the shift amount Kx in the X direction increases by 0.5 in synchronization with the clock CK, the shadow image is created by uniformly thickening the original image in the X direction, as described later. It becomes an image.

Note that as long as the shift amount Kx changes in proportion to the input of the clock CK, the rate of change may be a rate expressed by an arbitrary function. For example, clock CK
In synchronization with , Kx may increase at a rate of the square. In that case, the shadow image becomes an image in which the original image becomes gradually thicker in the X direction.

Furthermore, the shift LjiKy in the Y direction is assumed to be constant at the Ky-5 coordinate.

Furthermore, it is assumed that shadow casting is performed on the image of the area of coordinates (1 to 24) in the X direction and coordinates (1 to 28) in the Y direction.

It is read by the CCD line image sensor 20 shown in FIG. 18, amplified by the amplifier circuit 41, and
The image data converted to a digital signal in time series, pixel by pixel, is D (1,1)D (2,1)D (
3,1)...D (1,2)D (2,2)D
(3,2)...D (1,3)D (2,
3) D (3, 3) ... flows into the image processing circuit 21C.

Here, D (x, y) indicates image data at the coordinates (x, y), and this image data is a pixel and has a value of "0" or "1".

The image processing circuit 21C shown in FIG. 7 is reset by the line synchronization signal Hsync and the vertical synchronization signal Vsync immediately before image data is input.

Therefore, the image data latch circuit 401 has been reset, and its Q output is "0".

Immediately before the first clock CK is applied, the A input of the change point extraction circuit 402 is set to the Q output of the image data latch circuit 401, and the B input is set to the first image data D ( 1,1)-“0” is set.

Therefore, the output of the change point extraction circuit 402 is inactive.

Furthermore, at this point, both the X coordinate counter 101 and the Y coordinate counter 201 remain reset to "1".

Next, when the first clock CK is applied from the clock oscillator 46 (see FIG. 18), the image data latch circuit 4
Image data D (1, 1) is latched at 01.

Therefore, immediately before the next clock CK is applied, the image data latch circuit 40
Image data D (1°1) latched at 1 is set, and image data D (2°1) is set to the B input.

These image data D(1°1) and D(2,1) are
As shown in FIG. 2, since both are "0", the output of the change point extraction circuit 402 is inactive.

At this time, the X coordinate counter 101 counts one clock CK and becomes "2", and the Y coordinate counter 201 counts "2".
1" remains.

Similarly, each time the clock CK is applied, the image data latch circuit 401 latches the image data D (x-1, y), and the change point extraction circuit 402 latches the image data D (x, y) at the change point. It is determined whether or not.

The first time a change point is reached in the image data D (x, y) is at D (4, 2).

At this time, D (3, 2) latched by the image data latch circuit 401 is set to the input signal of the change point extraction circuit 402, and D (42) is set to the B input.

Here, since D (3, 2) is "0" and D (4, 2) is "1", the output of the change point extraction circuit 402 becomes active.

Further, the values of the X coordinate counter 101 and the Y coordinate counter 102 at this time are "4" and "2", respectively. Furthermore, the shift amount Kx given to the B input of the X-coordinate addition circuit 102 is KxMAROINT (4/2)-2, and the value given to the eight-man power is "4", so the shift amount Kx given to the eight-man power is "4". The A+B output obtained by adding "4" and "2" applied to the B input becomes "6". Further, the Y-coordinate addition circuit 202 adds "2" given to the eight-person force and "rKy-5" given to the B input, and then adds the A+B
The output will be "7".

Furthermore, “4” is input to the C input of the X direction range detection circuit 102.
is given, and “1” and “24” are given from the CPU 501 to the eight inputs and B input of the range detection circuit 105.
is determined to be within the range.

In addition, since "2" is given to the C input of the Y direction range detection circuit 205, this also applies to the eight power and B input of the same circuit 205.
It is determined that it is within the range of "1" and "28" given to the input.

Therefore, the outputs of the X-direction range detection circuit 105 and the Y-direction range detection circuit 205 are each "1", and the output of the change point extraction circuit 402 passes through the AND circuit 403 and is FIFO memory 103 and Y coordinate F
It is given to the IFO memory as a write signal WCK, the X coordinate IF IFO memory 103 takes in the output "6" of the X coordinate addition circuit 102, and the Y coordinate FIFO memory 203 receives the output "7" of the Y coordinate addition circuit 202. Take in.

Thereafter, in the same way, when a change point occurs in the image data D (x, y), the X coordinate FIFO memory 103 and the Y coordinate
The outputs of the X coordinate addition circuit 102 and the Y coordinate addition circuit 202 are respectively taken into the coordinate FIFO memory 203. As a result, in the X coordinate FIFO memory 103, (6, 13, 28, 36, 7, 1, 3, 28, 34, 7
,15,27,34,7,15,27,34,7,16
, 25, 34) are stored, and in the Y coordinate FIFO memory 203, +7.7, 7, 7, 8, 8.8, 8, 9, 9°9.9,
10, 10.10, 10, 11.11°11.111 are stored.

In other words, the coordinate values (6,7) (13,7) (18,7) (36,7
)(7,8)(13,8)(28,8)(34,8)(
7,9)(15,9)(27,9)(34,9) (
7,10) (15,10) (2710) (
34,10) (7,11) (16,11)(2
5,11) (34,11) are stored.

Then, when the counted current coordinates reach (6, 7), a coincidence signal is output from the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204, as described below.

Specifically, the operation when the coordinate is y-line number-7 will be explained in order as follows. That is, the X coordinate counter 101 and the Y coordinate counter 201 count the coordinates (1, 7) (2, 7) (3° 7) (4, 7), and reach a changing point at the coordinate (5, 7). When a change point is reached, the X coordinate addition circuit 102 and the Y coordinate addition circuit 2
The coordinate values output from 02 are (7, 12). Therefore, the FIFO memory 103 for the X coordinate and the FIFO memory for the Y coordinate
The coordinate values (7, 12) are stored in the FO memory 203.

Then, an X coordinate counter 101 and a Y coordinate counter 2
01 counts the next coordinates (6, 7), a coincidence signal is output from the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204, respectively.

To explain more specifically, the current coordinates to be counted are (6
, 7), the output "6" of the X coordinate counter 101 is
It is given as a B input to the X coordinate comparison circuit 104. On the other hand, the output of the X-coordinate FIFO memory 103 is "6", which was stored first, and the output of the X-coordinate comparison circuit 104 is
It is given to the eight people of power. Therefore, the X coordinate comparison circuit 1
The eight power of 04 and the B input match, and a match signal is output.

Similarly, the output “7” of the Y coordinate counter 201 is Y
It is applied to the B input of the coordinate comparison circuit 204.

On the other hand, the output of the Y-coordinate FIFO memory 203 is "7", which is stored first, and is applied to the A input of the Y-coordinate comparison circuit 204. Therefore, the Y coordinate comparison circuit 20
4 and the B input match, and a match signal is output from the comparison circuit 204.

As a result, the output of the coordinate matching AND circuit 301 becomes active.

The output of the coordinate matching AND circuit 301 is fed back to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203, and is given to each memory as a read signal RCK. Therefore, the first data in the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 are discarded, and the next data "
13" and "7", that is, the coordinate values (13, 7) are set.

Further, since the output of the coordinate matching AND circuit 301 is given as a clock input to the shadow data generation circuit 302, the Q output of the shadow data generation circuit 302 changes from "0" to "1".

After 1, when the current coordinates counted become (13, 7), the output of the coordinate coincidence AND circuit 301 becomes active, and the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 The readout signal RCK is input to , the output coordinates of each memory 103 and 203 change to (28, 7), and the Q output of the shadow data generation circuit 302 is inverted from "1" to "O".

The same processing is performed thereafter.

Then, when the coordinate reaches y-10, the FI for the X coordinate
FO memory 103 and Y coordinate FIFO memory 203
(7, 15, 27, 34, 7, 16, 25, 34, 7,
16, 25, 34, 7, 10, 12, 18, 24, 27
,28,34,7,10,12゜18.24,27,2
8.34) (10,10,10,10,11,11,11゜11.
12, 12, 12.12.13, 13, 13.13.1
B, 13, 13, 13, 14, 14゜14.14.14
, 14, 14.14) are stored.

And the coordinates! -10, that is, at the 10th line, when the coordinates are x-29, that is, the current coordinates are (29,
10), the image data D (29, 10) reaches a changing point, but since this changing point is outside the range determined by the X-direction range detection circuit 105, the AND circuit 403 enters the non-active state. Even if the output of the change point extraction circuit 402 becomes active, the active output cannot pass through the AND circuit 403, and the
FO memory 103 and Y coordinate FIFO memory 203
Write signal WCK is not applied to.

Therefore, the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 are connected to the X-coordinate addition circuit 1, respectively.
02 and the output of the Y coordinate addition circuit 202 are not taken in.

As a result of the above-described processing being performed on the image data of FIG. 2, the output of the shadow data generation circuit 302 is arranged in chronological order as shown in FIG. 8.

Output of shadow data generation circuit 302 and image processing circuit 21
The image data (original image data) given to C is logically summed in the logical sum circuit 306 and synthesized.
The output of this image processing circuit 21C is as shown in FIG. That is, image data obtained by superimposing the original image data of FIG. 2 and the shadow data of FIG. 8 is obtained as processed output data.

FIG. 10 shows an image processing circuit 2 according to still another embodiment of the present invention, which is an application of the image processing circuit 21C shown in FIG.
FIG. 2 is a block diagram showing the configuration of 1D.

The image processing circuit 21D shown in FIG. 10 has a multilevel conversion circuit 303, a dither comparison circuit 304, and a dither matrix memory 305 added to the circuit shown in FIG. 7 so that a shadow image becomes a halftone image. It is something that

The output of the shadow data generation circuit 302 is multivalued in a multivalue conversion circuit 303, compared with dither data stored in a dither matrix memory 305 in a dither comparison circuit 304, and output as dithered halftone data. , will be. The output is given to OR circuit 306.

Note that the configurations and functions of the multi-level conversion circuit 303, dither comparison circuit 304, and dither matrix memory 305 are the same as those described with reference to FIG. 5, and the description thereof will be omitted here.

The output image of the image processing circuit 21D shown in FIG.
The result will be as shown in Figure 1.

The circuit in FIG. 12 is a block diagram showing the configuration of an image processing circuit 21H according to yet another embodiment of the present invention.

The image processing circuit 21E shown in FIG. 12 is a circuit that can enlarge or reduce the shadow image in the Y direction.

To this end, the image processing circuit 21E includes the following circuits in addition to the image processing circuit 21C shown in FIG. That is, 206...KV generation circuit--This circuit is for calculating the shadow shift amount KV in the Y direction. The shift amount Ky is configured to sequentially change at a constant rate in synchronization with the line synchronization signal Hsync.

Also, according to the instructions from the CPU 501, the amount of shift x in the Y direction is
It is also possible to set y to a constant value in this circuit.

601... FIFO memory for line number This FIFO
The memory is for storing the shifted line number, that is, the shifted coordinate value y.

602...Line comparison circuit This circuit compares the shifted line number and the current coordinate y, and compares the shifted line number with the current coordinate y,
This is a circuit for determining whether it is necessary to update the contents of .

603...Y-direction interpolation selection circuit This circuit is necessary for interpolating shadow data in the Y direction, and determines whether the output of the 1-line FIFO buffer memory 604, which will be described later, should be input again to the 1-line FIFO buffer memory 604. Alternatively, it is a circuit for selecting whether to update the contents of the 1-line FIFO buffer memory 604 by inputting new shadow data output from the line comparison circuit 602 to the 1-line FIFO buffer memory 604.

604...1 line FIFO buffer memory This memory is a memory for holding shadow data for one line.

The circuit configuration other than the circuit described above is the same as that of the image processing circuit 21C shown in FIG. 7, and the same parts are given the same numbers and the explanation here will be omitted.

Next, the operation of the image processing circuit 21E shown in FIG. 12 will be explained with reference to specific image data.

Consider the shading process when the image data shown in FIG. 2 described above is given to the image processing circuit 21H shown in FIG. 12.

Now, with respect to the image data shown in Fig. 2, the shift amount Kx in the X direction is constant at the Kx-10 coordinate, and the shift amount KV in the Y direction is synchronized with the line synchronization signal Hsync, in other words, with the coordinate y. Then 0. Consider a case where shading is performed in increments of 5. That is, in FIG. 12, the amount of shift Kx in the X direction output from the Kx generation circuit 106 is a constant value, KxmlO, in this embodiment.

This shift Kx does not necessarily change in synchronization with the clock CK. On the other hand, the shift amount Ky of shadow casting in the Y direction
is Ky-INT (y/2) However, INT() is a function that means conversion into an integer.

shall be.

As in this embodiment, the shift amount Ky in the Y direction is set to 0.0 in synchronization with the line synchronization signal Hs yn c. When the number is increased by 5, the shadow image becomes an image obtained by uniformly elongating the original image in the Y direction, as will be described later.

Furthermore, it is assumed that shadow casting is performed on the image of the area of coordinates (1 to 24) in the X direction and coordinates (1 to 28) in the Y direction.

In this embodiment, the shift amount Ky in the Y direction is assumed to increase by 0°5 in synchronization with the line synchronization signal Hsync, but the shift amount KV is synchronized with the line synchronization signal Hsync.
As long as it changes in proportion to the input of c, the rate of change may be expressed by any function. For example, the shift amount KY may increase at a square rate in synchronization with the line synchronization signal Hsync.

It is read by the CCD line image sensor 20 shown in FIG. 18, amplified by the amplifier circuit 41, and
The image data converted to digital signals in time series, pixel by pixel, is D (1, 1), D (2, 1), D
(3,1)...D (1,2), D (2,2)
, D (3,2)...D(1,3), D (2,3
), D (3, 3), and so on, flow into the image processing circuit 21E.

Here, D (x, y) indicates image data at coordinates (x, y), and this image data is a pixel and has a value of "Oo" or "1#".

The image processing circuit 21E shown in FIG. 12 is first reset by the vertical synchronization signal Vsync, and the image data latch circuit 401 is reset by the line synchronization signal Hsync, and its Q output is 10''.

Immediately before the first clock CK is applied, the A input of the change point extraction circuit 402 is connected to the image data latch circuit 40.
1's Q output "O" is set, and the B input is set to the first image data D (1, 1) -'0". Therefore, the output of the change point extraction circuit 402 is inactive. .

Furthermore, at this point, both the X coordinate counter 101 and the Y coordinate counter 201 remain reset to "1".

Next, when the first clock CK is applied from the clock oscillator 46 (see FIG. 18), the image data latch circuit 4
01, image data DC1,1) is latched. Therefore, immediately before the next clock CK is applied, the image data latch circuit 401
The image data D (1, 1) latched in is set,
Image data D (1, 2) is set to the B input.

Since these image data D(1,1) and D(1,2) are both "0" as shown in FIG. 2, the output of the change point extraction circuit 402 is inactive.

At this time, the X coordinate counter 101 counts one clock CK and becomes "2", and the Y coordinate counter 201 counts "2".
1" remains.

Similarly, each time the clock CK is applied, the coordinate data latch circuit 401 latches the image data D (x-1, y), and the change point extraction circuit 402 latches the image data D (x, y) at the change point. It is determined whether or not.

The first change point in the image data D (x, y) occurs at D (4, 2).

At this time, D (3, 2) latched by the image data latch circuit 401 is set to the input signal of the change point extraction circuit 402, and D (4° 2) is set to the B input.

Here, D (3, 2) is “0” and D (4, 2) is “
1'', the output of the change point extraction circuit 402 becomes active.

Further, the values of the X coordinate counter 101 and the X coordinate counter 102 at this time are "4" and "2", respectively. Furthermore, since the shift amount Kx given to the B input of the X-coordinate addition circuit 102 is Kx-10, and the value given to the B input is "4", the shift amount Kx given to the B input of the X-coordinate addition circuit 102 is ``4'' and ``10'' added to the B input are added, and the A+B output becomes ``14.'' Further, the shift amount Ky given to the 8-manpower of the Y coordinate addition circuit 202 is Ky-INT (2/2)-1, and on the other hand, the value given to the 8-manpower is the above-mentioned "2", so Y In the coordinate addition circuit 202, "2" given to the A human power and "1" given to the B input are added, and the A+B output becomes "3".

Furthermore, “4” is input to the C input of the X direction range detection circuit 105.
is given, and “1” and “24” are given from the CPU 501 to the A input and B input of the range detection circuit 105.
is determined to be within the range.

In addition, since "2" is given to the C input of the Y-direction range detection circuit 205, this is also the 8-power and 8-power of the same circuit 205.
It is determined that it is within the range of "1" and "28" given to human power.

Therefore, the outputs of the X-direction range detection circuit 105 and the Y-direction range detection circuit 205 are each "1", and the output of the change point extraction circuit 402 passes through the AND circuit 403 and is stored in the X-coordinate FIFO memory. FI for 103 and Y seat building
It is given to the FO memory as a write signal WCK, and the X-coordinate FIFO memory 103 receives the output of the
The Y-coordinate FIFO memory 203 takes in the output “3” of the Y-coordinate addition circuit 202.

Thereafter, in the same manner, when a change point occurs in the image data D (x, y), the X coordinate addition circuit 102 and the Y coordinate addition circuit 202 are stored in the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203, respectively. The output of is captured. As a result, (14, 9th, 29, 34>) is stored in the FIFO memory 103 for the X coordinate, and (3, 3, 3, 3) is stored in the FIFO memory 203 for the Y coordinate. It's getting worse.

In other words, the coordinate values (14, 3) (9th, 3) (29, 3) (34,
3) will be accumulated.

On the other hand, line synchronization signal Hsync is applied to line number FIFO memory 601 as write signal WCK. Therefore, the output "1" of the Y coordinate addition circuit 202 at that time is written into the line number FIFO memory 601 by the first line synchronization signal Hsync. However, since this value "1" is reset by the vertical synchronization signal Vsync that is first applied via the delay circuit 701, the stored contents of the line number FIFO memory 601 are cleared.

Thereafter, the output of the Y coordinate addition circuit 202 is stored in the line number FIFO memory 601 every time there is a line synchronization signal Hsync. Here, the output of the Y coordinate addition circuit 202 is a line synchronization signal, Hs y n
According to c, it changes as follows: 2+Ky (2/2)-3 3+Ky (3/2)=4 4+Ky (4/2)=6 5+Ky (5/2)-7, so the line number FIFO memory 60
1 is the coordinate y to which the shift amount Ky-INT (y/2) in the Y direction is added, that is, the line number r3J r4
J r6J r7J... are stored.

Next, the operation when the current coordinate to be counted is y-3 is as follows.
I will explain step by step.

When the coordinate is y-3, the X coordinate counter 201 is set to "3" by the line periodic signal Hsync given at the beginning of the line.
'', and the Ky generation circuit 206 generates the shift amount Ky-INT (3/2)-1. Therefore,
“3” is given to the Y-coordinate addition circuit 202,
Since "1j" is given to the B input, the output is "4"
becomes. Then, "4" outputted from the Y-coordinate addition circuit 202 is taken into the line number FIFO memory 601 and stored.

Further, the output of the line number FIFO memory 601 is "3", which was stored first, and is applied to the A input of the line comparison circuit 602. On the other hand, since the output "3" of the X coordinate counter 201 is given to the B input of the line comparison circuit 602, both the A input and the B input of the line comparison circuit 602 become "3", and the line comparison circuit 602
An image update signal is output from 02.

The image update signal is given to the line number FIFO memory 601 as a read signal RCK. Therefore, the first data in the line number FIFO memory 601 is discarded, and the next data "4" is set in the output of the memory 601.

The image update signal is also given to the Y-direction interpolation selection circuit 603 as a selection switching signal.

On the other hand, when the coordinate is y-3, the data at the change point is stored in the
It is taken into the memory 103 and the Y-coordinate FIFO memory 203.

That is, the X coordinate counter 101 and the X coordinate counter 201 calculate the coordinates (1, 3) (23) (3, 3
)(4,3) is counted, and a change point is reached at the coordinates (5,3). When a change point is reached, the X coordinate addition circuit 102
The coordinate value output by the Y coordinate addition circuit 202 is (15, 4). Therefore, the coordinate value (15, 4) is stored in the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203.

Furthermore, an X coordinate counter 101 and an X coordinate counter 2
The coordinates counted by 01 are (6, 3) (7,
3) Proceed as (8, 3), reach a changing point at the coordinates (9, 3), and enter the FI for the X coordinate.
FO memory 103 and Y coordinate FIFO memory 203
The coordinate values (9th, 4th) are stored in .

Then, the X coordinate counter 101 and the X coordinate counter 2
The coordinates counted by 01 further advance as (10, 3) (11, 3) (12, 3) (13 degrees).

Next, when the current coordinate to be counted reaches the coordinate (14°3), a coincidence signal is output from the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204.

More specifically, when the current coordinates are (14, 3), the output "14" of the X coordinate counter 101 is given to the B input of the X coordinate comparison circuit 104. - direction, FI for X coordinate
The output of the FO memory 103 is the first stored “1”.
4'' and is applied to the six inputs of the X coordinate comparison circuit 104. Therefore, the A input and B input of the X coordinate comparison circuit 104 match, and a match signal is output.

Similarly, the output “3” of the X coordinate counter 201 is applied to the B input of the Y coordinate comparison circuit 204. On the other hand, the output of the Y-coordinate FIFO memory 203 is "3", which is stored first in the - number, and is applied to the six inputs of the Y-coordinate comparison circuit 204. Therefore, the eight forces of the Y coordinate comparison circuit 204 and the B
There is a match with the input, and a match signal is output from the comparison circuit 204.

As a result, the output of the coordinate matching AND circuit 301 becomes active.

The output of the coordinate matching AND circuit 301 is fed back to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203, and is given to each memory as a continuous signal RCK. Therefore, the first data in the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 are discarded, and the next data "
9th" and "3", that is, the coordinate values (9th, 3rd) are set.

Furthermore, since the output of the coordinate matching AND circuit 301 is given as a clock input to the shadow data generation circuit 302, the Q output of the shadow data generation circuit 302 is inverted from "0" to "1".

Thereafter, when the current coordinates become <9.3), the output of the coordinate coincidence AND circuit 301 becomes active, and the X-coordinate FIFO memory 103 and Y-coordinate FIF
The read signal RCK enters the O memory 203, and each memory 10
The output value of 3,203 changes to (29, 3), and the Q output of the shadow data generation circuit 302 is inverted from 1° to 0°.

The same processing is performed thereafter.

By the way, at the coordinate y-3, that is, at the third line, the image update signal output from the line comparison circuit 602 is given to the Y-direction interpolation selection circuit 603, as described above.

This selection circuit 603 switches the connection state so that the signal from the shadow data generation circuit 302 becomes the output of the selection circuit 603 during the line period when the image update signal is applied.

Therefore, when the coordinate y=3, the data output from the shadow data generation circuit 302 is sequentially stored in the 1-line FIFO buffer memory 604.
Shadow data for each line is stored.

On the other hand, in the line comparison circuit 602, the line number F
In other words, when it is determined that the output of the IFO memory 601 and the output of the Y coordinate counter 201 do not match,
When the current coordinate y does not match the line number to which the shift amount Ky in the Y direction has been added, the line comparison circuit 602
No image update signal is output from.

At this time, the Y-direction interpolation selection circuit 603
The connection is switched so that the B input becomes the output. In other words,
The connection is switched so that the output of the 1-line FIFO buffer memory 604 is written into the buffer memory 604 again.

Note that since the clocks 1 and K are applied to the 1-line FIFO buffer memory 604 as the write signal WCK and the read signal RCK, the contents thereof are sequentially shifted in synchronization with the clock CK.

Then, when the current coordinate is y-10, the FI for X coordinate
FO memory 103 and Y coordinate FIFO memory 203
are respectively (15, 21, 27, 33, 15, 17, 18°22.
26, 28, 29, 33.15, 17, 18.22.2
6.28,29.33) (10,10,10,10,12,12,12゜12,
12. 12. 12. 12. 13. 13.
13, 13. 13. 13. 13. 13+ is stored.

Then, when the current coordinates to be counted reach the current coordinates to be counted X-29 on the 10th line of yl-10, that is, when the current coordinates to be counted become (29, 10), the image data D (29, 10 ) reaches a changing point, but since this changing point is outside the range determined by the X-direction range detection circuit 105, the AND circuit 403 remains in an inactive state, and the output of the changing point extraction circuit 402 Even if it becomes active, its active output cannot pass through the AND circuit 403, and the X coordinate FIFO memory 103
and a write signal WCK to the Y-coordinate FIFO memory 203.
is not given. Therefore, the FIFO memory 10 for the X coordinate
3 and Y coordinate FIFO memory 203, respectively.
The output "39" of the X coordinate addition circuit 102 and the output "15" of the Y coordinate addition circuit 202 are not taken in.

As a result of the above-described processing being performed on the image data shown in FIG. 2, when the outputs of the 1-line FIFO buffer memory 604 are arranged in chronological order, the image data shown in FIG. 13 is obtained.

The output of the 1-line FIFO buffer memory 604 and the image data (original image) inputted to the image processing circuit 21E are ORed and synthesized in the OR circuit 306, so the output of the image processing circuit 21F is as follows. 14th
It will be as shown in the figure.

That is, image data obtained by superimposing the original image data of FIG. 2 and the shadow data of FIG. 13 is obtained as processed output image data.

In the circuit shown in FIG. 12, the shift amount Kx in the X direction output from the Kx generation circuit 106 is kept constant at Kx-10, but both shifts Ky in the Y direction are determined by the line synchronization signal Hs.
In addition to changing in synchronization with ync, the shift amount Kx in the X direction may be changed in synchronization with clock CK. When both the shift amount Kx in the X direction and the shift amount Ky in the Y direction are changed, the generated shadow data is
This results in an image that has been transformed in both the X direction and the Y direction with respect to the original image data.

FIG. 15 shows an image processing circuit 2F, which is an application of the image processing circuit 21E of FIG. A feature of the image processing circuit 21F shown in FIG. 15 is that a shadow image can be expressed in halftones. For this, one line F
Output of IFO buffer memory 604 and OR circuit 306
A multi-value conversion circuit 303, a dither comparison circuit 304, and a dither matrix memory 305 are inserted between the two.

Note that these multi-value conversion circuit 303 and dither comparison circuit 304
The configuration and operation of the dither matrix memory 305 are the same as those of the circuit shown in FIG. 5 or FIG. 10 described above, and detailed description thereof will be omitted here.

According to the image processing circuit 21F shown in FIG. 15, since the shadow image is expressed in halftones, an image as shown in FIG. 16 is obtained as its output.

In each of the above embodiments, the X direction range detection circuit 105
The image area to be shaded is specified by the X-direction range detection circuit 105 and/or the Y-direction range detection circuit 205, but if it is not necessary to specify the image area to be shaded, The direction range detection circuit 205 may be omitted.

Note that if the shading range is not limited and shading is applied to the entire image, the address value when adding the shading shift amount to the image address at the end of the screen is larger than the maximum address of the screen. Since the size increases, it is necessary to provide a margin for that amount in the FIFO memory.

Furthermore, although the above-described embodiments have been explained using a digital copying machine as an example, the digital image processing apparatus according to the present invention can be applied to digital image forming apparatuses other than digital copying machines, and can be applied to digital image forming apparatuses other than digital copying machines. It should be noted that it can also be used for equipment.

<Effects of the Invention> According to the present invention, various shading processes can be performed on an image with only a relatively small memory capacity compared to conventional devices.

In particular, by using FIFO memory with a small capacity, it is possible to form a shadow image with the same outline as the original image with an arbitrary shift amount, or to form a shadow image that is a transformed original image with an arbitrary shift amount. can.

Therefore, according to the present invention, it is possible to provide a digital image processing device that can perform various image processing, particularly various shadow shading processing, at a low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a digital image processing circuit 21A according to an embodiment of the present invention. FIG. 2 is a diagram representing an example of current image data to be processed. FIG. 3 is a diagram showing an example of shadow data obtained as a result of processing. FIG. 4 is a diagram showing an example of image data obtained as the output of the image processing circuit 21A. FIG. 5 is a block diagram showing a configuration example of an image processing circuit 21B according to another embodiment of the invention. FIG. 6 is a diagram showing an example of image data processed and output by the image processing circuit 21B. FIG. 7 is a block diagram showing a configuration example of an image processing circuit 2IC according to still another embodiment of the present invention. FIG. 8 is a diagram showing shadow data as a result of processing by the image processing circuit 21C. FIG. 9 is a diagram showing image data output from the image processing circuit 21C. FIG. 10 is a block diagram showing a configuration example of an image processing circuit 21D according to still another embodiment of the present invention. FIG. 11 is a diagram showing an example of output image data of the image processing circuit 21D. FIG. 12 is a block diagram showing a configuration example of an image processing circuit 21E according to still another embodiment of the invention. FIG. 13 is a diagram showing shadow data obtained as a result of processing by the image processing circuit 21H. FIG. 14 is a diagram showing data obtained as the output of the image processing circuit 21E. FIG. 15 is a block diagram showing an image processing circuit 21F according to yet another embodiment of the invention. FIG. 16 is a diagram showing an example of output image data obtained by the image processing circuit 21F. FIG. 17 is a schematic diagram of the entire digital copying machine to which an image processing apparatus according to an embodiment of the present invention is applied. FIG. 18 is a block diagram showing the configuration of image processing related parts in the digital copying machine according to this embodiment. FIG. 9 is a diagram for explaining the shading process. In the figure, 21, 21A, 21B, 21D. 21E, 21F... Image processing circuit, 101... X coordinate counter, 102... X coordinate addition circuit, 103...
・FIFO memory for X coordinate, 104...X coordinate comparison circuit, 105...X direction range detection circuit, 201...Y
Coordinate counter, 202...Y coordinate addition circuit, 203.
... FIFO memory for Y coordinate, 204... Y coordinate comparison circuit, 205... Y direction range detection circuit, 301...
Coordinate matching AND circuit, 302...shadow data generation circuit,
306... OR circuit, 401... Image data latch circuit, 402... Change point extraction circuit, 403... AND circuit, 303... Multi-value conversion circuit, 304... Dither comparison circuit , 305... dither matrix memory, 1
06...Kx generation circuit, 206...Ky generation circuit,
601... FIFO memory for line number, 602...
・Line comparison circuit, 603...Y direction interpolation selection circuit, 604...1 line FIFO buffer memory.

Claims (1)

[Claims] 1. A digital image processing device for processing given digital image data, comprising: input means into which the digital image data is sequentially inputted in chronological order; Data change point detection means that determines whether the image data subsequent to the image data has changed and derives an output when a change occurs, and sequentially assigns addresses to the image data input to the input means. Shift amount setting means in which the shift amount of the shadow image necessary for shadow casting is set, and data change point detection means. Arithmetic storage means for determining a shadow casting address to which a predetermined shift amount set in the shift amount setting means is added, and storing the shadow casting address; and an address given by the address assignment means and stored in the calculation storage means. A match signal output means that compares the shadowed address and outputs a match signal when the two match, and always derives either a first level or a second level binary output, the match signal A shadow data generating means for inverting an output level in response to the shadow data generating means; and a synthesizing means for synthesizing and outputting the image data input to the input means and the shadow data derived from the shadow data generating means. Digital image processing device. 2. In the digital image processing device according to claim 1, the shadow data generation means further includes outputs of at least one of the first level and the second level.
The present invention is characterized in that it includes an intermediate level signal output means for converting the output to an intermediate level between the two levels. 3. A digital image processing device for processing given digital image data, an input means into which the digital image data is sequentially inputted in chronological order; data change point detection means for determining whether or not the image data to be processed has changed and deriving an output when a change occurs; address assignment means for sequentially assigning addresses to the image data input to the input means; A shift amount setting means in which the amount of shift of the shadow image necessary for shadow casting is set, a predetermined address is set, and an activation signal is output when the address assigned by the address assignment means is within the set address range. shading range specifying means, and each time there is an output of the shading range specifying means and an output of the data change point detecting means, the shift amount setting means sets the address assigned by the address assigning means at that time. computing storage means for determining a shadowing address to which a predetermined amount of shift has been added and storing the shadowing address; comparing the address assigned by the address assigning means with the shadowing address stored in the computing storage means; A coincidence signal output means that outputs a coincidence signal when the two match, and always derives either a first level or a second level binary output, and inverts the output level in response to the coincidence signal. 1. A digital image processing device comprising: a shadow data generating means for generating a shadow data; and a synthesizing means for synthesizing and outputting image data input to the input means and shadow data derived from the shadow data generating means. 4. In the digital image processing apparatus according to claim 3, the shadow data generation means further includes outputs of at least one of the first level and the second level.
The present invention is characterized in that it includes an intermediate level signal output means for converting the output to an intermediate level between the two levels. 5. A digital image processing device for processing given digital image data, where the digital image data is two-dimensional data composed of a plurality of line data each consisting of a plurality of pixels, and each pixel is input means into which the digital image data is sequentially input pixel by pixel in time series; A data change point detection means that determines whether or not a pixel following a pixel that follows has changed with respect to a preceding pixel that is input, and derives an output when a change occurs, and sequentially assigns addresses to pixels that are input to the input means. address assigning means for outputting a shift amount of a shadow image necessary for shadow casting, the shift amount includes a shift amount in the line length direction, and the shift amount in the line length direction is outputted. The shift amount is changed in synchronization with the reference clock and is reset to an initial value by the line synchronization signal, and address assigning means is configured to change the shift amount each time there is an output from the data change point detection means. calculation storage means for calculating the shadowed address by adding the current shift amount outputted from the shift amount output means to the current address assigned by the shift amount output means, and storing the shadowed address, the address assigned by the address assigning means; and a shading address stored in the arithmetic storage means, and a match signal output means for outputting a match signal when the two match, and constantly deriving either a first level or a second level binary output. a shadow data generation means for inverting the output level in response to the coincidence signal, and a composite of the image data input to the input means and the shadow data generated from the shadow data generation means and outputted. A digital image processing device comprising: a composition means. 6. In the digital image processing apparatus according to claim 5, the shadow data generation means further includes outputs of at least one of the first level and the second level.
The present invention is characterized in that it includes an intermediate level signal output means for converting the output to an intermediate level between the two levels. 7. In the digital image processing device according to claim 5, the shift amount output by the shift amount output means further includes a shift amount in the line arrangement direction, and the shift amount in the line arrangement direction is determined in advance. It is characterized in that it is a predetermined fixed amount. 8. In the digital image processing device according to claim 5, the shift amount outputted by the shift amount output means further includes a shift amount in the line alignment direction, and the shift amount in the line alignment direction is: It is characterized in that it changes in proportion to the line synchronization signal. 9. A digital image processing device for processing given digital image data, where the digital image data is composed of a plurality of line data lined up, and each line data is sequentially processed in synchronization with a line synchronization signal. an input means into which the digital image data is sequentially inputted in chronological order, and a method for determining whether or not subsequent image data has changed with respect to preceding image data input to the input means, and determining whether or not the subsequent image data has changed; data change point detection means for deriving an output when a change point occurs; address assignment means for sequentially assigning addresses to the image data input to the input means; outputting the shift amount of the shadow image necessary for shadow casting. Shift amount output means, wherein the shift amount includes at least a shift amount in the line alignment direction, and the shift amount in the line alignment direction is changed in synchronization with a line synchronization signal; Every time there is an output from the data change point detection means, a shadowed address is obtained by adding the shift amount output from the shift amount output means to the current address assigned by the address assignment means, and the shadowed address is stored. arithmetic storage means, a coincidence signal output means that compares the address assigned by the address assigning means and the shadowed address stored in the arithmetic storage means and outputs a coincidence signal when the two match; Shadow data generation means for always deriving one of two levels of binary output and inverting the output level in response to the coincidence signal; line data storage means capable of storing shadow data for one line; Discrimination means for determining whether it is necessary to repeatedly output shadow data based on the shift amount in the line alignment direction output from the shift amount output means; when the discrimination means determines that it is necessary, a shadow data generation means; without storing the shadow data derived from the line data storage means in the line data storage means, and sequentially reads out the shadow data already stored in the line data storage means, and when the determination means determines that it is not necessary, stores the shadow data in the line data storage means. storage control means for sequentially reading out the shadow data stored in the storage means and sequentially storing the shadow data derived from the shadow data generation means in the line data storage means to update the stored contents; and a synthesizing means for synthesizing and outputting the image data input to the input means and the shadow data read from the line data storage means. 10. In the digital image processing device according to claim 9, the shadow data generation means further includes outputs of at least one of the first level and the second level.
The present invention is characterized in that it includes an intermediate level signal output means for converting the output to an intermediate level between the two levels. 11. In the digital image processing device according to claim 9, the shift amount outputted by the shift amount output means further includes a shift amount in the line length direction, and the shift amount in the line length direction is a predetermined fixed amount. 12. In the digital image processing device according to claim 9, the line data consists of a plurality of pixels, each pixel is processed sequentially in synchronization with a reference clock, and the shift amount output means outputs The shift amount further includes a shift amount in the line length direction, and the shift amount in the line length direction changes in proportion to the reference clock and returns to the initial value by the line synchronization signal. It is characterized in that it can be reset.