JP2922618B2 - Digital image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus for digitally processing image data. In particular, the present invention relates to an image processing apparatus for a digital image forming apparatus such as a digital copying machine, a digital printer, and a digital facsimile.

<Prior Art> For example, taking a digital copying machine as an example,
As shown in FIG. 19, some recent digital copying machines can output a copy in which a shadow image displayed by hatching is added to an original image of the character "mita" displayed by the detailed check.

In a conventional digital copying machine, in order to perform such a shadowing process, an arrow X is a main scanning direction which is a reading direction of a line sensor, and an arrow Y is a sub scanning direction which is a relative moving direction between a line sensor and a document. In the scanning direction, a line memory for at least the shadow width in the Y direction (a shift amount of the shadow image in the Y direction), for example, a line memory for several tens of lines, is required. Alternatively, a page memory capable of storing all image data for one screen is required.

<Problems to be Solved by the Invention> As described above, in order to perform shadowing processing in a conventional digital copying machine, many line memories or page memories are indispensable for storing shadow data. There was a disadvantage that the cost was high.

Similarly, other digital image processing apparatuses have a disadvantage that a large-capacity memory is required to perform the shadowing processing.

Therefore, an object of the present invention is to solve the drawbacks of the prior art and to provide a digital image processing apparatus capable of performing shadowing on an image without using a large-capacity memory.

<Means for Solving the Problems> A first aspect of the present invention is a digital image processing apparatus for processing given digital image data, comprising: input means for sequentially inputting the digital image data in time series; Data change point detecting means for judging whether subsequent image data has changed with respect to preceding image data input to the means, and deriving an output when a change occurs, image data input to the input means Each time there is an output of an address assigning means for sequentially assigning an address, a shift amount setting means in which a shift amount of a shadow image required for shadowing is set, and an output of the data change point detecting means, An operation for obtaining a shadowing address obtained by adding a predetermined shift amount set by the shift amount setting means to the address to be given at that time and storing the shadowing address. Arithmetic storage means, a match signal output means for comparing an address assigned by the address assigning means with a shadowing address stored in the arithmetic storage means, and outputting a match signal when the two match.
A shadow data generating means for constantly deriving either a first level or a second level binary output, inverting an output level in response to the coincidence signal, and image data input to an input means. Combining means for combining and outputting shadow data derived from the shadow data generating means.

The shadow data generating means according to the first invention is further configured to convert an output of at least one of the first level and the second level into an output of an intermediate level between the first level and the second level. It is characterized by including means.

According to a second aspect of the present invention, there is provided a digital image processing apparatus for processing given digital image data, comprising: input means for sequentially inputting the digital image data in time series; and a preceding image input to the input means. Data change point detecting means for determining whether or not subsequent image data has changed with respect to the data and deriving an output when a change occurs, for sequentially assigning addresses to image data input to the input means Addressing means, a shift amount setting means in which a shift amount of a shadow image required for shadowing is set,
A predetermined address is set, and when the address assigned by the address assigning unit is within the set address range, there is a shadowing range identifying unit that outputs an activation signal. Every time there is an output from the point detecting means, a shadow address is obtained by adding a predetermined shift amount set in the shift amount setting means to the address at that time assigned by the address assigning means, and the shadow address is stored. Operation storage means, a coincidence signal output means for comparing an address given by the address assignment means with a shadowing address stored in the operation storage means, and outputting a match signal when the two coincide with each other; 2
The method always derives one of binary output of levels, and derives from a shadow data generating means for inverting an output level in response to the coincidence signal, and image data and shadow data generating means input to the input means. And synthesizing means for synthesizing and outputting the shadow data to be generated.

The shadow data generating means in the second invention further converts an output of at least one of the first level and the second level into an output of an intermediate level between the first level and the second level. It is characterized by including means.

Further, a third invention is a digital image processing apparatus for processing given digital image data,
Digital image data is two-dimensional data in which a plurality of line data composed of a plurality of pixels are arranged.
An input unit in which each pixel is sequentially processed in synchronization with a reference clock, and each line data is sequentially processed in synchronization with a line synchronization signal; Determine whether or not the subsequent pixel data has changed with respect to the preceding pixel input to the input means, data change point detection means to derive an output when a change occurs, a pixel input to the input means, Address assigning means for sequentially assigning an address; outputting a shift amount of a shadow image necessary for shadowing; the shift amount includes a shift amount in a line length direction; A shift amount output means for changing the shift amount in the length direction in synchronization with the reference clock and resetting the shift amount to an initial value by the line synchronization signal; Every time there is an output of the stage, a shadowing address is obtained by adding the current shift amount output from the shift amount output unit to the current address assigned by the address assigning unit, and stores the shadowing address. An operation storage unit, a match signal output unit that compares an address assigned by the address assignment unit with a shadowing address stored in the operation storage unit, and outputs a match signal when the two match. A shadow data generator for inverting the output level in response to the coincidence signal; and image data and shadow data generator input to the input unit. A synthesizing unit for synthesizing and outputting the generated shadow data.

The shadow data generation means in the third invention further comprises an intermediate level signal output for converting at least one of the output of the first level and the second level into an output of an intermediate level between the first level and the second level. It is characterized by including means.

Further, the shift amount output by the shift amount output means in the third invention further includes a shift amount in the line arrangement direction, and the shift amount in the line arrangement direction may be a predetermined fixed amount. Alternatively, it may be made to change in proportion to the line synchronization signal.

A fourth invention is a digital image processing apparatus for processing given digital image data, wherein the digital image data comprises a plurality of line data arranged side by side, and each line data is synchronized with a line synchronization signal. Input means for sequentially inputting the digital image data in chronological order, and determining whether subsequent image data has changed with respect to preceding image data input to the input means. A data change point detecting means for deriving an output when a change occurs, an address assigning means for sequentially assigning an address to image data inputted to the input means, and a shift of a shadow image required for shadowing. The shift amount includes at least the shift amount in the line arrangement direction, and the shift amount in the line arrangement direction is the line amount. Each time there is an output of the shift amount output means and the data change point detecting means which are changed in synchronization with the synchronization signal, the shift outputted from the shift amount output means to the address at that time assigned by the address assigning means. An arithmetic storage unit for storing the shadowed address to which the amount has been added, and comparing the address assigned by the address assigning unit with the shadowing address stored in the arithmetic storage unit, so that the two match. Coincidence signal output means for outputting a coincidence signal when the first level or the second level
A shadow data generating means for inverting the output level in response to the coincidence signal, a line data storage means capable of storing one line of shadow data, Based on the shift amount in the line arrangement direction output from the amount output means, the determination means for determining whether or not it is necessary to repeatedly output the shadow data. When the determination means determines that the shadow data is necessary, the shadow data generation means The derived shadow data is not stored in the line data storage means, and the shadow data already stored in the line data storage means is sequentially read out, and when the determination means determines that it is unnecessary, the shadow data is stored in the line data storage means. The shadow data stored in the storage means is sequentially read out, and the shadow data derived from the shadow data generation means is sequentially read into the line data storage means. Storage means for storing the image data input to the input means and shadow data read from the line data storage means and outputting the combined data. It is.

The shadow data generating means in the fourth invention further comprises an intermediate level signal output for converting at least one of the first level and the second level output into an intermediate level output between the first level and the second level. It is characterized by including means.

Further, the shift amount output by the shift amount output means in the fourth invention further includes a shift amount in the line length direction, and the shift amount in the line length direction is a predetermined fixed amount. It is characterized by the following.

Further, the line data in the fourth invention is composed of a plurality of pixels, each pixel is sequentially processed in synchronization with the reference clock, and the shift amount output by the shift amount output means further includes: A shift amount in the line length direction is included, and the shift amount in the line length direction changes in proportion to the reference clock, and is reset to an initial value by the line synchronization signal. It is characterized by the following.

<Operation> According to the first aspect, when a change point occurs in the input image data, the change point is detected by the data change point detecting means. Then, a change point address of the shadow image in which a predetermined shift amount is added to the address of the change point is calculated and stored. Then, when the address of the input image data matches the change point address of the calculated and stored shadow image, a match signal is output, and the output level of the shadow data generation means is inverted. The shadow data generating means derives a binary output, for example, an output of a white level or a black level, and the output is inverted at a shadow data change point. Therefore, the output of the shadow data generating means is shadow data obtained by shifting the image data by a predetermined shift amount. Then, the combining unit superimposes the shadow data on the image data.

According to the second invention, the output of the data change point detecting means is validated only within the range specified by the shadowing range specifying means. Therefore, shadow data can be obtained only for image data included in a predetermined shadowing range.

According to the third aspect, the shift amount of the shadow image required for shadowing can be changed in the line length direction in proportion to the reference clock. Therefore, the width of the shadow image in the line length direction can be changed with respect to the width of the original image, and the original image can be shaded by extending or contracting the shape in the line length direction.

According to the fourth aspect, the shift amount of the shadow image necessary for shadowing can be changed in the line arrangement direction in proportion to the line synchronization signal. Therefore, the width of the shadow image in the line arrangement direction can be changed with respect to the width of the original image.

<Embodiment> An embodiment of the present invention will be described below using a digital copying machine as an example.

FIG. 17 is a schematic configuration diagram of an entire digital copying machine to which an image processing apparatus according to one embodiment of the present invention is applied.

The digital copying machine is provided with a contact glass 13 for setting a document 12 on an upper surface of a main body 11, and an openable / closable document cover 14 is provided thereon.

Above the inside of the main body 11, a light source 15 that is movable in the direction of arrow A1 along the lower surface of the contact glass 13 is provided. The light source 15 has a long cylindrical shape extending in a direction perpendicular to the plane of the drawing, and the reflected light of the document 12 illuminated by the light source 15 is transmitted to the CCD line image sensor 20 via mirrors 16, 17, 18 and a condenser lens 19. Given. Then, the document image is read by the image sensor 20.

The CCD line image sensor 20 is a longitudinal sensor extending in a direction perpendicular to the paper surface, and its length direction is the main scanning direction X, and reads image data line by line.

The document image data read by the CCD line image sensor 20 is provided to an image processing circuit 21 and subjected to image processing described later. Then, the output of the image processing circuit 21 is supplied to the laser diode 22 to cause the diode 22 to emit light.
The laser light output from the laser diode 22 is scanned by the polygon mirror 23 and applied to the photosensitive drum 25 via the mirror 24.

Known members such as a charger 26, a developing device 27, a transfer / separation charger 28, and a cleaner 29 are arranged around the photoconductor drum 25. An electrostatic latent image is formed on the surface of the photoconductor drum 25 by an electrophotographic method. Once formed, the latent image is developed into a toner image. Then, the toner image is taken from the paper cassette 30, and is transferred to the paper supplied to the photosensitive drum 25 at a timing adjusted by the registration roller 31. Then, the sheet on which the toner image has been transferred is conveyed by the conveying belt 32 and sent to the fixing device 33. In the fixing device 33, the toner image on the paper is fixed, and the copied paper on which the fixing is completed is discharged to the discharge tray.

FIG. 18 is a block diagram showing a configuration of a part related to image processing in the digital copying machine described above. Original image data read by the CCD line image sensor 20 is amplified by an amplifier 41, converted from analog data to digital data by an A / D converter 42, and provided to the image processing circuit 21. Then, the output image data processed by the image processing circuit 21 is provided to the laser diode 22 to cause the laser diode 22 to emit light.

Further, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is supplied to the timing generation circuit 44, the A / D converter 42, and the image processing circuit 21, and the line synchronization signal output from the line synchronization signal generation circuit 45
Hsync is connected to the image processing circuit 21 and the timing generation circuit 44.
Given to.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 is
The operation is performed in synchronization with the reference clock CK output from the CPU, and the operation is performed in synchronization with each line by the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. Similarly, the image processing circuit 21 operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is under the control of a CPU 47 for controlling the entire operation of the digital copying machine.

Next, image processing circuits 21A, 21B, 21C, 21D, 21E and 21F will be described below as specific examples of the configuration of the image processing circuit 21 shown in FIG.

FIG. 1 is a block diagram showing a configuration of an image processing circuit 21A according to one embodiment. First, this image processing circuit 21A
Each component included in the following will be described in block units as follows.

101... X coordinate counter This counter is a circuit for counting the reference clock CK supplied from the clock oscillator 46 (see FIG. 18) and calculating the coordinate x in the X direction which is the main scanning direction.

The X coordinate counter 101 includes a line synchronization signal generation circuit 45.
It is reset to 1 by the line synchronizing signal Hsync given from (see FIG. 18). Thus, for each line, the X coordinate counter 101 calculates a coordinate x from a predetermined start position.

102... X-coordinate addition circuit The coordinate x (given as an A input) calculated by the X-coordinate counter 101 is added to the shadow shift amount Kx (B
(Given as an input).

103... X-coordinate first-in first-out memory (X-coordinate FIFO memory) A memory for storing the coordinate value (x + Kx) added by the X-coordinate addition circuit 102.

Note that the stored coordinate value (x + Kx) is a value obtained by adding the shift amount Kx to the coordinate Xn of the change point of the image data in the X direction (Kn + Kx), that is, only the coordinate value of the change point of the shadow data will be described later. Is controlled by the write signal WCK.

104: X coordinate comparison circuit Coordinate values (Xn + K) stored in the X coordinate FIFO memory 103
This is a circuit for comparing x) with the current coordinate x and outputting a match signal when they match.

105 X-direction range detection circuit A circuit for determining whether or not the coordinate x falls within a range set in a CPU 501 described later.

201... Y coordinate counter This counter counts the line synchronization signal Hsync supplied from the line synchronization signal generation circuit 45 (see FIG. 18) and calculates the coordinate y in the Y direction which is the sub-scanning direction, that is, the line number y. It is a circuit for performing.

The Y coordinate counter 201 is reset to 1 by a vertical synchronization signal Vsync which is a reading start signal for each page.

202... Y coordinate adding circuit The coordinate y (given as an A input) calculated by the Y coordinate counter 201 is added to the shadow shift amount Ky (B
(Given as an input).

203... Y-coordinate first-in first-out memory (Y-coordinate FIFO memory) A memory for storing the coordinate value (y + Ky) added by the Y-coordinate addition circuit 202.

Note that the stored coordinate value (y + Ky) will be a value obtained by adding the shift amount Ky to the coordinate Yn of the change point of the image data in the Y direction (Yn + Ky), that is, only the coordinate value of the change point of the shadow data will be described later. Is controlled by the write signal WCK.

204: Y coordinate comparison circuit Coordinate values (Yn + K) stored in Y coordinate FIFO memory 203
This is a circuit for comparing y) with the current coordinate y and outputting a match signal when they match.

205... Y-direction range detection circuit A circuit for determining whether or not the coordinate y falls within a range set in a CPU 501 described later.

301... Coordinate coincidence logical AND circuit This circuit is a circuit that performs logical AND of the coincidence signals of the X coordinate comparing circuit 104 and the Y coordinate comparing circuit 204.

The following processing is performed by the X coordinate comparison circuit 104, the Y coordinate comparison circuit 204, and the coordinate coincidence AND circuit 301.

That is, the current coordinate (x, y) is stored in the X coordinate FIFO memory 1
It is determined whether or not the change point coordinate value (Xn + Kx, Yn + Ky) of the shadow data stored in the 03 and Y coordinate FIFO memory 203 has been reached, and an output is derived when the coordinate value has been reached.

302... Shadow data generation circuit In this example, this circuit is configured by a D flip-flop.

The signal output from the coordinate coincidence AND circuit 301 is a change point signal of the shadow data. Therefore, in the flip-flop 302, the output signal is changed from the first level (for example, low level) to the second level (for example, high level) every clock by using the transition point signal as a clock input.
Alternatively, the shadow data is inverted from the second level to the first level and output.

The shadow data generation circuit 302 is reset by the line synchronization signal Hsync, and the output is returned to the initial state for each line, that is, to the first level (low level) in this embodiment.

306... OR circuit This circuit is a circuit for calculating the OR of image data and shadow data.

401 ... Image data latch circuit A circuit for sequentially latching the minimum unit of input image data (pixel) represented by a binary level of a high level or a low level in synchronization with a reference clock.

402... Change point extraction circuit This circuit outputs a signal when the input pixel changes from, for example, black to white (high level to low level) or white to black (low level to high level).

More specifically, the preceding pixel one clock before latched by the image data latch circuit 401 is compared with the current pixel, and if they do not match, the current pixel changes with respect to the preceding pixel. Therefore, it is a circuit for outputting a change point signal.

403 AND circuit In this image processing circuit, the change point signal output from the change point extraction circuit is stored in the X coordinate FIFO memory 103 and the Y coordinate F memory.
Although the write signal WCK of the IFO memory 203 is used, if the write signal WCK is out of a predetermined range, the write signal WCK is prevented from being output by the AND circuit 403, and the write operation is prohibited. ing.

That is, the X direction range detection circuit 105 and Y
The direction range detection circuit 205 opens the gate only when the current coordinates (x, y) are within a predetermined range, and the change point signal passes through the AND circuit 403.

Next, the operation of the image processing circuit 21A in FIG. 1 will be described with reference to specific image data.

Now, consider the case where the data read by the CCD line image sensor 20 (see FIGS. 17 and 18) is the image data shown in FIG.

In FIG. 2, the X direction extending horizontally is the main scanning direction, and the Y direction extending vertically is the sub-scanning direction. In FIG. 2, one square represented by a small square is the minimum unit data,
That is, it is a pixel. Pixels in white cells are 0 (low level)
, The black square indicates that the pixel is 1 (high level).

The numerical values given along the upper side and the left side represent the X coordinate value and the Y coordinate value of each pixel, respectively.

It is assumed that the image data shown in FIG. 2 is shaded with a shift amount Kx = 10 coordinates in the X direction and a shift amount Ky = 5 coordinates in the Y direction. The shadowing is performed on the image in the area of the coordinates (1 to 24) in the X direction and the coordinates (1 to 28) in the Y direction.

Read by the CCD line image sensor 20, the amplification circuit 41
The image data amplified by the A / D converter 42 and converted into a digital signal by the A / D converter 42 is time-series, pixel by pixel, Flows into the image processing circuit 21A.

Here, D (x, y) indicates image data at the coordinates (x, y), and this image data is a pixel and “0”
Or “1”.

The image processing circuit 21A shown in FIG. 1 has a line synchronization signal Hsync and a vertical synchronization signal Vay immediately before image data is input.
Reset by nc.

Therefore, the image data latch circuit 401 has been reset, and its Q output is "0".

In addition, the first reference clock CK (hereinafter simply referred to as “clock
CK "), the change point extraction circuit 402
Is set to the Q output “0” of the image data latch circuit 401, and the B input is set to the first image data D
(1,1) is set. Therefore, A input data = B
Since the input data = 0, the output of the change point extraction circuit 402 is non-active.

At this point, both the X coordinate counter 101 and the Y coordinate counter 201 are still being reset to “1”.

Next, when the first clock CK is given from the clock oscillator 46 (see FIG. 18), the image data latch circuit 401 latches the image data D (1,1).

Therefore, immediately before the next clock CK is applied, the image data D (1,1) latched by the image data latch circuit 401 is set to the A input of the change point extraction circuit 402, and the image data D is input to the B input. (2,1) is set. Since these image data D (1,1) and D (2,1) are both "0" as shown in FIG. 2, the output of the change point extraction circuit 402 is non-active.

At this time, the X-coordinate counter 101 counts one clock CK to “2”, and the second counter 201 sets “1”.
Remains.

Similarly, every time the clock CK is applied, the image data D (x−1, y) is latched by the image data latch circuit 401, and the image data D (x−1, y) is changed by the change point extraction circuit 402.
It is determined whether (x, y) is a change point.

The first point of change in the image data D (x, y) is
D (4,2).

At this time, D (3,2) latched by the image data latch circuit 401 is set to the A input of the change point extraction circuit 402, and D (4,2) is set to the B input. here,
Since D (3,2) is “0” and D (4,2) is “1”, the output of the change point extraction circuit 402 becomes active.

At this time, the values of the X coordinate counter 101 and the Y coordinate counter 102 are "4" and "2", respectively.

Then, the X coordinate addition circuit 102 adds “4” given to the A input and “Kx = 10” given to the B input, and the A + B output becomes “14”. Also, the Y coordinate addition circuit 20
2 adds “2” given to the A input and “Ky = 5” given to the B input, and the A + B output becomes “7”.

Further, "4" is input to the C input of the X-direction range detection circuit 105.
Is determined to be within the range of “1” and “24” given from the CPU 501 to the A input and the B input of the X direction range detection circuit 105.

Also, since "2" is given to the C input of the Y direction range detection circuit 205, this is also determined to be within the range of "1" and "28" given to the A and B inputs of the same circuit 205.

For this reason, the outputs of the X-direction range detection circuit 105 and the Y-direction range detection circuit 205 are each “1”, and the output of the change point extraction circuit 402 passes through the AND circuit 403 to output the X-coordinate FIFO. The write signal WCK is given to the memory 103 and the Y-coordinate FIFO memory 203, the X-coordinate FIFO memory 103 takes in the output “14” of the X-coordinate addition circuit 102, and the Y-coordinate FIFO memory 203 outputs the Y-coordinate addition circuit 202. Of the output "7".

Since the next image data D (5,2) is not a change point,
The output of the change point extraction circuit 402 is non-active, and X
Write signal WCK is not supplied to coordinate FIFO memory 103 and Y coordinate FIFO memory 203.

When the process proceeds and the next change point arrives, that is, when the image data D (9, 2), the output of the change point extraction circuit 402 becomes active, as in the case of the image data D (4, 2). Then, the write signal WCK is supplied to the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203, and the outputs of the X coordinate addition circuit 102 and the Y coordinate addition circuit 202 are taken in, respectively.

In this way, the same is repeated sequentially, and only when the change point comes, the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 store the X-coordinate addition circuit 102 and the Y-coordinate addition circuit 202, respectively. Output is captured.

As a result, the X-coordinate FIFO memory 103 contains ｛14,19,29,34,15,19,29,33,15,20,28,33,15,20,28,3
3,15,21,27,33｝ will be stored. Also, in the Y-coordinate FIFO memory 203, ｛7,7,7,7,8,8,8,8,9,9,9,9,10,10,10,10,11,11,11 , 1
1｝ is stored.

In other words, if the expression is changed, the coordinate values (14,7) (19,7) (29,7) (34, 7) (15,8)
(19,8) (29,8) (33,8) (15,9) (20,9) (28,9)
(33,9) (15,10) (20,10) (28,10) (33,10) (15,1
1) (21,11) (27,11) (33,11) are stored.

Then, when the counted current coordinate becomes (14, 7), a coincidence signal is output from the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204 as described below.

Specifically, the operation when coordinate y = line number = 7 will be described in order. X coordinate counter 101 and Y coordinate counter 2
According to 01, coordinates (1,7) (2,7) (3,7) (4,7) are counted, and a change point is reached at coordinates (5,7). When a change point is reached, the X coordinate adding circuit 102 and the Y coordinate adding circuit 202
The coordinate values output from are (15,12). Therefore, X
The coordinate values (15, 12) are stored in the coordinate FIFO memory 103 and the Y coordinate FIFO memory 203.

Further, an X coordinate counter 101 and a Y coordinate counter 201
The coordinates counted by (6,7) (7,7) (8,7) (9,7) (10,7) advance, and since the coordinate (11,7) is a change point, the X coordinate For FI
The FO memory 103 and the Y coordinate FIFO memory 203 store coordinate values (21, 12).

Then, the X coordinate counter 101 and the Y coordinate counter 201
The coordinates counted by (1) further advance to (12,7) (13,7) (14,7).

Here, when the counted current coordinates become the coordinates (14, 7), the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204
Outputs a match signal.

More specifically, the coordinate to be counted is (1
In the case of (4, 7), the output “14” of the X coordinate counter 101 is given to the B input of the X coordinate comparison circuit 104. On the other hand, F for X coordinate
The output of the IFO memory 103 is “14” stored first, and is supplied to the A input of the X coordinate comparison circuit 104. Therefore, the A input and the B input of the X coordinate comparison circuit 104 match, and a match signal is output.

Similarly, the output “7” of the Y coordinate counter 201 is Y
It is given to the B input of the coordinate comparison circuit 204. On the other hand, the output of the Y coordinate FIFO memory 203 is “7” stored first, and is supplied to the A input of the Y coordinate comparison circuit 204. Therefore, the A input and the B input of the Y coordinate comparison circuit 204 match, and the comparison circuit 204 outputs a match signal.

As a result, the output of the coordinate coincidence AND circuit 301 becomes active.

The output of the coordinate coincidence AND circuit 301 is the X-coordinate FIFO memory 1
The signal is fed back to the 03 and Y coordinate FIFO memories 303 and is given to each memory as a read signal RCK. Therefore, the first data of the X-coordinate FIFO memory 103 and the first data of the Y-coordinate FIFO memory 203 are discarded, and the next data "19" and "7", that is, the coordinate values (19, 7) are output to each memory. Is set.

Further, since the output of the coordinate coincidence AND circuit 301 is provided to the shadow data generation circuit 302 as a clock input, the Q output of the shadow data generation circuit 302 changes from “0” to “1”.

Thereafter, when the current coordinate to be counted becomes the coordinate (19, 7), the output of the coordinate coincidence logical AND circuit 301 is similarly activated, and the FIFO memory 103 for the X coordinate and the FIFO memory 203 for the Y coordinate are similarly activated. Read signal RCK is input and each memory 103, 20
The output of 3 changes to the coordinate value (29, 7), and the Q output of the shadow data generation circuit 302 is inverted from “1” to “0”.

 Hereinafter, the same processing is performed.

When the coordinate y = 10, the X-coordinate FIFO
10315,20,28,33,15,21,27,33,15,21,27,33,15,17,18,2
2,26,28,29,33,15,17,18,22,26,28,29,33｝, 10,10,10,10,11,11,11,11,12,12,12,12 , 13,13,13,1
3,13,13,13,13,14,14,14,14,14,14,14,14 are stored.

When the coordinate y = 10, that is, the coordinate x = 29 on the tenth line, that is, when the current coordinate to be counted is (29,10), the image data D (29,10) reaches a change point. Since this change point is outside the range defined by the X-direction range detection circuit 105, the write signal WCK is supplied to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 as described below. X-coordinate FIFO memory 103 and Y
Each of the coordinate FIFO memories 203 includes an X-coordinate addition circuit 102.
And the output of the Y coordinate addition circuit 202 are not taken in.

Specifically, when the coordinates (29, 10) are reached,
Since the output data D (28,10) of the image data latch circuit 401 set to the A input of the change point extraction circuit 402 and the image data D (29,10) set to the B input are different, The output of the point extraction circuit 402 becomes active.

However, when the coordinate x = 29, the output of the X-direction range detection circuit 105 is “0”, and the AND circuit 403 is in a non-active state. I can't pass. Thus, the X coordinate FIF
Write signal WCK to O memory 103 and Y coordinate FIFO memory 203
Is not given, and the coordinate values (39, 14) are not accumulated.

As a result of performing the processing described above on the image data of FIG. 2, the outputs of the shadow data generation circuit 302 are arranged in time series as shown in FIG.

The output of the shadow data generation circuit 302 and the image data (original image data) supplied to the image processing circuit 21A are logical talk circuits.
Since the logical sum is obtained in 306, this image processing circuit 2
The output of 1A is as shown in FIG. That is, the second
The image data is obtained by superimposing the original image data in the figure and the shadow data in FIG.

FIG. 5 is a block diagram showing a configuration of an image processing circuit 21B according to another embodiment of the present invention.

The feature of the configuration of the image processing circuit 21B shown in FIG. 5 is that a series connection of a multi-level conversion circuit 303 and a dither comparison circuit 304 is inserted between the shadow data generation circuit 302 and the OR circuit 306. Further, a dither matrix memory 305 is connected to the dither comparison circuit 304.

Data from the CPU 501 is given to the A input and the B input of the multi-level conversion circuit 303, respectively. These data are, for example, 8-bit data, and are given “77h” and “00h” in hexadecimal notation (h is a code indicating that the data is in hexadecimal notation).

When the output “1” of the shadow data generation circuit 302 is given to the multi-level quantization circuit 303, the output of the multi-level quantization circuit 303 becomes “77h” which is the A input data. On the other hand, when the output “0” of the shadow data generation circuit 302 is given to the multi-level
The output of 03 becomes “00h” which is the B input data. Therefore, the multi-level conversion circuit 303 outputs halftone density data “77h” or white data “00h”.

The dither comparison circuit 304 compares the output from the multi-level quantization circuit 303 provided as the A input with the output from the dither matrix memory 305 provided as the B input, and when the A input data is smaller than the B input data, That is, the output data of the multi-level conversion circuit 303 is stored in the dither matrix memory 305.
"1" is output when the output data is smaller than the output data, and "0" is output otherwise.

That is, in the dither comparison circuit 304, the halftone density data “77h” from the multi-level conversion circuit 303 given as the A input.
With reference to the dither matrix memory 305 to obtain halftone data expressed in dither.

Therefore, the data synthesized and output by the OR circuit 306 is as shown in FIG. 6 in which the original image data and the halftone contrast data are superimposed.

In FIG. 6, for convenience, the halftone data is not expressed in dither, but simply expressed by reducing the minimum unit pixel.

Also, in the case of a display device that can express multi-valued minimum unit data (pixels), such as a CRT display, instead of a digital copying machine, the output of the multi-valued circuit 303 may be directly supplied to the OR circuit 306. , Dither comparison circuit 3
04 and the dither matrix memory 305 can be omitted.

The other configuration of the circuit 21B in FIG. 5 is the same as the configuration of the image processing circuit 21A shown in FIG. 1, and therefore, the same portions are denoted by the same reference characters, and description thereof will not be repeated.

FIG. 7 is a block diagram showing a configuration of an image processing circuit 21C according to another embodiment of the present invention. A feature of the configuration of the image processing circuit 21C shown in FIG. 7 is that a Kx generation circuit 106 is provided. The Kx generation circuit 106 is a circuit for calculating a shadow shift amount Kx in the X direction necessary for adding a shadow to an image in accordance with an instruction from the CPU 501.

More specifically, the clock C is applied to the Kx generation circuit 106.
K is given, and the shift amount Kx generated by the generation circuit 106 is synchronized with the clock CK, for example,
It is made to increase by 0.5. The shift amount Kx generated by the Kx generation circuit 106 is given to the B input of the X coordinate addition circuit 102.

The circuit configuration other than the above is the same as that of the image processing circuit 21A described with reference to FIG. 1, and the same portions are denoted by the same reference numerals and description thereof will be omitted.

 Next, the operation of the image processing circuit 21C shown in FIG. 7 will be described.

The shadowing process when the image data shown in FIG. 2 described above is given to the image processing circuit 21C in FIG. 7 will be described.

The amount of shift Kx in the X direction with respect to the image data shown in FIG.
Let's consider a case where shadows are gradually increased. That is, Kx = INT (x / 2) where INT () is a function meaning integer conversion.

In this embodiment, the shift amount Kx in the X direction is determined by the clock.
Since it is assumed that the shadow image is increased by 0.5 in synchronization with CK, the shadow image is an image obtained by uniformly thickening the original image in the X direction, as described later.

If the shift amount Kx changes in proportion to the input of the clock CK, the rate of the change may be a rate represented by an arbitrary function. For example, Kx may increase at the rate of the square of 2 in synchronization with the clock CK. In this case, the shadow image is an image obtained by gradually increasing the thickness of the original image in the X direction.

Further, the shift amount Ky in the Y direction is assumed to be constant at Ky = 5 coordinates.

Further, the shadowing is performed on the image of the area of the coordinates (1 to 24) in the X direction and the coordinates (1 to 28) in the Y direction.

Image data read by the CCD line image sensor 20 shown in FIG. 18, amplified by the amplifier circuit 41, and converted to a digital signal by the A / D converter 42 is time-series, pixel by pixel, Flows into the image processing circuit 21C.

Here, D (x, y) indicates image data at the coordinates (x, y), and this image data is a pixel and “0”
Or “1”.

The image processing circuit 21C shown in FIG. 7 has a line synchronization signal Hsync and a vertical synchronization signal Vsy immediately before image data is input.
Reset by nc.

Therefore, the image data latch circuit 401 has been reset, and its Q output is "0".

Immediately before the first clock CK is applied, the A input of the change point extraction circuit 402 is connected to the image data latch circuit 4.
The Q output “0” of 01 is set, and the first image data D (1,1) = “0” is set to the B input. Therefore, the output of the change point extraction circuit 402 is non-active.

At this point, both the X coordinate counter 101 and the Y coordinate counter 201 are still being reset to “1”.

Next, when the first clock CK is given from the clock oscillator 46 (see FIG. 18), the image data latch circuit 401 latches the image data D (1,1).

Therefore, immediately before the next clock CK is applied, the image data D (1,1) latched by the image data latch circuit 401 is set to the A input of the change point extraction circuit 402, and the image data D is input to the B input. (2,1) is set. Since these image data D (1,1) and D (2,1) are both "0" as shown in FIG. 2, the output of the change point extraction circuit 402 is non-active.

At this time, the X-coordinate counter 101 counts one clock CK to be “2”, and the Y-coordinate counter 201 has “1”.
Remains.

Similarly, every time the clock CK is applied, the image data D (x−1, y) is latched by the image data latch circuit 401, and the image data D (x−1, y) is changed by the change point extraction circuit 402.
It is determined whether (x, y) is a change point.

The first point of change in the image data D (x, y) is
D (4,2).

At this time, D (3,2) latched by the image data latch circuit 401 is set to the A input of the change point extraction circuit 402, and D (4,2) is set to the B input. here,
Since D (3,2) is “0” and D (4,2) is “1”, the output of the change point extraction circuit 402 becomes active.

At this time, the values of the X coordinate counter 101 and the Y coordinate counter 102 are "4" and "2", respectively. Further, the shift amount Kx given to the B input of the X coordinate addition circuit 102 is Kx = INT (4/2) = 2, and the value given to the A input is "4".
The A + B output obtained by adding “4” given to the input and “2” given to the B input is “6”. Further, the Y coordinate adding circuit 202 adds “2” given to the A input and “Ky = 5” given to the B input, and the A + B output becomes “7”.

Further, "4" is input to the C input of the X direction range detection circuit 102.
Is determined to be within the range of “1” and “24” given from the CPU 501 to the A and B inputs of the range detection circuit 105.

Also, since "2" is given to the C input of the Y direction range detection circuit 205, this is also determined to be within the range of "1" and "28" given to the A and B inputs of the same circuit 205.

For this reason, the outputs of the X-direction range detection circuit 105 and the Y-direction range detection circuit 205 are each “1”, and the output of the change point extraction circuit 402 passes through the AND circuit 403 to output the X-coordinate FIFO. The write signal WCK is given to the memory 103 and the Y-coordinate FIFO memory, and the X-coordinate FIFO memory 103 takes in the output “6” of the X-coordinate addition circuit 102. Capture the output "7".

Similarly, when a change point comes to the image data D (x, y), the X coordinate FIFO memory 103 and the Y coordinate FIF
The X-coordinate addition circuit 102 and the Y-coordinate
The output of the coordinate adding circuit 202 is taken. As a result, in the X coordinate FIFO memory 103, ｛6,13,28,36,7,13,28,34,7,15,27,34,7,15,27,34,7,
16,25,34｝ are stored, and in the Y-coordinate FIFO memory 203, {7,7,7,7,8,8,8,8,9,9,9,9,10,10,10 10,10,11,11,11,1
1｝ is stored.

In other words, the X-coordinate FIFO memory 10 composed of two pairs
The coordinate values (6,7) (13,7) (18,7) (36,7) (7,8) (1
3,8) (28,8) (34,8) (7,9) (15,9) (27,9) (34,
9) (7,10) (15,10) (27,10) (34,10) (7,11) (1
6,11) (25,11) (34,11) are stored.

When the current coordinates to be counted become (6, 7), a coincidence signal is output from the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204 as described below.

Specifically, the operation when coordinate y = line number = 7 is
This will be described in order as follows. That is, the X coordinate counter 101 and the Y coordinate counter 201 determine the coordinates (1,
7) (2,7) (3,7) (4,7) are counted and the coordinates (5,
7) is at a turning point. When the change point is reached, the coordinate values output from the X coordinate addition circuit 102 and the Y coordinate addition circuit 202 are (7, 12). Therefore, the X coordinate FIFO memory 103
And the Y-coordinate FIFO memory 203 stores coordinate values (7,1
2) is stored.

Then, the X coordinate counter 101 and the Y coordinate counter 201
When the next coordinate (6, 7) is counted, a match signal is output from each of the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204.

More specifically, when the current coordinate to be counted is (6, 7), the output “6” of the X coordinate counter 101 is X
It is provided to the coordinate comparison circuit 104 as a B input. On the other hand, X
The output of the coordinate FIFO memory 103 is “6” stored first, and is supplied to the A input of the X coordinate comparison circuit 104. Therefore, the A input and the B input of the X coordinate comparison circuit 104 match, and a match signal is output.

Similarly, the output “7” of the Y coordinate counter 201 is Y
It is given to the B input of the coordinate comparison circuit 204. On the other hand, the output of the Y coordinate FIFO memory 203 is “7” stored first, and is supplied to the A input of the Y coordinate comparison circuit 204. Therefore, the A input and the B input of the Y coordinate comparison circuit 204 match, and the comparison circuit 204 outputs a match signal.

As a result, the output of the coordinate coincidence AND circuit 301 becomes active.

The output of the coordinate coincidence AND circuit 301 is the X-coordinate FIFO memory 1
The signal is fed back to the 03 and Y coordinate FIFO memory 203 and is given to each memory as a read signal RCK. Therefore, the first data of the X-coordinate FIFO memory 103 and the first data of the Y-coordinate FIFO memory 203 are discarded, and the next data "13" and "7", that is, the coordinate values (13, 7) are output from the memories. Is set.

Further, since the output of the coordinate coincidence AND circuit 301 is provided to the shadow data generation circuit 302 as a clock input, the Q output of the shadow data generation circuit 302 changes from “0” to “1”.

Thereafter, when the counted current coordinate becomes (13, 7), the output of the coordinate coincidence logical AND circuit 301 is similarly activated, and the X coordinate FIFO memory 103 and the Y coordinate FIF
The read signal RCK is input to the O memory 203, and the output coordinates of each of the memories 103 and 203 change to (28, 7).
The output is inverted from “1” to “0”.

 Hereinafter, the same processing is performed.

When the coordinate y = 10, the X-coordinate FIFO
The memory 103 and the Y-coordinate FIFO memory 203 store ｛7,15,27,34,7,16,25,34,7,16,25,34,7,10,12,18,2
4,27,28,34,7,10,12,18,24,27,28,34｝, 10,10,10,10,11,11,11,11,12,12,12,12,13 , 13,13,1
3,13,13,13,13,14,14,14,14,14,14,14,14 are stored.

Then, at the coordinate y = 10, that is, at the tenth line,
When the coordinate x = 29, that is, when the current coordinate is (29,10), the image data D (29,10) reaches a change point. The change point is determined by the X-direction range detection circuit 105. Therefore, the AND circuit 403 remains in the non-active state, and even if the output of the change point extraction circuit 402 becomes active, the active output cannot pass through the AND circuit 403, The write signal WCK is not supplied to the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203. Therefore, the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 store the output of the X-coordinate addition circuit 102 and the Y-coordinate FIFO memory 203, respectively.
The output of the coordinate adding circuit 202 is not taken.

As a result of performing the processing described above on the image data of FIG. 2, the outputs of the shadow data generation circuit 302 are arranged in time series as shown in FIG.

The output of the shadow data generation circuit 302 and the image data (original image data) supplied to the image processing circuit 21C are output from an OR circuit.
Since the logical sum is obtained at 306 and synthesized, the output of the image processing circuit 21C is as shown in FIG. That is, image data in which the original image data of FIG. 2 and the shadow data of FIG. 8 are superimposed is obtained as the processing output data.

FIG. 10 shows an image processing circuit 21D according to still another embodiment of the present invention to which the image processing circuit 21C shown in FIG. 7 is applied.
FIG. 3 is a block diagram showing the configuration of FIG.

An image processing circuit 21D shown in FIG. 10 is a multi-value conversion circuit with respect to the circuit shown in FIG. 7 so that a shadow image becomes a halftone image.
303, dither comparison circuit 304 and dither matrix memory
305 is added.

The output of the shadow data generation circuit 302 is multi-valued by a multi-value conversion circuit 303, compared with dither data stored in a dither matrix memory 305 by a dither comparison circuit 304, and output as dither-expressed halftone data. You. The output is provided to the OR circuit 306.

Note that the configurations and functions of the multilevel conversion circuit 303, the dither comparison circuit 304, and the dither matrix memory 305 are as follows.
This is the same as that described with reference to FIG. 5, and a description thereof will be omitted.

The output image of the image processing circuit 21D shown in FIG. 10 is as shown in FIG.

FIG. 12 is a block diagram showing a configuration of an image processing circuit 21E according to still another embodiment of the present invention. First
The image processing circuit 21E shown in FIG. 2 is a circuit that can enlarge or reduce a shadow image in the Y direction.

For this purpose, the following circuit is added to the image processing circuit 21E in addition to the image processing circuit 21C shown in FIG. That is, 206 ... Ky generation circuit This circuit is for calculating the shift amount Ky of the shadow in the Y direction. The shift amount Ky is determined by the line synchronization signal Hs
It is designed to change sequentially at a fixed rate in synchronization with the ync.

In addition, the circuit is capable of setting the shift amount Ky in the Y direction to a constant value in accordance with an instruction from the CPU 501.

601... FIFO memory for line numbers This FIFO memory is for storing shifted line numbers, that is, shifted coordinate values y.

602... Line Comparison Circuit This circuit is a circuit for comparing the shifted line number with the current coordinate y to determine whether or not the contents of the one-line FIFO buffer memory 604 described later need to be updated.

603... Y-directional interpolation selection circuit This circuit is necessary for interpolating shadow data in the Y direction. Whether the output of the one-line FIFO buffer memory 604 described later should be input to the one-line FIFO buffer memory 604 again, Alternatively, the new shadow data output from the line comparison circuit 602 is input to the one-line FIFO buffer memory 604 to select whether to update the contents of the one-line FIFO buffer memory 604.

604... 1-line FIFO buffer memory This memory is for holding shadow data for one line.

The circuit configuration other than the circuit described above is the same as that of the image processing circuit 21C shown in FIG. 7, and the same portions are denoted by the same reference numerals and description thereof will be omitted.

Next, the operation of the image processing circuit 21E shown in FIG. 12 will be described with reference to specific image data.

Consider the shadowing process when the image data shown in FIG. 2 is given to the image processing circuit 21E shown in FIG.

Now, with respect to the image data shown in FIG. 2, the shift amount Kx in the X direction is constant at Kx = 10 coordinates, and the shift amount Ky in the Y direction.
However, consider a case in which shadowing is performed such that it increases by 0.5 in synchronization with the line synchronization signal Hsync, in other words, the coordinate y.
That is, in FIG. 12, the shift amount Kx in the X direction output from the Kx generation circuit 106 is a constant value in this embodiment, and Kx = 10. This staggered Kx is the clock
It does not change in synchronization with CK. On the other hand, the shift amount Ky of the shadowing in the Y direction is Ky = INT (y / 2), where INT () is a function meaning integer conversion.

And

As in this embodiment, when the shift amount Ky in the Y direction is increased by 0.5 in synchronization with the line synchronization signal Hsync, as described later, the shadow image uniformly lengthens the original image in the Y direction. Become an image.

Further, the shadowing is performed on the image of the area of the coordinates (1 to 24) in the X direction and the coordinates (1 to 28) in the Y direction.

In this embodiment, the shift amount Ky in the Y direction is assumed to increase by 0.5 in synchronization with the line synchronization signal Hsync, but the shift amount Ky changes in proportion to the input of the line synchronization signal Hsync. Then, the rate of the change may be a rate represented by an arbitrary function. For example, the shift amount Ky may increase at a rate of a square in synchronization with the line synchronization signal Hsync.

Image data read by the CCD line image sensor 20 shown in FIG. 18, amplified by the amplifier circuit 41, and converted to a digital signal by the A / D converter 42 is time-series, pixel by pixel, Flows into the image processing circuit 21E.

Here, D (x, y) indicates image data at the coordinates (x, y), and this image data is a pixel and “0”
Or it has the value “1”.

The image processing circuit 21E shown in FIG. 12 is first reset by the vertical synchronizing signal Vsync, and the line synchronizing signal Hsy
The image data latch circuit 401 is reset by nc, and its Q output is “0”.

Immediately before the first clock CK is applied, the A input of the change point extraction circuit 402 is connected to the Q input of the image data latch circuit 401.
The output “0” is set, and the first image data D (1,1) = “0” is set in the B input. Therefore, the output of the change point extraction circuit 402 is non-active.

At this point, both the X coordinate counter 101 and the Y coordinate counter 201 are still being reset to “1”.

Next, when the first clock CK is given from the clock oscillator 46 (see FIG. 18), the image data latch circuit 401 latches the image data D (1,1). Therefore, immediately before the next clock CK is supplied, the change point extraction circuit 402
The image data D (1,1) latched by the image data latch circuit 401 is set to the A input of the device, and the image data D (1,2) is set to the B input. These image data D
Since (1,1) and D (1,2) are both "0" as shown in FIG. 2, the output of the change point extraction circuit 402 is non-active.

At this time, the X-coordinate counter 101 counts one clock CK to be “2”, and the Y-coordinate counter 201 has “1”.
Remains.

Similarly, every time the clock CK is supplied, the coordinate data latch circuit 401 latches the image data D (x−1, y), and the change point extraction circuit 402
It is determined whether (x, y) is a change point.

The first point of change in the image data D (x, y) is
D (4,2).

At this time, D (3,2) latched by the image data latch circuit 401 is set to the A input of the change point extraction circuit 402, and D (4,2) is set to the B input. here,
Since D (3,2) is “0” and D (4,2) is “1”, the output of the change point extraction circuit 402 becomes active.

At this time, the values of the X coordinate counter 101 and the Y coordinate counter 102 are "4" and "2", respectively. Further, the shift amount Kx given to the B input of the X coordinate adding circuit 102 is Kx = 10, and the value given to the B input is “4”. "4" and "10" given to the B input are added, and the A + B output becomes "14". Further, the shift amount Ky given to the B input of the Y coordinate addition circuit 202 is Ky = INT (2/2) = 1, while the value given to the A input is the above-mentioned "2". In the coordinate adding circuit 202, “2” given to the A input and “1” given to the B input are added, and the A + B output becomes “3”.

Further, "4" is input to the C input of the X-direction range detection circuit 105.
Is determined to be within the range of “1” and “24” given from the CPU 501 to the A and B inputs of the range detection circuit 105.

Also, since "2" is given to the C input of the Y direction range detection circuit 205, this is also determined to be within the range of "1" and "28" given to the A and B inputs of the same circuit 205.

For this reason, the outputs of the X-direction range detection circuit 105 and the Y-direction range detection circuit 205 are each “1”, and the output of the change point extraction circuit 402 passes through the AND circuit 403 and the X-coordinate FIFO memory. Write signal W to 103 and Y coordinate FIFO memory
CK, and the X coordinate FIFO memory 103 takes in the output “14” of the X coordinate addition circuit 102 and outputs the Y coordinate FIFO memory 2
03 takes in the output “3” of the Y coordinate addition circuit 202.

Similarly, when a change point comes to the image data D (x, y), the X coordinate FIFO memory 103 and the Y coordinate FIF
The X-coordinate addition circuit 102 and the Y-coordinate
The output of the coordinate adding circuit 202 is taken. As a result, {14,19,29,34} is stored in the X-coordinate FIFO memory 103, and {3,3,3,3} is stored in the Y-coordinate FIFO memory 203. To go.

In other words, the X-coordinate FIFO memory 10 composed of two pairs
The coordinate values (14,3) (19,3) (29,3) (34,3) are stored by the 3 and Y coordinate FIFO memory 203.

On the other hand, the line synchronization signal Hsync is given to the line number FIFO memory 601 as the write signal WCK. For this reason, the line number F
The output “1” of the Y coordinate adding circuit 202 at that time is written in the IFO memory 601. However, since this value “1” is reset by the vertical synchronization signal Vsync first given through the delay circuit 701, the line number FIFO memory 60
The stored contents of 1 are cleared.

Thereafter, the output of the Y coordinate addition circuit 202 is stored in the line number FIFO memory 601 each time the line synchronization signal Hsync is present. Here, the output of the Y coordinate addition circuit 202 is 2 + Ky (2/2) = 3 in accordance with the line synchronization signal Hsync. Therefore, the line number FIFO memory 601 stores the coordinate y to which the shift amount Ky = INT (y / 2) in the Y direction is added, that is, the line numbers “3”, “4”, “6”, and “6”. 7 "...
Is stored.

Next, the operation when the current coordinate to be counted is y = 3 will be described step by step.

When the coordinate y = 3, the Y coordinate counter 201 counts “3” by the line synchronization signal Hsync given at the beginning of the line, and the Ky generation circuit 206 sets the shift amount Ky = INT.
(3/2) = 1 is generated. Therefore, "3" is given to the A input and "1" is given to the B input of the Y coordinate addition circuit 202, so that the output is "4". "4" output from the Y coordinate addition circuit 202 is a line number FIFO.
It is taken into the memory 601 and stored.

The output of the line number FIFO memory 601 is “3” stored first, which is supplied to the A input of the line comparison circuit 602. On the other hand, the line comparison circuit 6
Since the output “3” of the Y coordinate counter 201 is given to the B input of 02, both the A input and the B input of the line comparison circuit 602 become “3”, and the line comparison circuit 602 outputs an image update signal.

The image update signal was given to the line number FIFO memory 601 as a read signal RCK. Therefore, F for line number
The first data of the IFO memory 601 is discarded and the memory 60
The next data “4” is set in the output of “1”.

The image update signal is also supplied to the Y-direction interpolation selection circuit 603 as a selection switching signal.

On the other hand, also at the coordinate y = 3, the data at the change point is taken into the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203 as in the case of the coordinates y = 1 and 2.

That is, the X coordinate counter 101 and the Y coordinate counter 2
According to 01, coordinates (1,3) (2,3) (3,3) (4,3) are counted, and a change point is reached at coordinates (5,3). When a change point is reached, the X coordinate adding circuit 102 and the Y coordinate adding circuit 202
Is (15,4). Therefore,
The X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 store coordinate values (15, 4).

Further, an X coordinate counter 101 and a Y coordinate counter 201
The coordinates counted by (6,3) (7,3) (8,3) advance to the changing point at the coordinates (9,3), and the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203 Has the coordinates (19,
4) is stored.

Then, the X coordinate counter 101 and the Y coordinate counter 201
The coordinates counted by (1) are further advanced to (10,3) (11,3) (12,3) (13,3).

Next, when the counted current coordinate becomes the coordinate (14,3), the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204
Outputs a match signal.

More specifically, when the current coordinate is (14,3),
The output “14” of the X coordinate counter 101 is
To the B input. On the other hand, the X coordinate FIFO memory 103
Output is the first stored “14”,
The signal is supplied to the A input of the X coordinate comparison circuit 104. Therefore, the A input and the B input of the X coordinate comparison circuit 104 match,
A match signal is output.

Similarly, the output “3” of the Y coordinate counter 201 is given to the B input of the Y coordinate comparison circuit 204. On the other hand, FIF for Y coordinate
The output of the O memory 203 is “3” stored first, and is supplied to the A input of the Y coordinate comparison circuit 204. Therefore, the A input and the B input of the Y coordinate comparison circuit 204 match, and the comparison circuit 204 outputs a match signal.

As a result, the output of the coordinate coincidence AND circuit 301 becomes active.

The output of the coordinate coincidence AND circuit 301 is the X-coordinate FIFO memory 1
The signal is fed back to the 03 and Y coordinate FIFO memory 203 and is given to each memory as a read signal RCK. Therefore, the first data of the X-coordinate FIFO memory 103 and the first data of the Y-coordinate FIFO memory 203 are discarded, and the next data “19” and “3”, that is, the coordinate values (19, 3) are output from each memory. Is set.

Further, since the output of the coordinate coincidence AND circuit 301 is given as a clock input to the shadow data generation circuit 302, the Q output of the shadow data generation circuit 302 is inverted from “0” to “1”.

Then, when the current coordinate becomes (19,3), similarly,
The output of the coordinate matching AND circuit 301 becomes active, and X
The read signal RCK is input to the coordinate FIFO memory 103 and the Y coordinate FIFO memory 203, and the output values of the memories 103 and 203 are (29, 3).
And the Q output of the shadow data generation circuit 302 is inverted from “1” to “0”.

 Hereinafter, the same processing is performed.

By the way, when the coordinate y = 3, that is, at the third line, the image update signal output from the line comparison circuit 602 is given to the Y-direction interpolation selection circuit 603 as described above.

The selection circuit 603 switches the connection state so that the signal from the shadow data generation circuit 302 becomes the output of the selection circuit 603 during the line period in which the image update signal is given.

Therefore, when the coordinate y = 3, data output from the shadow data generation circuit 302 is sequentially stored in the one-line FIFO buffer memory 604, and one line of shadow data is stored in the memory 604.

On the other hand, in the line comparison circuit 602, the line number FIF
When it is determined that the output of the O memory 601 does not match the output of the Y coordinate counter 201, in other words, the current coordinate y does not match the line number to which the shift amount Ky in the Y direction has been added. At times, no image update signal is output from the line comparison circuit 602.

At this time, the selection circuit 603 for Y-direction interpolation
The connection is switched so that the B input becomes an output. That is,
The connection is switched so that the output of the one-line FIFO buffer memory 604 is written into the buffer memory 604 again.

Since the clock CK is given to the one-line FIFO buffer memory 604 as the write signal WCK and the read signal RCK, the contents are sequentially shifted in synchronization with the clock CK.

Then, when the current coordinate is y = 10, the FIFO for the X coordinate is used.
10315,21,27,33,15,17,18,22,26,28,29,33,15,17,18,2 are stored in the memory 103 and the Y-coordinate FIFO memory 203, respectively.
2,26,28,29,33｝ ｛10,10,10,10,12,12,12,12,12,12,12,12,13,13,13,1
3,13,13,13,13｝ are stored.

When the current coordinate x = 29 on the tenth line where the current coordinate to be counted is y = 10, that is, when the current coordinate becomes (29,10), the image data D (29, 10) reaches a change point, but since this change point is outside the range defined by the X-direction range detection circuit 105, the AND circuit 403 remains in the non-active state, and the output of the change point extraction circuit 402 Becomes active, its active output cannot pass through the AND circuit 403, and the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 2
Write signal WCK is not applied to 03. Therefore, the X coordinate FIF
The O memory 103 and the Y coordinate FIFO memory 203 do not receive the output “39” of the X coordinate addition circuit 102 and the output “15” of the Y coordinate addition circuit 202, respectively.

As a result of the above-described processing being performed on the image data of FIG. 2, when the outputs of the one-line FIFO buffer memory 604 are arranged in chronological order, the image data shown in FIG. 13 is obtained.

The output of the one-line FIFO buffer memory 604 and the image data (original image) input to the image processing circuit 21E are:
Since the logical sum is obtained and synthesized in the logical sum circuit 306, the output of the image processing circuit 21F is as shown in FIG.

That is, image data obtained by superimposing the original image data of FIG. 2 and the shadow data of FIG. 13 is obtained as processed output image data.

In the circuit of FIG. 12, the shift amount Kx in the X direction output from the Kx generation circuit 106 is fixed at Kx = 10,
In addition to changing both the Ky in the direction in synchronization with the line synchronization signal Hsync, the shift amount Kx in the X direction may be changed in synchronization with the clock CK. When both the shift amount Kx in the X direction and the shift amount Ky in the Y direction are changed, the generated shadow data becomes an image deformed in both the X direction and the Y direction with respect to the original image data.

FIG. 15 shows an image processing circuit 21F to which the image processing circuit 21E of FIG. 12 is applied. A feature of the image processing circuit 21F shown in FIG. 15 is that a shadow image can be expressed in a halftone. For this purpose, the one-line FIFO buffer memory 60
Between the output of FIG. 4 and the OR circuit 306, a multi-level conversion circuit 303, a dither comparison circuit 304 and a dither matrix memory 305 are inserted.

The configurations and operations of the multi-level circuit 303, the dither comparison circuit 304, and the dither matrix memory 305 are the same as those of the circuit of FIG. 5 or FIG. 10 described above. Omitted.

According to the image processing circuit 21F shown in FIG. 15, since the shadow image is expressed in halftone, an image as shown in FIG. 16 is obtained as its output.

In each of the above embodiments, the X direction range detection circuit 105
If the image area to be shaded is specified by the Y-direction range detection circuit 205 and it is not necessary to specify the image area to be shadowed, these X-direction range detection circuits 105 and / or Y The direction range detection circuit 205 may be omitted.

When the shadowing range is not limited and the entire image is shadowed, the address value obtained by adding the shift amount of the shadowing to the image address at the end of the screen is larger than the maximum address of the screen. Since it becomes large, it is necessary to make room for that amount in the FIFO memory.

In the above-described embodiment, the digital copying machine has been described as an example. However, the digital image processing apparatus according to the present invention can be applied to a digital image forming apparatus other than the digital copying machine, It should be noted that it can also be used for devices.

<Effects of the Invention> According to the present invention, it is possible to perform various shadowing processes on an image with only a memory having a relatively small capacity as compared with a conventional device.

In particular, by using a small-capacity FIFO memory, a shadow image having the same contour as the original image can be formed with an arbitrary shift amount, or an original image can be formed with an arbitrary shift amount of a deformed shadow image. it can.

Therefore, according to the present invention, it is possible to provide a digital image processing apparatus capable of performing various image processing at low cost, in particular, various shadowing processing.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration example of a digital image processing circuit 21A according to one embodiment of the present invention. FIG. 2 is a diagram showing an example of original image data to be processed. FIG. 3 is a diagram showing an example of shadow data obtained as a result of the processing. FIG. 4 is a diagram showing an example of image data obtained as an output of the image processing circuit 21A. FIG. 5 is an image processing circuit according to another embodiment of the present invention.
21B is a block diagram illustrating a configuration example of 21B. FIG. 6 is a diagram showing an example of image data processed and output by the image processing circuit 21B. FIG. 7 is a block diagram showing a configuration example of an image processing circuit 21C according to still another embodiment of the present invention. FIG. 8 is a diagram showing shadow data as a result of processing by the image processing circuit 21C. FIG. 9 is a diagram showing image data output from the image processing circuit 21C. FIG. 10 is a block diagram showing a configuration example of an image processing circuit 21D according to still another embodiment of the present invention. FIG. 11 is a diagram illustrating an example of output image data of the image processing circuit 21D. FIG. 12 is a block diagram showing a configuration example of an image processing circuit 21E according to still another embodiment of the present invention. FIG. 13 is a diagram showing shadow data obtained as a result of processing by the image processing circuit 21E. FIG. 14 is a diagram illustrating data obtained as an output of the image processing circuit 21E. FIG. 15 is a block diagram showing an image processing circuit 21F according to still another embodiment of the present invention. FIG. 16 is a diagram illustrating an example of output image data obtained by the image processing circuit 21F. FIG. 17 is a schematic configuration diagram of an entire digital copying machine to which an image processing apparatus according to one embodiment of the present invention is applied. FIG. 18 is a block diagram showing a configuration of a part related to image processing in the digital copying machine according to this embodiment. FIG. 19 is a diagram for explaining the shadowing process. In the figure, 21, 21A, 21B, 21D, 21E, 21F ... image processing circuit, 101 ... X coordinate counter, 102 ... X coordinate addition circuit,
103: X-coordinate FIFO memory, 104: X-coordinate comparison circuit,
105: X direction range detection circuit, 201: Y coordinate counter,
202: Y coordinate addition circuit, 203: FIFO memory for Y coordinate,
204: Y coordinate comparison circuit 205: Y direction range detection circuit
301 ... coordinate coincidence AND circuit, 302 ... shadow data generation circuit, 306 ... OR circuit, 401 ... image data latch circuit, 402 ... change point extraction circuit, 403 ... AND circuit, 303
... Multi-value conversion circuit, 304 dither comparison circuit, 305 dither matrix memory, 106 Kx generation circuit, 206 Ky generation circuit, 601 FIFO memory for line number, 602 line comparison circuit , 603... Y-direction interpolation selection circuit, 604.
2 shows a line FIFO buffer memory.

Claims (12)

(57) [Claims] 1. A digital image processing apparatus for processing given digital image data, comprising: input means for sequentially inputting the digital image data in time series; Data change point detecting means for determining whether or not subsequent image data has changed, and deriving an output when a change has occurred; an address for sequentially assigning an address to image data input to the input means Assigning means, shifting amount setting means in which the shifting amount of the shadow image necessary for shadowing is set, and setting of the shifting amount to the current address assigned by the address assigning means each time there is an output of the data change point detecting means. Calculation storage means for obtaining a shadowing address to which a predetermined shift amount added to the means is added, and storing the shadowing address; A match signal output means for comparing the address given by the first address with the shadowing address stored in the operation storage means, and outputting a match signal when the two match, any one of a first level and a second level binary output The shadow data generating means for inverting the output level in response to the coincidence signal; and synthesizing the image data input to the input means and the shadow data derived from the shadow data generating means. A digital image processing apparatus, comprising: a synthesizing means for outputting a digital image. 2. The digital image processing apparatus according to claim 1, wherein the shadow data generating means further outputs at least one of the first level and the second level to the first level and the second level.
And an intermediate level signal output means for converting the output to an intermediate level between the two levels. 3. A digital image processing apparatus for processing given digital image data, comprising: input means for sequentially inputting the digital image data in chronological order; Data change point detecting means for determining whether or not subsequent image data has changed, and deriving an output when a change has occurred; an address for sequentially assigning an address to image data input to the input means Assigning means, a shift amount setting means in which a shift amount of a shadow image required for shadowing is set, a predetermined address is set, and activated when an address assigned by the address assigning means is within a set address range. Each time there is an output of the shadowing area specifying means for outputting a signal, and an output of the shadowing area specifying means and an output of the data change point detecting means, an address is inputted. A calculation address storage means for storing a shadow address obtained by adding a predetermined shift amount set in the shift amount setting means to the address at that time assigned by the assignment means, and the address assignment means assigns the shadow address. A coincidence signal output means for comparing the address with the shadowing address stored in the operation storage means and outputting a coincidence signal when the two coincide with each other; and constantly outputting either the first level or the second level binary output. Shadow data generating means for inverting an output level in response to the coincidence signal; and synthesizing and outputting image data input to the input means and shadow data derived from the shadow data generating means. A digital image processing apparatus, comprising: synthesizing means. 4. The digital image processing apparatus according to claim 3, wherein the shadow data generating means further outputs at least one of the first level and the second level to the first level and the second level.
And an intermediate level signal output means for converting the output to an intermediate level between the two levels. 5. A digital image processing apparatus for processing given digital image data, wherein the digital image data is two-dimensional data in which a plurality of line data composed of a plurality of pixels are arranged. Wherein each pixel is sequentially processed in synchronization with a reference clock, and each line data is sequentially processed in synchronization with a line synchronization signal, wherein the digital image data is sequentially input in pixel units in time series; A data change point detecting unit that determines whether a subsequent pixel has changed with respect to a preceding pixel input to the input unit, and derives an output when a change occurs. Address assigning means for assigning an address; outputting a shift amount of a shadow image required for shadowing; A shift amount in the line length direction, wherein the shift amount in the line length direction changes in synchronization with the reference clock and is reset to an initial value by the line synchronization signal. Every time there is an output from the change point detecting means, a shadow address is obtained by adding the current shift amount output from the shift amount output means to the current address given by the address assigning means, and the shadow address is stored. Operation signal storage means for comparing an address assigned by the address assignment means with a shadowing address stored in the operation storage means, and outputting a match signal when the two match. A shadow data generating means for constantly deriving one of a binary output of a second level and inverting an output level in response to the coincidence signal; And digital image processing apparatus characterized by comprising synthesizing means, for combining and outputting shadow data generated from the input image data and the shadow data generating means to the input means. 6. The digital image processing apparatus according to claim 5, wherein the shadow data generating means further outputs at least one of the first level and the second level to the first level and the second level.
And an intermediate level signal output means for converting the output to an intermediate level between the two levels. 7. The digital image processing apparatus according to claim 5, wherein the shift amount output by the shift amount output means further includes a shift amount in the line arrangement direction, and the shift amount in the line arrangement direction is different. The amount is a predetermined fixed amount. 8. The digital image processing apparatus according to claim 5, wherein the shift amount output by the shift amount output means further includes a shift amount in the line arrangement direction, and the shift amount in the line arrangement direction is different. The amount is adapted to change in proportion to the line synchronization signal. 9. A digital image processing apparatus for processing given digital image data, wherein the digital image data is constituted by a plurality of line data, each line data being synchronized with a line synchronizing signal. Input means for sequentially inputting the digital image data in chronological order, and determining whether subsequent image data has changed with respect to preceding image data input to the input means. Data change point detecting means for deriving an output when a change occurs, addressing means for sequentially assigning an address to image data inputted to the input means, and a shift amount of a shadow image required for shadowing. The shift amount includes at least the shift amount in the line arrangement direction, and the shift amount in the line arrangement direction is The shift amount output means, which is adapted to change in synchronization with the synchronization signal, is output from the shift amount output means to the current address given by the address assigning means each time there is an output from the data change point detecting means. An arithmetic storage unit for storing the shadowing address to which the shift amount has been added, an arithmetic storage unit for storing the shadowing address, and an address assigned by the address providing unit are compared with the shadowing address stored in the arithmetic storage unit. A coincidence signal output means for outputting a coincidence signal when a coincidence occurs, which always derives either a first level or a second level binary output, and inverts an output level in response to the coincidence signal Data generation means, line data storage means capable of storing one line of shadow data, and a shift amount in the line arrangement direction outputted from the shift amount output means. Determining means for determining whether or not it is necessary to repeatedly output shadow data.When determining that the determining means is necessary, the shadow data derived from the shadow data generating means is not stored in the line data storage means. Further, the shadow data already stored in the line data storage means is sequentially read out, and when the determination means determines that the shadow data is unnecessary, the shadow data stored in the line data storage means is sequentially read out and stored in the storage means. Storage control means for sequentially storing the shadow data derived from the shadow data generation means in the line data storage means and updating the storage content, and reading out the image data and line data storage means inputted to the input means And a synthesizing unit for synthesizing and outputting the shadow data to be output. 10. The digital image processing apparatus according to claim 9, wherein the shadow data generating means further outputs at least one of the first level and the second level to the first level and the second level.
And an intermediate level signal output means for converting the output to an intermediate level between the two levels. 11. The digital image processing apparatus according to claim 9, wherein the shift amount output by the shift amount output means further includes a shift amount in the line length direction. The shift amount is a predetermined fixed amount. 12. The digital image processing apparatus according to claim 9, wherein the line data is composed of a plurality of pixels, each of which is sequentially processed in synchronization with a reference clock, and wherein a shift amount is output. The shift amount output by the means further includes a shift amount in the line length direction, and the shift amount in the line length direction changes in proportion to the reference clock, and is changed by the line synchronization signal. It is characterized by being reset to an initial value.