JP3021018B2 - Digital image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus for digitally processing image data. In particular, the present invention relates to an image processing apparatus for a digital image forming apparatus such as a digital copying machine, a digital printer, and a digital facsimile.

<Prior Art> For example, taking an analog copier as an example, there has conventionally been known a copy machine in which a document image is shifted by a predetermined amount in the sub-scanning direction. In general, such image shifting is performed by changing the timing of feeding a sheet by a registration roller disposed in a sheet feeding path. Therefore, it has not been possible to shift only a part of the image on the document surface in the sub-scanning direction.

On the other hand, in recent digital copiers, since the read original image is digitally processed, it is possible to shift only a part of the original image in the sub-scanning direction. Exists.

However, in order to shift an image in a conventional digital copying machine, the image data in an arbitrary area is shifted after storing all the data for one screen of the original, so that a page memory is indispensable. there were.

<Problems to be Solved by the Invention> That is, in order to perform image shift processing in a conventional digital copying machine, a page memory is indispensable for storing image data for one screen, and the cost of the memory increases. There was a disadvantage.

Similarly, other digital image processing apparatuses have the disadvantage that a large-capacity memory is required to perform the image shift processing.

Therefore, an object of the present invention is to provide a digital image processing apparatus which can solve the disadvantages of the prior art and can shift an image without using a large-capacity memory.

<Means for Solving the Problems> The present invention is a digital image processing apparatus for processing given digital image data, wherein the digital image data is input to the input means and the input means sequentially. Data change point detection means to determine whether the subsequent image data has changed with respect to the input preceding image data, and to derive an output when a change occurs, to the image data input to the input means, Each time there is an output of an address assigning unit for sequentially assigning an address, a shift amount setting unit in which a shift amount necessary for image shift is set, and a data change point detecting unit, the address assigning unit assigns an address. A shift address obtained by adding a predetermined shift amount set in the shift amount setting means to the address is obtained,
Arithmetic storage means for storing the shift address, a coincidence signal output means for comparing an address assigned by the address assignment means with the shift address stored in the arithmetic storage means, and outputting a coincidence signal when they match. And a shift data generating means for constantly deriving either the first level or the second level binary output and inverting the output level in response to the coincidence signal. It is.

<Operation> According to the present invention, when a change point occurs in the input image data, the change point is detected by the data change point detecting means. Then, a change point address of the shifted image in which a predetermined shift amount is added to the address of the change point is calculated and stored. Then, when the address of the input image data matches the change point address of the calculated and stored shift image, a match signal is output, and the output level of the shift data generation means is inverted.
The shift data generating means derives a binary output, for example, an output of a white level or a black level, and the output is inverted at a shift data change point. Therefore, the output of the shift data generating means is data obtained by shifting the image data by a predetermined shift amount.

<Embodiment> An embodiment of the present invention will be described below by taking a digital copying machine as an example.

FIG. 4 is a schematic configuration diagram of an entire digital copying machine to which the image processing apparatus according to one embodiment of the present invention is applied.

The digital copying machine is provided with a contact glass 13 for setting a document 12 on an upper surface of a main body 11, and an openable / closable document cover 14 is provided thereon.

Above the inside of the main body 11, a light source 15 that is movable in the direction of arrow A1 along the lower surface of the contact glass 13 is provided. The light source 15 has a long cylindrical shape extending in a direction perpendicular to the plane of the drawing, and the reflected light of the document 12 certified by the light source 15 is transmitted to the CCD line image sensor 20 via mirrors 16, 17, 18 and a condensing lens 19. Given. Then, the document image is read by the image sensor 20.

The CCD line image sensor 20 is a longitudinal sensor extending in a direction perpendicular to the paper surface, and its length direction is the main scanning direction X, and reads image data line by line.

The document image data read by the CCD line image sensor 20 is provided to an image processing circuit 21 and subjected to image processing described later. Then, the output of the image processing circuit 21 is supplied to the laser diode 22 to cause the diode 22 to emit light.
The laser light output from the laser diode 22 is scanned by the polygon mirror 23 and applied to the photosensitive drum 25 via the mirror 24.

Known members such as a charger 26, a developing device 27, a transfer / separation charger 28, and a cleaner 29 are arranged around the photoconductor drum 25. An electrostatic latent image is formed on the surface of the photoconductor drum 25 by an electrophotographic method. Once formed, the latent image is developed into a toner image. Then, the toner image is taken from the paper cassette 30, and is transferred to the paper supplied to the photosensitive drum 25 at a timing adjusted by the registration roller 31. Then, the sheet on which the toner image has been transferred is conveyed by the conveying belt 32 and sent to the fixing device 33. In the fixing device 33, the toner image on the paper is fixed, and the copied paper on which the fixing is completed is discharged to the discharge tray.

FIG. 5 is a block diagram showing a configuration of a part related to image processing in the above-described digital copying machine. Original image data read by the CCD line image sensor 20 is amplified by an amplifier 41, converted from analog data to digital data by an A / D converter 42, and provided to the image processing circuit 21. Then, the output image data processed by the image processing circuit 21 is provided to the laser diode 22 to cause the laser diode 22 to emit light. Furthermore, the clock oscillator 46
And a line synchronization signal generation circuit 45. The reference clock CK output from the clock oscillator 46 is supplied to the timing generation circuit 44, the A / D converter 42, and the image processing circuit 21, and the line synchronization signal Hsync output from the line synchronization signal generation circuit 45 It is provided to the processing circuit 21 and the timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 is
The operation is performed in synchronization with the reference clock CK output from the CPU, and the operation is performed in synchronization with each line by the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. Similarly, the image processing circuit 21 operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is under the control of a CPU 47 for controlling the entire operation of the digital copying machine.

Next, a specific configuration example of the image processing circuit 21 shown in FIG. 5 will be described.

FIG. 1 is a block diagram showing a detailed configuration of the image processing circuit 21 according to one embodiment. First, this image processing circuit
Explaining each component included in 21 in block units,
It is as follows.

101... X coordinate counter This counter is a circuit for counting the reference clock CK supplied from the clock oscillator 46 (see FIG. 5) and calculating the coordinate x in the X direction which is the main scanning direction.

The X coordinate counter 101 includes a line synchronization signal generation circuit 45.
It is reset to 1 by the line synchronization signal Hsync given from FIG. Thus, for each line, the X coordinate counter 101 calculates a coordinate x from a predetermined start position.

102 X-coordinate addition circuit A circuit for adding a shift amount Kx (given as a B input) in the X direction to the coordinate x (given as an A input) calculated by the X-coordinate counter 101.

103... X-coordinate first-in first-out memory (X-coordinate FIFO memory) A memory for storing the coordinate value (x + Kx) added by the X-coordinate addition circuit 102.

Note that the stored coordinate value (x + Kx) is a value obtained by adding the shift amount Kx to the coordinate Xn of the change point of the image data in the X direction (Xn + Kx), that is, only the coordinate value of the change point of the shift data will be described later. Is controlled by the write signal WCK.

104: X coordinate comparison circuit Coordinate values (Xn + K) stored in the X coordinate FIFO memory 103
This is a circuit for comparing x) with the current coordinate x and outputting a match signal when they match.

105 X-direction range detection circuit A circuit for determining whether or not the coordinate x falls within a range set in a CPU 501 described later.

201: Y coordinate counter This counter counts the line synchronization signal Hsync supplied from the line synchronization signal generation circuit 45 (see FIG. 5) and calculates the coordinate y in the Y direction which is the sub-scanning direction, that is, the line number y. It is a circuit for performing.

The Y coordinate counter 201 is reset to 1 by a vertical synchronization signal Vsync which is a reading start signal for each page.

202... Y coordinate addition circuit A circuit for adding a shift amount Ky (given as a B input) in the Y direction to the coordinate y (given as an A input) calculated by the Y coordinate counter 201.

203... Y-coordinate first-in first-out memory (Y-coordinate FIFO memory) A memory for storing the coordinate value (y + Ky) added by the Y-coordinate addition circuit 202.

Note that the stored coordinate value (y + Ky) is a value (Yn + Ky) obtained by adding the shift amount Ky to the coordinate Yn of the change point of the image data in the Y direction, that is, only the coordinate value of the change point of the shift data, which will be described later. Is controlled by the write signal WCK.

204: Y coordinate comparison circuit Coordinate values (Yn + K) stored in Y coordinate FIFO memory 203
This is a circuit for comparing y) with the current coordinate y and outputting a match signal when they match.

205... Y-direction range detection circuit A circuit for determining whether or not the coordinate y falls within a range set in a CPU 501 described later.

301... Coordinate coincidence logical AND circuit This circuit is a circuit that performs logical AND of the coincidence signals of the X coordinate comparing circuit 104 and the Y coordinate comparing circuit 204.

The following processing is performed by the X coordinate comparison circuit 104, the Y coordinate comparison circuit 204, and the coordinate coincidence AND circuit 301.

That is, the current coordinate (x, y) is stored in the X coordinate FIFO memory 1
It is determined whether or not the shift data stored in the 03 and Y coordinate FIFO memory 203 has reached the change point coordinate value (Xn + Kx, Yn + Ky).

302... Shift data generation circuit In this example, this circuit is configured by a D flip-flop.

The signal output from the coordinate coincidence AND circuit 301 is a change point signal of the shift data. Therefore, in this flip-flop 302, the output signal is changed from the first level (for example, low level) to the second level (for example, high level) every clock by using the transition point signal as a clock input.
Or from the second level to the first level to output shift data.

The shift data generation circuit 302 is reset by the line synchronization signal Hsync, and the output is returned to the initial state for each line, that is, to the first level (low level) in this embodiment.

401 ... Image data latch circuit A circuit for sequentially latching the minimum unit of input image data (pixel) represented by a binary level of a high level or a low level in synchronization with a reference clock.

402... Change point extraction circuit This circuit outputs a signal when the input pixel changes from, for example, black to white (high level to low level) or white to black (low level to high level).

More specifically, the preceding pixel one clock before latched by the image data latch circuit 401 is compared with the current pixel, and if they do not match, the current pixel changes with respect to the preceding pixel. Therefore, it is a circuit for outputting a change point signal.

403 AND circuit In this image processing circuit, the change point signal output from the change point extraction circuit is stored in the X coordinate FIFO memory 103 and the Y coordinate F memory.
The write signal WCK of the IFO memory 203 is used, but if the write signal WCK is out of the predetermined range, the write signal WCK is prevented from being output by the AND circuit 403, and the write operation is prohibited. ing.

That is, the X direction range detection circuit 105 and Y
The direction range detection circuit 205 opens the gate only when the current coordinates (x, y) are within a predetermined range, and the change point signal passes through the AND circuit 403.

Next, the operation of the image processing circuit 21 of FIG. 1 will be described with reference to specific image data.

Now, consider the case where the data read by the CCD line image sensor 20 (see FIGS. 4 and 5) is the image data shown in FIG.

In FIG. 2, the X direction extending horizontally is the main scanning direction, and the Y direction extending vertically is the sub-scanning direction. In FIG. 2, one square represented by a small square is the minimum unit data,
That is, it is a pixel. Pixels in white cells are 0 (low level)
, The black square indicates that the pixel is 1 (high level).

The numerical values given along the upper side and the left side represent the X coordinate value and the Y coordinate value of each pixel, respectively.

It is assumed that the image shown in FIG. 2 is shifted by a shift amount Kx = 10 coordinates in the X direction and a shift amount Ky = 5 coordinates in the Y direction. The shift is performed by using coordinates (1 to 24) in the X direction, Y
It is assumed that the processing is performed on the image in the area of the direction coordinates (1 to 28).

Read by the CCD line image sensor 20, the amplification circuit 41
The image data amplified by the A / D converter 42 and converted into a digital signal by the A / D converter 42 is time-sequentially, pixel by pixel, D (1,1), D (2,1), D (3,1) ... D (1,2), D (2,2), D (3,2) ... D (1,3), D (2,3), D (3,3) ...:::::::: : And flows into the image processing circuit 21.

Here, D (x, y) indicates image data at coordinates (x, y), and this image data is a pixel,
It has a value of “0” or “1”.

The image processing circuit 21 shown in FIG. 1 has a line synchronization signal Hsync and a vertical synchronization signal Vsync just before image data is input.
Is reset by

Therefore, the image data latch circuit 401 has been reset, and its Q output is "0".

In addition, the first reference clock CK (hereinafter simply referred to as “clock
CK "), the change point extraction circuit 402
Is set to the Q output “0” of the image data latch circuit 401, and the B input is set to the first image data D
(1,1) is set. Therefore, A input data = B
Since the input data = 0, the output of the change point extraction circuit 402 is non-active.

At this point, both the X coordinate counter 101 and the Y coordinate counter 201 are still being reset to “1”.

Next, when the first clock CK is given from the clock oscillator 46 (see FIG. 5), the image data latch circuit 401 latches the image data D (1,1).

Therefore, immediately before the next clock CK is applied, the image data D (1,1) latched by the image data latch circuit 401 is set to the A input of the change point extraction circuit 402, and the image data D is input to the B input. (2,1) is set. Since these image data D (1,1) and D (2,1) are both "0" as shown in FIG. 2, the output of the change point extraction circuit 402 is non-active.

At this time, the X-coordinate counter 101 counts one clock CK to be “2”, and the second counter 201 has “1”.
Remains.

Similarly, every time the clock CK is applied, the image data D (x−1, y) is latched by the image data latch circuit 401, and the image data D (x−1, y) is changed by the change point extraction circuit 402.
It is determined whether (x, y) is a change point.

The first point of change in the image data D (x, y) is
D (4,2).

At this time, D (3,2) latched by the image data latch circuit 401 is set to the A input of the change point extraction circuit 402, and D (4,2) is set to the B input. here,
Since D (3,2) is “0” and D (4,2) is “1”, the output of the change point extraction circuit 402 becomes active.

At this time, the values of the X coordinate counter 101 and the Y coordinate counter 102 are "4" and "2", respectively.

Then, the X coordinate addition circuit 102 adds “4” given to the A input and “Kx = 10” given to the B input, and the A + B output becomes “14”. Also, the Y coordinate addition circuit 20
2 adds “2” given to the A input and “Ky = 5” given to the B input, and the A + B output becomes “7”.

Further, "4" is input to the C input of the X-direction range detection circuit 105.
Is determined to be within the range of “1” and “24” given from the CPU 501 to the A input and the B input of the X direction range detection circuit 105.

Also, since "2" is given to the C input of the Y direction range detection circuit 205, this is also determined to be within the range of "1" and "28" given to the A and B inputs of the same circuit 205.

For this reason, the outputs of the X-direction range detection circuit 105 and the Y-direction range detection circuit 205 are each “1”, and the output of the change point extraction circuit 402 passes through the AND circuit 403 to output the X-coordinate FIFO. The write signal WCK is given to the memory 103 and the Y-coordinate FIFO memory 203, the X-coordinate FIFO memory 103 takes in the output “14” of the X-coordinate addition circuit 102, and the Y-coordinate FIFO memory 203 outputs the Y-coordinate addition circuit 202. Of the output "7".

Since the next image data D (5,2) is not a change point,
The output of the change point extraction circuit 402 is non-active, and X
Write signal WCK is not supplied to coordinate FIFO memory 103 and Y coordinate FIFO memory 203.

When the process proceeds and the next change point arrives, that is, when the image data D (9, 2), the output of the change point extraction circuit 402 becomes active, as in the case of the image data D (4, 2). Then, the write signal WCK is supplied to the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203, and the outputs of the X coordinate addition circuit 102 and the Y coordinate addition circuit 202 are taken in, respectively.

In this way, the same is repeated sequentially, and only when the change point comes, the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 store the X-coordinate addition circuit 102 and the Y-coordinate addition circuit 202, respectively. Output is captured.

As a result, the X-coordinate FIFO memory 103 contains ｛14,19,29,34,15,19,29,33,15,20,28,33,15,20,28,3
3,15,21,27,33｝ will be stored. Also, in the Y-coordinate FIFO memory 203, ｛7,7,7,7,8,8,8,8,9,9,9,9,10,10,10,10,11,11,11 , 1
1,｝ are stored.

In other words, if the expression is changed, the coordinate values (14,7) (19,7) (29,7) (34,34) can be obtained by a pair of memories consisting of the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203. 7) (15,8)
(19,8) (29,8) (33,8) (15,9) (20,9) (28,9)
(33,9) (15,10) (20,10) (28,10) (33,10) (15,1
1) (21,11) (27,11) (33,11) are stored.

Then, when the counted current coordinate becomes (14, 7), a coincidence signal is output from the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204 as described below.

Specifically, the operation when coordinate y = line number = 7 will be described in order. X coordinate counter 101 and Y coordinate counter 2
According to 01, coordinates (1,7) (2,7) (3,7) (4,7) are counted, and a change point is reached at coordinates (5,7). When a change point is reached, the X coordinate adding circuit 102 and the Y coordinate adding circuit 202
The coordinate values output from are (15,12). Therefore, X
The coordinate values (15, 12) are stored in the coordinate FIFO memory 103 and the Y coordinate FIFO memory 203.

Further, an X coordinate counter 101 and a Y coordinate counter 201
The coordinates counted by (6,7) (7,7) (8,7) (9,7) (10,7) advance, and since the coordinate (11,7) is a change point, the X coordinate For FI
The FO memory 103 and the Y coordinate FIFO memory 203 store coordinate values (21, 12).

Then, the X coordinate counter 101 and the Y coordinate counter 201
The coordinates counted by (1) further advance to (12,7) (13,7) (14,7).

Here, when the counted current coordinates become the coordinates (14, 7), the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204
Outputs a match signal.

More specifically, the coordinate to be counted is (1
In the case of (4, 7), the output “14” of the X coordinate counter 101 is given to the B input of the X coordinate comparison circuit 104. On the other hand, F for X coordinate
The output of the IFO memory 103 is “14” stored first, and is supplied to the A input of the X coordinate comparison circuit 104. Therefore, the A input and the B input of the X coordinate comparison circuit 104 match, and a match signal is output.

Similarly, the output “7” of the Y coordinate counter 201 is Y
It is given to the B input of the coordinate comparison circuit 204. On the other hand, the output of the Y coordinate FIFO memory 203 is “7” stored first, and is supplied to the A input of the Y coordinate comparison circuit 204. Therefore, the A input and the B input of the Y coordinate comparison circuit 204 match, and the comparison circuit 204 outputs a match signal.

As a result, the output of the coordinate coincidence AND circuit 301 becomes active.

The output of the coordinate coincidence AND circuit 301 is the X-coordinate FIFO memory 1
The signal is fed back to the 03 and Y coordinate FIFO memory 203 and is given to each memory as a read signal RCK. Therefore, the first data of the X-coordinate FIFO memory 103 and the first data of the Y-coordinate FIFO memory 203 are discarded, and the next data "19" and "7", that is, the coordinate values (19, 7) are output to each memory. Is set.

Further, since the output of the coordinate coincidence AND circuit 301 is given as a clock input to the shift data generation circuit 302, the Q output of the shift data generation circuit 302 changes from “0” to “1”.

Thereafter, when the current coordinate to be counted becomes the coordinate (19, 7), the output of the coordinate coincidence logical AND circuit 301 is similarly activated, and the FIFO memory 103 for the X coordinate and the FIFO memory 203 for the Y coordinate are similarly activated. Read signal RCK is input and each memory 103, 20
The output of 3 changes to the coordinate value (29, 7), and the Q output of the shift data generation circuit 302 is inverted from “1” to “0”.

 Hereinafter, the same processing is performed.

When the coordinate y = 10, the X-coordinate FIFO
10315,20,28,33,15,21,27,33,15,21,27,33,15,17,18,2
2,26,28,29,33,15,17,18,22,26,28,29,33｝, 10,10,10,10,11,11,11,11,12,12,12,12 , 13,13,13,1
3,13,13,13,13,14,14,14,14,14,14,14,14 are stored.

When the coordinate y = 10, that is, the coordinate x = 29 on the tenth line, that is, when the current coordinate to be counted is (29,10), the image data D (29,10) reaches a change point. Since this change point is outside the range determined by the X-direction range detection circuit 105, the write signal WCK is supplied to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 as described below. X-coordinate FIFO memory 103 and Y
Each of the coordinate FIFO memories 203 includes an X-coordinate addition circuit 102.
And the output of the Y coordinate addition circuit 202 are not taken in.

Specifically, when the coordinates (29, 10) are reached,
Since the output data D (28,10) of the image data latch circuit 401 set to the A input of the change point extraction circuit 402 and the image data D (29,10) set to the B input are different, The output of the point extraction circuit 402 becomes active.

However, when the coordinate x = 29, the output of the X-direction range detection circuit 105 is “0”, and the AND circuit 403 is in a non-active state. I can't pass. Thus, the X coordinate FIF
Write signal WCK to O memory 103 and Y coordinate FIFO memory 203
Is not given, and the coordinate values (39, 14) are not accumulated.

As a result of performing the above-described processing on the image data of FIG. 2, the outputs of the shift data generation circuit 302 are arranged in time series as shown in FIG.

2 and 3, it can be seen that the original image has been shifted by the desired amount.

Note that it is of course possible to shift the image only in the X direction or only in the Y direction. For such a shift, the shift amount in the Y direction or the shift amount in the X direction may be set to “0”.

In the above embodiment, the image area to be shifted is specified by the X direction range detection circuit 105 and the Y direction range detection circuit 205. However, when it is not necessary to specify the image area to be shifted, X direction range detection circuit
The 105 and / or the Y-direction range detection circuit 205 may be omitted.

Note that when the image shift range is not limited and the shift processing is performed on the entire image, the address value obtained by adding the shift amount for the shift to the image address at the end of the screen is larger than the maximum address of the screen. Therefore, it is necessary to provide the FIFO memory with a margin for that.

In the above-described embodiment, the digital copying machine has been described as an example. However, the digital image processing apparatus according to the present invention can be applied to a digital image forming apparatus other than the digital copying machine, Note that it can also be used for devices.

<Effects of the Invention> According to the present invention, an image can be shifted with only a memory having a relatively small capacity as compared with a conventional device.

In particular, the original image can be shifted by an arbitrary shift amount by using a small-capacity FIFO memory. Further, only an image in an arbitrary area can be shifted.

Therefore, according to the present invention, it is possible to provide a digital image processing apparatus capable of performing various image processing at low cost, in particular, various shift processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a digital image processing circuit 21 according to one embodiment of the present invention. FIG. 2 is a diagram showing an example of current image data to be processed. FIG. 3 is a diagram showing an example of shift data obtained as a result of the processing. FIG. 4 is a schematic configuration diagram of an entire digital copying machine to which the image processing apparatus according to one embodiment of the present invention is applied. FIG. 5 is a block diagram showing a configuration of a part related to image processing in the digital copying machine according to this embodiment. In the figure, 21 ... image processing circuit, 101 ... X coordinate counter, 102 ... X coordinate adding circuit, 103 ... X coordinate FIFO memory,
104: X coordinate comparison circuit, 105: X direction range detection circuit, 201
.. Y coordinate counter, 202 Y coordinate adding circuit, 203 Y coordinate FIFO memory, 204 Y coordinate comparison circuit, 205 Y direction range detection circuit, 301 coordinate coincidence logical AND circuit, 302 shift data generation circuit, Reference numeral 401 denotes an image data latch circuit, 402 denotes a change point extraction circuit, and 403 denotes an AND circuit.

Claims (1)

(57) [Claims] 1. A digital image processing apparatus for processing given digital image data, comprising: input means for sequentially inputting the digital image data in time series; Data change point detecting means for determining whether or not subsequent image data has changed, and deriving an output when a change has occurred; an address for sequentially assigning an address to image data input to the input means Assigning means, shifting amount setting means in which a shifting amount necessary for image shift is set, and setting of the shifting amount setting means to the address assigned by the address assigning means each time there is an output of the data change point detecting means. The arithmetic storage means for obtaining the shift address to which the given predetermined shift amount is added, and storing the shift address, A coincidence signal output means for comparing the given address with the shift address stored in the operation storage means and outputting a coincidence signal when the two coincide with each other; and one of a first level and a second level binary output And a shift data generating means for inverting an output level in response to the coincidence signal.