JP3021027B2 - Digital image data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device for digitally processing image data, and more particularly to a digital image data processing device for a digital copying machine, a digital printer, and the like. More specifically, the present invention relates to a digital image data processing device capable of performing three-dimensional shadowing of an image.

<Prior Art> A digital copier will be described as an example. In a recent digital copier, as shown in FIG. 13, for example, an original image of a character "mita" displayed by a fine check is hatched. Some can output a copy with a shadow image.

In a conventional digital copying machine, in order to perform such a shadowing process, an arrow X indicates a main scanning direction which is a reading direction of a line sensor, and an arrow Y indicates a sub scanning direction which is a relative movement direction between a line sensor and a document. In the scanning direction, at least Y
A line memory for the shadow width in the direction (the shift amount of the shadow image in the Y direction), for example, a line memory for several tens of lines, is required. Alternatively, a page memory capable of storing all image data for one screen is required.

<Problems to be Solved by the Invention> However, when the storage capacity of the line memory is set to be large enough to store several tens of lines, or when a page memory is used, the cost of the memory increases, and There was a drawback that it became expensive.

Further, in the case where the image forming apparatus cannot display gradations, in an extreme case, when an image is displayed only in black or white, that is, when the image forming apparatus is a black or white binary output type image forming apparatus In the case where halftone expression cannot be performed,
The original image displayed by the detailed check in the figure and the shadow image displayed by hatching are both output as a true black image, and it is not possible to distinguish which part is the original image and which part is the shadow image. There is also a disadvantage that the obtained image is different from the original image.

Therefore, the present invention solves the above-mentioned drawbacks of the conventional apparatus, and enables data processing for three-dimensional shadowing using a one-line memory. Further, the obtained shadowed image can easily determine the original image. It is an object of the present invention to provide a digital image data processing device capable of generating a possible image.

<Means for Solving the Problems> The present invention relates to a digital image data processing apparatus, which extracts image contour data from given digital image data, and uses the image contour data as first data having a predetermined value. Output contour data extraction means,
One-line memory means capable of storing given digital image data, feedback means for feeding back the output of the one-line memory means to the input side of the one-line memory means, data provided in the feedback means and fed back A change processing means for generating a shadow image data by subtracting a predetermined value from the image data, obtaining a logical sum of the newly given digital image data and the shadow image data generated by the change processing means, and obtaining the obtained data. Means for providing the data to the one-line memory means, and the output data of the one-line memory means according to the data value of the first value of the predetermined value consisting of the original image data and the shadow image data or the predetermined value consisting of the background data. Output from the binarization processing means for binarizing the second data and the contour data extraction means; And synthesizing means for obtaining the output data synthesized and in a predetermined manner the output of the binarizing processing means and it is characterized in that it comprises a.

Further, according to the present invention, in the digital image data processing device, the synthesizing means includes an exclusive OR circuit.

<Operation> According to the present invention, shadow image data as feedback is created by giving a predetermined change to the digital image data for one line, and the shadow image data is newly given.
It is added to the digital image data for the line. As a result, the digital image data output from the one-line memory means becomes data composed of an original image component, a shadow image component, and a background component. The binarization processing means converts the output data of the one-line memory means into first density (for example, black) first data consisting of original image data and shadow image data or second density (for example white) consisting of background data. Binarization into two data.

On the other hand, in the contour data extracting means, image contour data is extracted from given digital image data, and the data is output as first data of a first density (for example, black).

Then, the output of the binarization processing means and the output of the contour data extraction means are combined in a predetermined manner, for example, an exclusive OR operation.

Therefore, since the outline data is further superimposed on the data in which the original image data and the shadow image data are completely integrated, it is possible to obtain an image to which the original image has been subjected to three-dimensional shadowing so that the original image can be easily identified.

<Embodiment> Hereinafter, an embodiment of the present invention will be described in detail using a digital copying machine as an example.

First, the principle of three-dimensional shadowing in the present invention will be described.

When a document image is read by a CCD line image sensor in a digital copying machine, the data read from the CCD line image sensor divides the document image into pixels in a two-dimensional array at each reading pitch of the image sensor (for example, 400 dots / inch). Is processed.

In other words, if the reading direction (length direction) of the CCD line image sensor is the main scanning direction X and the relative displacement direction between the CCD line image sensor and the document image is the sub-scanning direction Y, the reading is performed by the CCD line image sensor. The original image data to be obtained can be represented as a set of a two-dimensional array of (Xi, Yj) as shown in FIG.

The read data of the CCD line image sensor as shown in FIG. 1 is composed of one line ((X ₀ , Yj) to (Xm, Y
j): However, j is given to the processing circuit in a time series for every 0 to n).

 Next, a specific example will be described.

Consider the case where the original image shown in FIG. 2 is read by a CCD line image sensor. In FIG. 2, X indicates the main scanning direction, and Y indicates the sub-scanning direction. When the original image shown in FIG. 2 is read by the CCD line image sensor, it is recognized as, for example, an image of a large number of pixels as shown in FIG. In this case, the read output data of the CCD line image sensor is shown in FIG. 4 (Xi, Y
j) is a set of two-dimensional arrays.

In this case, the black data of the original image in FIG.
F "(hexadecimal notation), white data is read as" 00 "(hexadecimal notation). In other words, the original image shown in FIG. 2 is binary with" FF "and" 00 ". It can be said that it was made.

Next, when the data shown in FIG. 4 is output in chronological order from the CCD line image sensor, a processing procedure for processing this data to perform three-dimensional shadowing will be described.

(1) A line memory having a memory area for one line is prepared.

Here, a line memory having a memory area equal to the number of read pixels (the number of read pixels in the main scanning direction X) of the CCD line image sensor is prepared. For example, FIFO
(First in first out) memory or random access memory.

For convenience, it is assumed that the memory area of the line memory is numbered as (Z ₀ ) (Z ₁ )... (Zi)... (Zm) in comparison with the pixel number (Xi) of the CCD line image sensor. .

(2) Initialize all memory areas of the line memory to white data (00). That is, when expressed by an equation, Zi ← 00 (i = 0 to m).

(3) From the data in each memory area of the line memory,
A constant K (for example, K = 22h: where h is a code indicating that “22” is a hexadecimal number, the same applies to the following) is subtracted. This process is called process a.

In the case where the process a is performed, if the data in the memory area is white data (00), the data does not become less than that, so the data remains white data (00).

(4) Next, the data subjected to the processing a is shifted one by one in the 0 → m direction in the memory area. This shift process will be referred to as process b.

As a result of the processing b, the data in the memory area (Zm) is discarded, and the white data (00) is stored in the memory area (Z ₀ ).

(5) The data of the line memory that performed the process b and the CCD
The logical sum with the data of the first line (the line data shown in FIG. 4) given from the line image sensor is obtained, and the result is stored again in the line memory. This process is called process c.

The above processing a to processing c can be expressed by the following equation: Z _O ← (00) v (X _O , Y _O ) Zi ← (Z _i-1 −K) v (Xi, Y _O ) (where v: Symbol i = 1 meaning bitwise OR
To m).

(6) Output the contents of the line memory that has been subjected to the process c to the printer unit. In this case, the output is binarized according to the printer. This process is called process d.

(7) Each time one line of read data is supplied from the CCD line image sensor, the processes a to d described above are performed in synchronization with the read data, and until the output of the line data of Repeat until done.

If it is expressed by a mathematical formula, Z _O ← (00) v (X _O , Yj) Zi ← (Z _i-1 −K) v (Xi, Yj) (where, v: logical sum for each bit) Symbol i = 1
~ M, j = 1 ~ n) Zi → image output (where i = 0 ~ m).

FIG. 5A and FIG. 5A show, in chronological order, how data a to d are applied to the data shown in FIG.
FIG. 5B and FIG. 5C. The processing proceeds from FIG. 5A to FIG. 5B to FIG. 5C.

5A, 5B and 5C, 1-d,
Data marked with 2-d, 3-d, 4-d,..., 22-d is output to the printer unit, and when the data is put together, it becomes data in a two-dimensional array shown in FIG.

By processing d, the data shown in FIG. 6 is binarized into white data (00) indicating the background or black data (FF) indicating the original image or the shadow image, and is printed out.
An image with a three-dimensional shadow as shown in FIG. 7 is obtained.

 The above is the principle of three-dimensional shadowing in the present invention.

Next, a specific apparatus for realizing the above-described principle of three-dimensional shadowing will be described.

FIG. 8 is a schematic diagram of an entire configuration of a digital copying machine to which a digital image data processing device according to one embodiment of the present invention is applied.

The digital copying machine is provided with a contact glass 13 for setting a document 12 on an upper surface of a main body 11, and an openable / closable document cover 14 is provided thereon.

Above the inside of the main body 11, a light source 15 that is movable in the direction of arrow A1 along the lower surface of the contact glass 13 is provided. The light source 15 has a long cylindrical shape extending in a direction perpendicular to the plane of the drawing, and the reflected light of the document 12 illuminated by the light source 15 is transmitted to the CCD line image sensor 20 via mirrors 16, 17, 18 and a condenser lens 19. Given. Then, the original image is read by the image sensor 20.

The CCD line image sensor 20 is a sensor having a longitudinal shape extending in a direction perpendicular to the paper surface, and its length direction is the main scanning direction X.

The document image read by the CCD line image sensor 20 is provided from the image sensor 20 to an image processing circuit 21 and subjected to image processing described later. Then, the output of the image processing circuit 21 is supplied to the laser diode 22 to cause the laser diode 22 to emit light. The laser light output from the laser diode 22 is guided by the polygon mirror 23,
The light is supplied to the photosensitive drum 25 via 24.

Known members such as a charger 26, a developing device 27, a transfer / separation charger 28, and a cleaner 29 are arranged around the photosensitive drum 25, and an electrostatic latent image is formed on the surface of the photosensitive drum 25 by an electrophotographic method. The latent image is developed into a toner image. Then, the toner image is taken from the paper cassette 30, and is transferred to the paper supplied to the photosensitive drum 25 at a timing adjusted by the registration roller 31. Then, the sheet on which the toner image has been transferred is conveyed by the conveying belt 32 and sent to the fixing device 33. The toner image on the paper is fixed by the fixing device 33, and the copied paper on which the fixing is completed is discharged to the discharge tray.

FIG. 9 is a block diagram showing a configuration of a part related to image processing in the digital copying machine described above. The image data read by the CCD line image sensor 20 is supplied to the amplifier 41
, And is converted from analog data to digital data by the A / D converter 42 and supplied to the image processing circuit 21. Then, the output image data processed by the image processing circuit 21 is output to the laser diode 22 to cause the laser diode 22 to emit light.

Further, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is supplied to the timing generation circuit 44, the A / D converter 42, and the image processing circuit 21, and the line synchronization signal Hs output from the line synchronization signal generation circuit 45
ync is supplied to the image processing circuit 21 and the timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 is
The operation is performed in synchronization with the reference clock CK output from the CPU, and the operation is performed in synchronization with each line by the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. Similarly, the image processing circuit 21 operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is under the control of a CPU 47 for controlling the entire operation of the digital copying machine.

Next, a more detailed configuration of the image processing circuit 21 shown in FIG. 9 will be described.

FIG. 10 is a block diagram showing a circuit configuration of the image processing circuit 21. The image processing circuit 21 includes an input processing circuit 51 to which image data converted into digital data is provided, a contour extraction circuit 60 to which image data is similarly provided, and a logical sum circuit 52 to which an output of the input processing circuit 51 is provided. , A FIFO memory 53 to which the output of the OR circuit 52 is provided, and a FIFO memory 53
Output processing circuit 54 to which the output of
Circuit for synthesizing the output of the image and the output of the contour extraction circuit 60
61 and a subtraction circuit 55 to which the output of the FIFO memory 53 is provided. The output of the subtraction circuit 55 is a logical sum circuit.
The output of the input processing circuit 51 is ORed by the OR circuit 52. The output of the OR circuit 52 is
As described above, it is provided to the FIFO memory 53.

The FIFO memory 53 is a line memory having a memory area equal to the number of read pixels of the CCD line image sensor 20.

Further, a FIFO timing circuit 56 for controlling the FIFO memory 53 is provided. The clock CK output from the clock oscillator 46 described above is input to the input processing circuit 51,
The contour extraction circuit 60 is provided as an operation clock to the OR circuit 52, the output processing circuit 54, and the FIFO timing circuit 56.

The FIFO timing circuit 56 and the contour extraction circuit 60 are supplied with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45 described above.

Further, the image processing circuit 21 is provided with a control CPU 57, and the input processing circuit 51, the subtraction circuit 55, and the output processing circuit 54 are controlled by the control CPU 57.

Next, the operation of the circuit of FIG. 10 will be described with reference to the explanation of the principle of the three-dimensional shadowing.

By controlling the input processing circuit 51 by the control CPU 57, the memory area of the FIFO memory 53 is initialized to white data (00) (see the explanation of the principle of three-dimensional shadowing (2)).

Next, when the digital image data is given to the input processing circuit 51, the input processing circuit 51
The digital image data is binarized one dot at a time and supplied to the OR circuit 52.

On the other hand, the output of the FIFO memory 53 is given to the subtraction circuit 55,
The subtraction circuit 55 subtracts a predetermined constant K (for example, K = 22h) given by the control CPU 57 from the output of the memory 53. Therefore, the data after the subtraction is supplied to the OR circuit 52.

The OR circuit 52 performs an OR operation on the data supplied from the input processing circuit 51 and the data supplied from the subtraction circuit 55.

Then, in response to the next clock CK, the output of the OR circuit 52 is stored in the FIFO memory 53.

Through the above processing, the processing a, the processing b, and the processing c described on the principle of the stereoscopic shadowing are performed.

The data stored in the FIFO memory 53 is supplied to the output processing circuit 54 in a first-in first-out order. Then, in the output processing circuit 54, a process d of binarizing into first data (for example, black data) composed of original image data and shadow image data or second data (for example, white data) composed of background data is performed.

In parallel with the above processes a, b, c and d, the contour extraction circuit 60 performs a contour extraction process of the original image data.

The specific configuration of the contour extraction circuit 60 is described in, for example,
The configuration described in JP-A-59484 and the configuration described in JP-A-62-175888 may be used, and the detailed configuration of such a contour extraction circuit is already known, and a detailed description thereof will be omitted. I do.

The original image provided to the input processing circuit 51 in FIG.
In the case of the image shown in the figure, the three-dimensionally shaded image output from the output processing circuit 54 is as shown in FIG. 11B. On the other hand, when the image of FIG. 11A is given to the contour extraction circuit 60, the output image of the contour extraction circuit 60 becomes the image shown in FIG. 11C. Then, in the synthesizing circuit 21, for example, the exclusive OR of the image of FIG. 11B output from the output processing circuit 54 and the image of FIG. 11C output from the contour extraction circuit 60 is obtained, and the output image is Make the image shown in Figure 11D. That is, an image is obtained in which the outline of the original image data is bordered white and three-dimensionally shaded.

Therefore, an image can be obtained in which the boundary between the original image and the shadow image is clear, and the original image has been subjected to a new three-dimensional shadowing without being difficult to identify by the shadow image.

FIG. 12 is a block diagram showing a more specific configuration example of the circuit of FIG.

Referring to FIG. 12, the input processing circuit 51 of the image processing circuit 21 includes an image data latch circuit 511 that performs a latch operation in response to a clock CK, and binarized threshold data supplied from the control CPU 57. CPU to latch
It can be constituted by a data latch circuit 512 and an 8-bit comparison operation circuit 513. 8-bit comparison operation circuit 51
Reference numeral 3 compares the output of the image data latch circuit 511 and the output of the CPU data latch circuit 512, that is, the threshold value, to perform binarization processing.

The OR circuit 52 is, for example, an 8-bit OR circuit.
It can be configured by connecting a 521 and an 8-bit gate circuit 522 in series. The 8-bit gate circuit 522 is a FIFO
This is a circuit necessary to initialize the memory 53.

The subtraction circuit 55 includes, for example, an 8-bit addition circuit 551.
And the CPU data latch circuit 552. If the output data of the control CPU 57 is changed, the output of the latch circuit 552 is changed, so that the subtraction constant can be changed.

Further, the output processing circuit 54 includes an 8-bit comparison operation circuit 54.
1 and the CPU data latch circuit 542.

In the circuit shown in FIG. 12, the FIFO timing circuit 56 in FIG. 10 is shown integrated with the FIFO memory 53, but even in such a case, the FIFO timing circuit built in the FIFO memory 53 is used. Can change the processing timing.

Further, the synthesis circuit 61 is configured by an exclusive OR circuit. With this circuit, as described above, the exclusive OR of the data output from the 8-bit comparison operation circuit 541 and the data output from the contour extraction circuit 60 is obtained, and the background is white, the original image and the shadow are obtained. A composite image is obtained in which the image is black and the outline of the original image is white.

However, the synthesizing circuit 61 according to the present invention may be configured by a circuit other than the exclusive OR circuit.

 Next, a modified example of this embodiment will be described.

In the circuit in FIG. 10, the length of the solid shadow can be changed by changing the constant K to be subtracted in the process a in the subtraction circuit 55. The change of the constant K may be performed by the control CPU 57.

By setting the shift amount of shifting the data in the process b one by one to 2, 3, 4,... Or 0 other than “1”, the inclination of the three-dimensional shadow can be changed.

In this case, the FIFO timing circuit 56 as the data shift means is removed, or the FIFO timing circuit 56
Assuming that the data shift amount at “0” is “0”, shadowing occurs only in the sub-scanning direction. Conversely, a shadow approaching the main scanning direction X can be obtained by increasing the shift amount. FI
The change of the shift amount in the FO timing circuit 56 can be performed by the control CPU 57 although the connection line is omitted.

Further, in the description of the principle of three-dimensional shadowing, it has been described that data processing is performed for each line, but data processing may be performed for each pixel.

That is, the processes a to d described in the principle of the stereoscopic shadowing are performed for each pixel.

Further, in the above-described embodiment, an example in which the FIFO memory is used as the one-line memory has been described, but a random access memory may be used instead of the FIFO memory.

<Effects of the Invention> Since the present invention is configured as described above, it is possible to perform a stereoscopic shadowing process by using a storage unit having a memory area of one line with a small memory capacity, In the shaded image, the original image can be clearly recognized.

Further, since the present invention can be constituted by a storage means having a small capacity of one line memory area and an outline extracting means, it can be applied to a small and inexpensive image forming apparatus.

[Brief description of the drawings]

FIG. 1 is a diagram showing document image data read by a CCD line image sensor as a set of two-dimensional arrays. FIG. 2 is a diagram illustrating an example of a document image read by a CCD line image sensor. FIG. 3 is a diagram showing an image recognized by the CCD line image sensor when the original image of FIG. 2 is read by the CCD line image sensor. FIG. 4 is a diagram showing read output data of a CCD line image sensor corresponding to the image of FIG. FIGS. 5A, 5B, and 5C are diagrams showing, in chronological order, the manner in which processing a to processing d is performed on the data shown in FIG. FIG. 6 shows 1-d, FIG. 5A, FIG. 5B and FIG.
It is the figure which expressed the data to which 2-d, ..., 22-d was attached by a two-dimensional array. FIG. 7 is a diagram showing an image shaded three-dimensionally based on the data shown in FIG. FIG. 8 is a schematic diagram of an entire configuration of a digital copying machine to which a digital image data processing device according to one embodiment of the present invention is applied. FIG. 9 is a block diagram showing a configuration of a part related to image processing in the digital copying machine. FIG. 10 is a block diagram showing a configuration of the image processing circuit. FIG. 11A is an example of an original image provided to the input processing circuit 51 and the contour extraction circuit 60 of the circuit of FIG. 10, and FIG. FIG. 11C is an example of an image, and FIG.
FIG. 11D is a diagram showing an example of an image output from the synthesizing circuit 61 in FIG. FIG. 12 is a block diagram showing a more specific configuration example of the circuit of FIG. FIG. 13 is a diagram for explaining three-dimensional shadowing in a conventional digital copying machine. In the figure, 20 ... CCD line image sensor, 43 ...
Image processing unit, 45: Line synchronization signal generation circuit, 46: Clock oscillator, 51: Input processing circuit, 52: OR circuit, 53: FIFO memory, 54: Output processing circuit, 55: Subtraction Circuit, 56... FIFO timing circuit, 60... Contour extraction circuit, 61...

Claims (2)

(57) [Claims] 1. An outline data extracting means for extracting image outline data from given digital image data and outputting the image outline data as first data having a predetermined value, and capable of storing given digital image data. Line memory means, feedback means for feeding back the output of the one-line memory means to the input side of the one-line memory means, provided in the feedback means, and subtracting a predetermined value from the fed-back data to produce shadow image data Change processing means for generating, arithmetic means for calculating a logical sum of newly given digital image data and shadow image data generated by the change processing means, and providing the obtained data to one line memory means, one line The output data of the memory means is converted into the original image data and Binarization processing means for binarizing first data of a predetermined value consisting of shadow image data or second data of a predetermined value consisting of background data; output of the contour data extraction means and output of the binary processing means A digital image data processing apparatus comprising: synthesizing means for synthesizing in a predetermined manner to obtain output data. 2. The digital image data processing device according to claim 1, wherein said synthesizing means includes an exclusive OR circuit.