JP2922629B2 - Digital image data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device for digitally processing image data, and more particularly to a digital image data processing device for a digital copying machine, a digital printer, and the like. More specifically, the present invention relates to a digital image data processing device capable of giving a three-dimensional shadow to an image.

<Prior Art> For example, taking a digital copying machine as an example,
Some recent digital copiers, when copying the original image shown in FIG. 16A, can give a three-dimensional shadow to the copy image as shown in FIG. 16B.

In a digital copying machine, to perform such three-dimensional shadowing, an arrow X indicates a main scanning direction which is a reading direction of a line sensor, and an arrow Y indicates a sub-scanning direction which is a relative moving direction of a line sensor and a document. Then, it is necessary to provide a memory having a capacity corresponding to the width of the shadow in the sub-scanning direction Y, for example, a line memory for 40 lines.

This is because, for one-line document image data read by the line sensor, data for the width of the shadow had to be held for shadowing.

<Problems to be Solved by the Invention> As described above, in order to perform three-dimensional shadowing with a conventional digital copying machine, a line memory capable of storing multiple lines is required to store shadow data in the sub-scanning direction Y. However, there is a disadvantage that the cost of the line memory is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital image data processing apparatus capable of solving such a drawback and performing data processing for necessary stereoscopic shadowing using a one-line memory.

<Means for Solving the Problems> The present invention relates to a digital image data processing apparatus, and more specifically, a one-line memory means capable of storing given digital image data, and an output of the one-line memory means. Feedback means for feeding back to the input side of the memory means, provided in the feedback means, a change processing means for subtracting a predetermined value corresponding to the data value from the data to be fed back to generate shadow image data, and A calculating means for calculating a logical sum of the newly given digital image data and the shadow image data generated by the change processing means, and providing the obtained data to the one-line memory means. .

Further, according to the present invention, in the digital image data processing apparatus, the change processing means includes a subtraction value storage means in which a subtraction value corresponding to the data value is stored, and a difference between the data value and the subtraction value stored in the subtraction value storage means. And a subtraction processing unit for subtracting the data fed back based on the relationship.

Still further, according to the present invention, in the digital image data processing apparatus, the change processing means includes a predetermined arithmetic processing means, and sets a function (dependent variable) having a predetermined relationship with the independent variable using the data to be fed back as an independent variable. It is output as shadow image data.

<Operation> According to the present invention, shadow image data as feedback data is created by changing a data value by subtracting a predetermined value according to a data value from digital image data for one line, It is added to the newly provided digital image data for one line. As a result, the digital image data output from the one-line memory means becomes data composed of an original image component, a shadow image component, and a background component.

If the subtraction value is changed in accordance with the image data value, a shadow image having a gradation whose density gradually changes as the distance from the original image changes is obtained.

<Embodiment> Hereinafter, an embodiment of the present invention will be described in detail using a digital copying machine as an example.

Principle of three-dimensional shadowing When an original image is read by a CCD line image sensor in a digital copying machine, data read from the CCD line image sensor is converted into a two-dimensional image at an image sensor reading pitch (for example, 400 dots / inch). It is divided into pixels in the array and processed.

In other words, if the reading direction (length direction) of the CCD line image sensor is the main scanning direction X and the relative displacement direction between the CCD line image sensor and the document image is the sub-scanning direction Y, the reading is performed by the CCD line image sensor. The original image data to be obtained can be represented as a set of a two-dimensional array of (Xi, Yj) as shown in FIG.

The read data of the CCD line image sensor as shown in FIG. 1 is composed of one line ((X ₀ , Yj) to (Xm, Y
j): However, j is given to the processing circuit in a time series for every 0 to n).

 Next, a specific example will be described.

Consider the case where the original image shown in FIG. 2 is read by a CCD line image sensor. In FIG. 2, X indicates the main scanning direction, and Y indicates the sub-scanning direction. When the original image shown in FIG. 2 is read by the CCD line image sensor, it is recognized as, for example, an image of a large number of pixels as shown in FIG. In this case, the read output data of the CCD line image sensor is shown in FIG. 4 (Xi, Y
j) is a set of two-dimensional arrays.

In this case, the black data of the original image in FIG.
F "(hexadecimal notation), white data is read as" 00 "(hexadecimal notation). In other words, the original image shown in FIG. 2 is binary with" FF "and" 00 ". It can be said that it was made.

Next, when the data shown in FIG. 4 is output in chronological order from the CCD line image sensor, a processing procedure for processing this data to perform three-dimensional shadowing will be described.

(1) A line memory having a memory area for one line is prepared.

Here, a line memory having a memory area equal to the number of read pixels (the number of read pixels in the main scanning direction X) of the CCD line image sensor is prepared. For example, FIFO
(First in first out) memory or random access memory.

For convenience, it is assumed that the memory area of the line memory is numbered as (Z ₀ ) (Z ₁ )... (Zi)... (Zm) in comparison with the pixel number (Xi) of the CCD line image sensor. .

(2) Initialize all memory areas of the line memory to white data (00). That is, when expressed by an equation, Zi ← 00 (i = 0 to m).

(3) A constant K (for example, K = 22h: where h is a code indicating that "22" is represented in hexadecimal, the same applies to the following) is subtracted from the data in each memory area of the line memory. This process is called process a.

In the case where the process a is performed, if the data in the memory area is white data (00), the data does not become less than that, so the data remains white data (00).

(4) Next, the data subjected to the processing a is shifted one by one in the 0 → m direction in the memory area. This shift process will be referred to as process b.

As a result of the processing b, the data in the memory area (Zm) is discarded, and the white data (00) is stored in the memory area (Z ₀ ).

(5) The logical sum of the data of the line memory that has performed the processing b and the data of the first line (line data shown in FIG. 4) given from the CCD line image sensor is obtained, and the result is stored in the line memory. Store again. This process is called process c.

The above processing a~ process c, if represented by the _{formula, Z o ← (00) v} (X o, Y o) Zi ← (Z i-1 -K) v (Xi, Y o) ( where, v: The symbol i = 1 to m, which means a logical sum for each bit.

(6) The contents of the line memory subjected to the process c are output to the printer unit. In this case, adjust the output to match the printer.
Value conversion etc. This process is called process d.

(7) Each time one line of read data is supplied from the CCD line image sensor, the processes a to d described above are performed in synchronism with the read data. Repeat until done.

By displaying it in the _{formula, Z o ← (00) v} (X o, Yj) Zi ← (Z i-1 -K) v (Xi, Yj) ( However, v: means the logical sum of each bit Symbol i = 1 to m, j = 1 to n) Zi → image output (where i = 0 to m).

FIG. 5A and FIG. 5A show, in chronological order, how data a to d are applied to the data shown in FIG.
FIG. 5B and FIG. 5C. The processing proceeds from FIG. 5A to FIG. 5B to FIG. 5C.

5A, 5B and 5C, 1-d,
Data marked with 2-d, 3-d, 4-d,..., 22-d is output to the printer unit, and when the data is put together, it becomes data in a two-dimensional array shown in FIG.

By the process d, the data shown in FIG. 6 is ternarized into white data (00), black data (FF) or intermediate data,
When it is printed out, an image with a three-dimensional shadow as shown in FIG. 7 is obtained.

The above is the basic principle of three-dimensional shadowing in the present invention.

According to the present invention, in the process a in the basic principle, when subtracting the data of the line memory, the subtraction value is determined in advance according to the data value instead of subtracting the constant K. When the value changes, the subtraction value changes accordingly. As a result, the data subjected to the processing a is a value whose value changes nonlinearly.

Further, in the present invention, in the process d, the output from the line memory is multi-valued so that an image with a shadow image having a non-linear gradation change is obtained.

Specific Apparatus Next, a specific apparatus for realizing the above-described principle of three-dimensional shadowing will be described.

FIG. 8 is a schematic diagram of an entire configuration of a digital copying machine to which a digital image data processing device according to one embodiment of the present invention is applied.

The digital copying machine is provided with a contact glass 13 for setting a document 12 on an upper surface of a main body 11, and an openable / closable document cover 14 is provided thereon.

Above the inside of the main body 11, a light source 15 that is movable in the direction of arrow A1 along the lower surface of the contact glass 13 is provided. The light source 15 has a long cylindrical shape extending in a direction perpendicular to the plane of the drawing, and the reflected light of the document 12 illuminated by the light source 15 is transmitted to the CCD line image sensor 20 via mirrors 16, 17, 18 and a condenser lens 19. Given. Then, the original image is read by the image sensor 20.

The CCD line image sensor 20 is a sensor having a longitudinal shape extending in a direction perpendicular to the paper surface, and its length direction is the main scanning direction X.

The document image read by the CCD line image sensor 20 is provided from the image sensor 20 to an image processing circuit 21 and subjected to image processing described later. Then, the output of the image processing circuit 21 is supplied to the laser diode 22 to cause the laser diode 22 to emit light. The laser light output from the laser diode 22 is guided by the polygon mirror 23,
The light is supplied to the photosensitive drum 25 via 24.

Known members such as a charger 26, a developing device 27, a transfer / separation charger 28, and a cleaner 29 are arranged around the photoconductor drum 25. An electrostatic latent image is formed on the surface of the photoconductor drum 25 by an electrophotographic method. Once formed, the latent image is developed into a toner image. Then, the toner image is taken from the paper cassette 30, and is transferred to the paper supplied to the photosensitive drum 25 at a timing adjusted by the registration roller 31. Then, the sheet on which the toner image has been transferred is conveyed by the conveying belt 32 and sent to the fixing device 33. The toner image on the paper is fixed by the fixing device 33, and the copied paper on which the fixing is completed is discharged to the discharge tray.

FIG. 9 is a block diagram showing a configuration of a part related to image processing in the digital copying machine described above. The image data read by the CCD line image sensor 20 is supplied to the amplifier 41
, And is converted from analog data to digital data by the A / D converter 42 and supplied to the image processing circuit 21. Then, the output image data processed by the image processing circuit 21 is output to the laser diode 22 to cause the laser diode 22 to emit light.

Further, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is supplied to the timing generation circuit 44, the A / D converter 42, and the image processing circuit 21, and the line synchronization signal Hs output from the line synchronization signal generation circuit 45
ync is supplied to the image processing circuit 21 and the timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 is
The operation is performed in synchronization with the reference clock CK output from the CPU, and the operation is performed in synchronization with each line by the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. Similarly, the image processing circuit 21 operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is under the control of a CPU 47 for controlling the entire operation of the digital copying machine.

Next, a more detailed configuration of the image processing circuit 21 shown in FIG. 9 will be described.

FIG. 10 is a block diagram showing a circuit configuration of the image processing circuit 21. The image processing circuit 21 includes an input processing circuit 51 to which digital image data is provided, an OR circuit 52 to which an output of the input processing circuit 51 is provided, a FIFO memory 53 to which an output of the OR circuit 52 is provided, and a FIFO memory. An output processing circuit 54 to which an output of 53 is provided and a subtraction circuit 55 to which an output of the FIFO memory 53 is provided are included. Then, the output of the subtraction circuit 55 is given to the OR circuit 52, and the OR of the output of the input processing circuit 51 is obtained by the OR circuit 52. The output of the OR circuit 52 is provided to the FIFO memory 53 as described above.

The FIFO memory 53 is a line memory having a memory area equal to the number of read pixels of the CCD line image sensor 20.

Further, a FIFO timing circuit 56 for controlling the FIFO memory 53 is provided. The clock CK output from the clock oscillator 46 described above is input to the input processing circuit 51,
The operation clock is supplied to the OR circuit 52, the output processing circuit 54, and the FIFO timing circuit 56.

The FIFO timing circuit 56 is supplied with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45 described above.

Further, the image processing circuit 21 is provided with a control CPU 57, and the control CPU 57
5 and the output processing circuit 54 are controlled.

FIG. 11 is a block diagram showing a specific configuration example of the circuit of FIG. The image processing circuit shown in FIG. 11 is a circuit to which image data represented by 8 bits is given and which can process the image data as it is represented by 8 bits.

For this purpose, an 8-bit image data latch circuit 511 is provided as an input processing circuit.

Further, as an OR circuit, an 8-bit comparison operation circuit 523 for selecting the maximum value, and an image data latch circuit 511
An 8-bit gate circuit 524 for selectively passing data supplied from the memory, an 8-bit gate circuit 525 for selectively passing subtraction result data, and a FIFO memory 53.
And an 8-bit gate circuit 526 necessary for initializing.

Further, the subtraction circuit 55 has a RAM 553 for generating a subtraction value function.
And a CPU data latch circuit 554 for holding data to be written to the RAM 553 as a subtraction value function, and a CPU data latch circuit 556 for holding initial operation data.

By setting the initial setting data in the RAM 553 for generating the subtraction value function to predetermined data, a value to be subtracted from the data output from the FIFO memory 53 can be set at an arbitrary ratio according to the output data value of the FIFO memory 53, for example. The density of the shadow image output from the RAM 553 can be changed at a desired ratio.

Next, the initialization processing of the RAM 553 will be specifically described. It is assumed that the data written to the RAM 553 by the initialization is the data shown in FIG. In the case of initialization, the control signal from the control CPU 57 is set high, for example, so that the output of the CPU data latch circuit 556 is selected by the 8-bit data selector 555. That is, CPU
The output of the data latch circuit 556 is an 8-bit data selector 5
55 to the address input Add of the RAM 553. The RAM 553 is set to the write mode by, for example, a high control signal.

In this state, the control CPU 57 sequentially outputs the data shown in FIG. As a result, the data “FF”, “FE”, “FD”,... Displayed in the column of “ADDR” in FIG. 12 are sequentially output from the CPU data latch circuit 556,
It is given to the address input Add of the RAM 553. In synchronization with this processing, the CPU data latch circuit 554 outputs data “FE”, “FD”, “FC” displayed in the “DATA” column of FIG.
Are sequentially output, and the data is output to the data input Din of the RAM 553.
Given to. As a result, the data shown in FIG. 12, that is, the data value displayed in the column of “DATA” is written in correspondence with the address displayed in the column of “ADDR” in FIG.

When the above initialization is completed, the control signal from the control CPU 57 becomes low, for example, and the 8-bit data selector 55 outputs the data output from the FIFO memory 53.
It is set to be applied to the address input Add of the RAM 553, and the RAM 553 is set to the read mode.

Therefore, the data output from the FIFO memory 53 is
The data is supplied to the address input Add of the RAM 553 via the 8-bit data selector 555. The RAM 553 outputs predetermined data from the data output Dout according to the value of the data supplied to the address input Add. The relationship between the given data and the output data is as shown in FIG. Therefore,
In the data conversion in the RAM 553, the data output from the FIFO memory 53 is subtracted, so that halftone image data having different densities according to the data values can be obtained.

The relationship between the density change of the shadow image thus obtained and the distance from the original image is shown in a graph in FIG. From FIG. 13, it can be seen that the density of the shadow image gradually decreases near the original image, and the density rapidly decreases as the distance from the original image increases.

Also, by changing the data to be written to the RAM 553 by the initialization, the way of changing the density of the shadow image can be changed.

For example, the data to be written to RAM553
With the data shown in the figure, the relationship between the density change of the shadow image and the distance from the original image is as shown in FIG. That is, it is possible to provide a shadow image in which the density rapidly decreases in the vicinity of the original image, and changes gradually when the density further increases.

Further, instead of the density of the shadow image changing non-linearly according to the distance from the original image, the density of the shadow image can be changed linearly in proportion to the distance from the original image. This may be a method of setting the relationship between address and data by the RAM 553 as in this embodiment,
As in the case of the principle of three-dimensional shadowing described above, it can also be performed by a simple circuit configuration in which a constant value is always subtracted from the original image.

Further, in this embodiment, the correspondence between the address and the data is set by initialization using the RAM 553, but the ROM storing the predetermined address and the corresponding data is stored in the ROM of the RAM 553 in FIG. It may be used instead. When a ROM is used, the 8-bit data selector 555, the CPU data latch circuit 554, and the CPU latch circuit 556 can be omitted from the circuit shown in FIG.

Furthermore, in the above-described embodiment, a storage unit called a RAM 553 is used, and a correspondence between an address and data is set in this storage in advance, and a FIFO is stored based on the set relation.
Although the shadow image data is generated by subtracting a predetermined value from the data output from the memory 53, the shadow image data can be generated without using a storage unit such as the RAM 553. That is, the subtraction circuit 55 is, for example, f (x) = x−
An arithmetic circuit for performing an operation (a / x) is provided so that output data from the FIFO memory 53 is given as an independent variable x, and a function (dependent variable) f (x) to be output is shadow image data. You may. Then, by changing variously the arithmetic equations performed by the arithmetic circuit, different shadow image data can be obtained.

As described above, the subtraction circuit 55 can be constituted by an arithmetic processing circuit.

Now, returning to FIG. 11, the configuration of another circuit will be briefly described as follows. In this circuit, a programmable shift circuit 56 for shifting read timing is used.
A FIFO timing circuit is constituted by 1 and a CPU data latch circuit 562 for holding the shift amount. By changing the shift amount of the shift circuit 561, it is possible to change the shift amount of the process b described in the principle of three-dimensional shadowing.

The output processing circuit in FIG. 11 includes an 8-bit comparison operation circuit 5410 for performing dither processing, a RAM 5411 for holding a dither matrix, and an 8-bit comparison circuit for selecting whether to initialize or execute the dither matrix. The data selector 5412 counts the line synchronization signal Hsync and the RAM 54
A counter 5413 for generating the upper address of 11; a counter 5414 for counting the clock CK to generate the lower address of the RAM 5411; a CPU data latch circuit 5415 for holding the initialization address of the RAM 5411;
CPU data latch circuit 5 for holding initialization data of
416.

Note that, for example, when displaying an image on a CRT display or the like, the output processing circuit may be omitted.

Description of Modified Examples Next, various modified examples of this embodiment will be described.

By setting the shift amount by which the data in the process b is shifted by one to 2, 3, 4,..., Or 0 other than “1”, the inclination with the three-dimensional shadow can be changed.

In this case, if the data shift means is omitted or the data shift amount in the data shift means is set to "0", the shadowing occurs only in the sub-scanning direction. Conversely, a shadow approaching the main scanning direction X can be obtained by increasing the shift amount. This change in the shift amount is also shown in FIGS.
Although connection lines are omitted in the figure, the control CP
If the shift amount is changed by the control CPU 57, for example, the CPU in the circuit of FIG. 11 can be used.
The value of the data latch circuit 562 changes.

Further, in the description of the principle of three-dimensional shadowing, it has been described that data processing is performed for each line, but data processing may be performed for each pixel.

That is, the processes a to d described in the principle of the stereoscopic shadowing are performed for each pixel.

Further, the present invention can be applied to a full-color image forming apparatus, for example, a full-color copying machine, to colorize a gradation with a three-dimensional shadow.

Further, in the above-described embodiment, an example in which the FIFO memory is used as the one-line memory has been described, but a random access memory may be used instead of the FIFO memory.

<Effect of the Invention> Since the present invention is configured as described above, a digital image data processing apparatus capable of performing processing such as three-dimensional shadowing by using storage means having a one-line memory area is provided. Can be provided.

In particular, according to the present invention, the shadow image added to the image data can be a shadow with gradation,
Moreover, the gradation can be made as desired.

Further, according to the present invention, since processing can be performed by using a storage unit having a memory area of one line, a small and inexpensive image forming apparatus can be provided by applying the present invention to an image processing apparatus. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing document image data read by a CCD line image sensor as a set of two-dimensional arrays. FIG. 2 is a diagram illustrating an example of a document image read by a CCD line image sensor. FIG. 3 is a diagram showing an image recognized by the CCD line image sensor when the original image of FIG. 2 is read by the CCD line image sensor. FIG. 4 is a diagram showing read output data of a CCD line image sensor corresponding to the image of FIG. FIGS. 5A, 5B, and 5C are diagrams showing, in chronological order, the manner in which processing a to processing d is performed on the data shown in FIG. FIG. 6 shows 1-d, FIG. 5A, FIG. 5B and FIG.
It is the figure which expressed the data to which 2-d, ..., 22-d was attached by a two-dimensional array. FIG. 7 is a diagram showing an image shaded three-dimensionally based on the data shown in FIG. FIG. 8 is a schematic diagram of an entire configuration of a digital copying machine to which a digital image data processing device according to one embodiment of the present invention is applied. FIG. 9 is a block diagram showing a configuration of a part related to image processing in the digital copying machine. FIG. 10 is a block diagram showing a configuration of the image processing circuit. FIG. 11 is a block diagram showing a more specific configuration example of the circuit of FIG. FIG. 12 is a diagram showing an example of data to be written into the RAM 553. FIG. 13 is a diagram showing the relationship between the change in the density of the shadow image and the distance from the original image when the data shown in FIG. 12 is set. FIG. 14 is a diagram showing another example of data to be written into the RAM 553. FIG. 15 is a diagram showing the relationship between the change in the density of the shadow image and the distance from the original image when the data shown in FIG. 14 is set. FIGS. 16A and 16B are diagrams for explaining three-dimensional shadowing in a conventional digital copying machine, in which FIG. 16A shows a document image, and FIG. It is. In the figure, 20 ... CCD line image sensor, 43 ...
Image processing unit, 45: Line synchronization signal generation circuit, 46: Clock oscillator, 51: Input processing circuit, 52: OR circuit, 53: FIFO memory, 54: Output processing circuit, 55: Subtraction Circuit, 56... FIFO timing circuit.

Claims (3)

(57) [Claims] 1. One-line memory means capable of storing given digital image data, feedback means for feeding back the output of the one-line memory means to the input side of the one-line memory means, and feedback means; Change processing means for subtracting a predetermined value corresponding to the data value from the fed-back data to generate shadow image data; digital image data newly provided; and shadow image data generated by the change processing means And a calculating means for calculating a logical sum of the data and the obtained data to a one-line memory means. 2. The digital image data processing device according to claim 1, wherein the change processing means includes a subtraction value storage means storing a subtraction value corresponding to the data value.
And subtraction processing means for subtracting the data fed back based on the relationship between the data value stored in the subtraction value storage means and the subtraction value. 3. The digital image data processing device according to claim 1, wherein the change processing means includes a predetermined arithmetic processing means, wherein the function is a function having a predetermined relationship with the independent variable using feedback data as an independent variable. (Variable) is output as shadow image data.