JPH03174871A - Digital picture data processor - Google Patents

Abstract

PURPOSE:To attain miniaturization and to reduce the cost by using a storage means having a 1-line memory area to apply processing such as stereoscopic shade. CONSTITUTION:A picture data read by a CCD line image sensor 40 is amplified by an amplifier 41 and converted into a digital data from an analog data by an A/D converter 42 and the resulting data is given to a picture processing section 43. Then the 1-line memory is used to give a predetermined change to a digital picture data by one line thereby generating a feedback data and the result is fed to a digital picture data by one line given newly. Thus, the given digital picture data receives a feedback data by one line each and desired processing such as stereoscopic shade is implemented, Thus, the small sized and inexpensive picture forming device is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a processing device for digitally processing image data, and particularly to a digital image data processing device for a digital copying machine, a digital printer, or the like. More particularly, the present invention relates to a digital image data processing apparatus capable of adding stereoscopic shadows to images.

<Prior Art> Taking a digital copying machine as an example, a recent digital copying machine has the following problems when copying the original image shown in FIG. 14(A), as shown in FIG. 14(B).
There are devices that can add three-dimensional shadows to copy images.

In order to perform such stereoscopic shadowing in a digital copying machine, arrow Therefore, it is necessary to provide a memory with a capacity corresponding to the width of the shadow in the sub-scanning direction Y, for example, a line memory for 40 lines.

This is because, in order to add a shadow to one line of document image data read by a line sensor, it is necessary to hold data for the width of the shadow.

<Problems to be Solved by the Invention> As described above, in order to perform stereoscopic shadow casting with a conventional digital copying machine, a line memory capable of storing multiple lines is required to store shadow data in the sub-scanning direction Y. This has the drawback of increasing the cost of line memory.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital image data processing device capable of eliminating such drawbacks and performing necessary data processing using a one-line memory.

<Means for Solving the Problems> The present invention relates to a digital image data processing device, and includes a one-line memory means capable of storing one line of given digital image data, and an output of the one-line memory means. feedback means for feeding back p to the input side of the one-line memory means; change processing means provided in the feedback means for generating shadow image data by subtracting a value determined by p from the fed-back data; an arithmetic means for calculating the logical sum of one line of digital image data given to the image data and the shadow image data generated by the change processing means, and supplying the obtained data to the one line memory means; and an output of the one line memory means. The present invention is characterized in that it includes an output means for binarizing and outputting data consisting of an image component and a background component, and data consisting of a shadow component.

Further, the digital image data processing device further includes:
The present invention is characterized in that it includes timing shift means that is provided in the feedback means and shifts the output timing of data to be fed back.

According to the present invention, feedback data is created by applying a predetermined change to one line of digital image data, and is added to one line of newly provided digital image data.

Therefore, feedback data is added line by line to the provided digital image data, and desired processing such as stereoscopic shadowing is performed.

Embodiment of the Invention An embodiment of the present invention will be described below in detail using a digital copying machine as an example.

Principle of stereoscopic shading When an original image is read by a CCD line image sensor in a digital copying machine, the data read from the CCD line image sensor is a two-dimensional image of the original image at each reading pitch of the image sensor (for example, 400 dots/inch). It is divided into array pixels and processed.

In other words, if the reading direction (lengthwise direction) of the CCD line image sensor is the main scanning direction X, and the relative displacement direction between the CCD line image sensor and the document image is the sub-scanning direction Y, then As shown in FIG. 1, the original image data that is
It can be represented as a set of dimensional arrays.

The data read by the CCD line image sensor as shown in FIG. 1 is one line ((X,.

Y j) ~(Xm, Y j): However, j is 0 to n
) is given to the processing circuit in a special sequence.

Next, a specific example will be given and explained.

The original image shown in Fig. 2 is transferred to the CCD line image sensor 2.
Consider the case of reading with 0. In FIG. 2, X indicates the main scanning direction and Y indicates the sub-scanning direction. When the original image shown in FIG. 2 is read by the CCD line image sensor 20, it is recognized as an image of a large number of pixel sets as shown in FIG. 3, for example. In this case, the read output data of the CCD line image sensor 20 is a set of two-dimensional arrays (Xi, Yj) shown in FIG.

In this case, the black data of the original image in FIG.
” (hexadecimal representation), and the white data is read as “00” (hexadecimal representation). To put it another way, the original image shown in Figure 2 is converted to 2Wi with “FF” and “00”. It can be said that

Next, when the data shown in FIG. 4 is output sequentially from the CCD line image sensor 20, a processing procedure for processing this data to perform stereoscopic shadow projection will be explained.

(1) Prepare a line memory having a memory area for one line.

Here, this line memory is prepared to have a memory area equal in number to the number of read pixels of the CCD line image sensor 20 (the number of read pixels in the main scanning direction X). for example,
F I F O (first in rlrstout
) memory or random access memory.

For convenience, the memory area of the line memory is 1! of the CCD line image sensor 20. ! In contrast to the i-A number (Xi), it is assumed that the numbers are (Zo)(Z+) .=(Zi)-(Zm).

(2) Initialize all memory areas of the line memory to white data (00). That is, if expressed as a formula, Z i ←00 (i −0 to m).

(3) From the data in each memory area of the line memory,
Constant K (for example, K-22h: where h is "22"
Subtract the number n indicating that is expressed in hexadecimal (the same applies below). This process will be referred to as process a.

Note that when processing a is performed, if the data in the memory area is white data (00), the data will not become lower than that, so the data will remain as white data (00).

(4) Next, the data subjected to process a is shifted one by one in the 0→m direction within the memory area. This shift processing will be called processing.

As a result of processing, the data in the memory area (Zm) is discarded, and the own data (00) is stored in the memory area (Zo).
) is stored.

(5) Processed line memory data and CC
A logical sum is calculated with the first line data (line data indicated by ■ in FIG. 4) provided from the D-line image sensor 20, and the result is stored in the line memory again.

This process will be referred to as process C.

If the above processing a to processing C are expressed as a formula, Zo ” (
00) v (Xo, Yo)Z 1-(Z i
-, -K) v (X t, yo ) (where ■=symbols i-1 to m meaning bitwise logical sum).

(6) Output the contents of the line memory subjected to process C to the printer section. In this case, the output is binarized or the like according to the printer. This process will be referred to as process d.

(7) Processes a to d explained above are performed in synchronization with each line of read data from the CCD line image sensor 20 until the output of line data from ■ to @ is completed, i.e. Repeat until sub-scanning is completed.

If we express it mathematically, we get Zo ” (00)V (Xo , Yj)Z 16-(
Z i−+−K) v (X t, Y j) (However,
V: Symbols i-1 to m meaning bitwise logical sum.

j-1~n) Zi-both image output (However, i -0~m) becomes.

Further, FIGS. 5A, 5B, and 5C show how the data shown in FIG. 4 is subjected to processes a to d in chronological order. The process proceeds from FIG. 5A to FIG. 5B to FIG. 5C.

1 in FIGS. 5A, 5B, and 5C.
The data marked with -d, 2-d, 3-d, 4-d..., 22-d is output to the printer section, and when it is put together, it becomes the two-dimensional array data shown in Figure 6. .

Then, through process d, the sixth. Among the data shown in the figure, data excluding white data (00) is black data (FF).
By binarizing the image into intermediate data and printing it out, an image with a three-dimensional shadow as shown in FIG. 7 is obtained.

Also, the black data (FF) was inverted to white data (00), and the intermediate data (other than FF and OO) was converted to black data (FF), while the own data (00) was left as is. Binarization, in other words, the background component, which is the own data (00), and the image component, which is the black data (F F), are both the own data (00), and the intermediate data, which is the shadow component, is the black data (FF). If the image is binarized as follows and printed out, an output image as shown in FIG. 8 with a white three-dimensional shadow cast is obtained.

The above is the principle of stereoscopic shadowing in this invention.

Specific Apparatus Next, a specific apparatus for realizing the above-mentioned principle of stereoscopic shading will be explained.

FIG. 9 shows the overall configuration of a digital copying machine to which a digital image data processing apparatus according to an embodiment of the present invention is applied. E is the main figure.

The digital copying machine is equipped with a contact glass 13 for setting a document 12 on the top surface of a main body 11, and a document cover 14 with an opening/closing opening is provided above the contact glass 13.

A light source 15 is provided inside and above the main body 11 and is movable along the lower surface of the contact glass 13 in the direction of arrow A1. The light source 15 has a cylindrical shape extending perpendicularly to the paper surface, and the light source 15 illuminates the original 12 with the light R15.
The reflected light is reflected by mirrors 16, 17, 18 and condenser lens 1.
The signal is applied to the CCD line image sensor 20 through one. Then, the image sensor 20 reads the original image.

The CCD line image sensor 20 is a longitudinal sensor extending perpendicularly to the paper surface, and its length direction is the main scanning direction X.

The original image read by the CCD line image sensor 20 is sent from the image sensor 20 to an image processing circuit 21, where it is subjected to image processing to be described later. The output of the image processing circuit 21 is then applied to the laser diode 22, causing the laser diode 22 to emit light. laser diode 2
The laser beam outputted from 2 is guided by a polygon mirror 23 and applied to a photosensitive drum 25 via a mirror 24.

Known members such as a charging charger 26, a developing device 27, a transfer 1 separation charger 28, and a cleaner 29 are arranged around the photoreceptor drum 25, and an electrostatic latent image is formed on the surface of the photoreceptor drum 25 by an electrophotographic method. The latent image is formed and the latent image is developed into a toner image.

Then, the toner image is taken in from the paper cassette 30 and transferred onto the paper applied to the photosensitive drum 25 with the timing adjusted by the registration rollers 31 . and,
The paper onto which the toner image has been transferred is transported by a transport belt 32 and sent to a fixing device 33. The toner image on the paper is fixed by the fixing device 33, and the copied paper on which the fixing has been completed is discharged to the discharge tray 34.

FIG. 10 is a block diagram showing the configuration of image processing related parts in the digital copying machine described above. Image data read by the CCD line image sensor 20 is amplified by an amplifier 41, converted from analog data to digital data by an A/D converter 42, and provided to the image processing circuit 21. The output image data processed by the image processing circuit 21 is output to the laser diode 22, causing the laser diode 22 to emit light.

Further, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is generated by the timing generation circuit 44,
Line synchronization signal Hsync, which is applied to A/D converter 42 and image processing circuit 21 and output from line synchronization signal generation circuit 45, is applied to image processing circuit 21 and timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing of the CCD line image sensor 20 and the output timing of both image data. That is, the CCD line image sensor 20 operates in synchronization with the reference clock CK output from the clock oscillator 46, and synchronizes each line with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. perform an action. The image processing circuit 21 similarly operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is placed under the control of a CPU 47 for controlling the overall operation of the digital copying machine.

Next, a more detailed configuration of the image processing circuit 21 shown in FIG. 10 will be explained.

FIG. 11 is a block diagram showing the circuit configuration of the image processing circuit 21. As shown in FIG. The image processing circuit 21 includes an input 21ift conversion circuit 51 to which image data converted into digital data is applied, a sum circuit 52 to which the output of the input binarization circuit 51 is applied, and an output of the logical sum circuit 52. given F
It includes an IFO memory 53, an output binarization circuit 54 to which the output of the FIFO memory 53 is applied, and a subtraction circuit 55 to which the output of the FIFO memory 53 is applied. The output of the subtraction circuit 55 is then given to the OR circuit 52, where it is ORed with the output of the manual binarization circuit 51. The output of the OR circuit 52 is applied to the FIFO memory 53 as described above.

The FIFO memory 53 is a CCD line image sensor 2
It is a line memory that stores a memory area equal to the number of pixels to be read and I, iJ.

Further, a FIFO timing circuit 56 for controlling the FIFO memory 53 is provided. The clock CK outputted from the clock oscillator 46 described above is transmitted to the manual binarization circuit 51, the OR circuit 52, and the output binarization circuit 5.
4 and FIFO timing circuit 56 as an operating clock.

The FIFO timing circuit 56 also receives a line synchronization signal H output from the line synchronization signal generation circuit 45 described above.
sync is given.

Furthermore, the image processing circuit 21 includes a control CPU 57.
The control CPU 57 controls the manual binarization circuit 51, the subtraction circuit 55, and the output binarization circuit 54.

Next, the operation of the circuit shown in FIG. 11 will be explained with reference to the previous explanation of the principle of stereoscopic shading.

By controlling the input binarization circuit 51 by the control CPU 57, the memory area of the FIFO memory 53 is initialized to white data (00) (see explanation (2) of the principle of stereoscopic shading). When the data is given to the input binarization circuit 51, the manual binarization circuit 51 converts the digital image data into 1 bit based on the clock CK.
It binarizes each dot and supplies it to the OR circuit 52.

On the other hand, the output of the FIFO memory 53 is given to the subtraction circuit 55, and in the subtraction circuit 55, the control CPU 5
A predetermined constant K given by 7 (for example −
22h) is subtracted from the output of the memory 53. Therefore, the data after the subtraction is provided to the OR circuit 52.

The OR circuit 52 performs the logical OR of the data provided from the manual binarization circuit 51 and the data provided from the subtraction circuit 55.

Then, in response to the next clock CK, the OR circuit 52
The output is sent to the FIFO memory 53.

By the above processing, processing a explained in the principle of stereoscopic shadowing is
1 processing and processing C are performed.

The data stored in the FIFO memory 53 is given to the output binarization circuit 54 in a first-in, first-out order, and in this large embodiment, it is binarized into background data, original data, and shadow data, and is printed out. The data is given to the laser diode 22 as data. That is, process d is performed.

FIG. 12 is a block diagram showing a more specific example of the configuration of the circuit shown in FIG. 11.

Next, the circuit shown in FIG. 12 will be explained.

The human-powered binarization circuit 51 of the image processing circuit 21 has a clock C.
Image data latch circuit 5 that performs a latch operation in response to K
11, a CPU data latch circuit 512 for latching the binarized threshold data given from the control CPU 57, and an 8-bit comparison calculation circuit 513. The 8-bit comparison calculation circuit 513 compares the output of the image data latch circuit 511 and the output of the CPU data latch circuit 512, that is, a threshold value, and performs binarization processing.

Further, the OR circuit 52 can be configured by, for example, an 8-bit OR circuit 521 and an 8-bit gate circuit 522 connected in series. 8-bit gate circuit 522
is a path necessary to initialize the FIFO memory 1.

Further, the subtraction circuit 55 is, for example, an 8-bit addition circuit 55.
1 and a CPU data latch circuit 552. If the output data of the control CPU 57 is changed, the output of the latch circuit 552 is changed, so that the subtraction constant can be changed.

Furthermore, the output binarization circuit 54 has a shadow data selection RAM 5.
41, a shadow data setting latch circuit 542, a shadow data address selection circuit 543, and a shadow data address setting latch circuit 544. The operation of these circuits will be briefly explained as follows.

By initialization, predetermined data is written into the shadow data selection RAM 541. This is done by setting the control signal from the control CPU 57 to high so that the eight outputs of the shadow data address selection circuit 543 become the Q output, and sequentially rFF'J from the shadow data address setting latch circuit 544.
rFEJ... "FO" rEFJ... rolJ r
The data ooJ is output, and the data is used as the Q output of the shadow data address selection circuit 543 to select the shadow data R.
Give it to the address input of AM541. In addition, in synchronization with this process, rOJ is output from the shadow data setting latch circuit 542.
rlJ..."1""1"...rlJ rOJ
This data is applied to the data input of the shadow data selection RAM 541.

The shadow data selection RAM 541 is controlled by the control CPU 57.
Since the control signal from the RAM 541 is I\I, it is in the write mode, so the RAM 541 contains rFFJ.
→ “0”, “FE” → “1”, ... “01” → “1”
”, “00”, “0”, and so on, addresses and their corresponding data are stored one by one.

The above initialization processing is performed. And control C
The control signal from the PU 57 goes low, and the shadow data address selection port 543 is set so that its A output becomes the Q output. In addition, the shadow data selection RAM 541
In this case, data is read out according to the address input.

Therefore, when data is output from the FIFO memory 53 and the data is rFFJ, the shadow data selection RA
1-bit data of "0" is output from M541. Furthermore, when the data rFEJ to "01" is given to the RAM 541 from the FIFO memory 53, 1-bit data "1" is output from the shadow data selection RAM 541 in response. Furthermore, “00” is written from the FIFO memory 53.
When the data is given to the RAM 541, the shadow data selection RAM 541 outputs 1-bit data of "0".

In this way, when the data output from the FIFO memory 53 is the black data (FF) and the own data (OO), the shadow data selection RAM 541 outputs 1-bit data of "0", and the FIFO memory 53 outputs the above-mentioned data. When intermediate data other than (other than FF and OO) is output,
Data conversion is performed so that 1-bit data of "1" is output from the shadow data selection RAM 541.

Therefore, data such as that shown in FIG. 8 is obtained in which the image is outlined and shaded.

In the circuit shown in FIG. 12, the FIFO timing low path 56 (see FIG. 11) is integrated into the FIFO memory 53.

FIG. 13 is a circuit diagram showing a modification of the circuit shown in FIG. 12. A feature of the circuit shown in FIG. 13 is that a shadow data selection ROM 545 is provided in place of the shadow data selection RAM 541 in the circuit shown in FIG. This shadow data selection ROM 545 includes rFFJ→“0”, rF
EJ → "1", ... "01" → "1", "00" →
Addresses and corresponding data, such as "0", are stored. Such shadow data selection ROM5
45, the data cannot be rewritten, but the shadow data setting latch circuit 542, the shadow data address selection circuit 543, and the shadow data address setting latch circuit 545 as shown in FIG. 12 described above can be omitted. I can do it.

Description of variants Next, various modifications of this embodiment will be explained.

In process a in the subtraction circuit 55 in FIG. 10, by changing the constant K for subtraction, the length of the three-dimensional shadow can be changed. The constant may be changed by the control CPU 57.

Furthermore, by setting the shift amount by which the data in the processing step is shifted by 1 to 2, 3, 4, .

In this case, if the data shift means is removed or the data shift amount in the data shift means is set to "0", shadowing will occur only in the sub-scanning direction.Conversely, by increasing the shift amount, shadowing will occur in the main scanning direction. You can make the shadow approach direction X.You can also change this shift amount using control C.
This can be done by PU'57.

Furthermore, in process a, the subtraction value K may not be a constant, but may be a value that depends on the data value to be subtracted.

In other words, K that has a specific relationship with the data value Zi to be subtracted
It may also be a subtraction value given by a function (Zl).

In this way, when adding a gradation to stereoscopic shadowing, the gradation can be varied. For example, rather than having the gradation change sequentially according to the length of the shadow, it is possible to change the change in the gradation.

Furthermore, the OR circuit 52 may be replaced with a circuit that performs a maximum value selection operation.

If you do that, human data will not be binary data,
Even in the case of multivalued data, stereoscopic shadowing can be performed.

Furthermore, in the explanation of the principle of stereoscopic shading, it has been explained that data processing is performed line by line, but data processing may be performed pixel by pixel.

That is, processes a to d described in the section on the principle of stereoscopic shadowing are performed for each pixel.

Further, the present invention can also be used in a full-color image forming apparatus, such as a full-color copying machine, to colorize a gradation with a three-dimensional shadow.

Further, in the above embodiment, an example was shown in which a FIFO memory was used as the one-line memory, but a random access memory may be used instead of the FIFO memory.

<Effects of the Invention> Since the present invention is configured as described above, there is provided a digital image data processing device that can perform processing such as stereoscopic shadowing by using a storage means that stores one line of memory area. can be provided.

Further, according to the present invention, processing can be performed by using the memory f6 stages having a memory area of one line, so by applying the present invention to an image processing device, it is possible to provide a small and inexpensive image forming device. be able to.

[Brief explanation of drawings]

FIG. 1 is a diagram showing document image data read by a CCD line image sensor as a set of two-dimensional arrays. FIG. 2 shows an example of an original image read by a CCD line image sensor. FIG. 3 is a diagram showing an image recognized by the CCD line image sensor when the original image shown in FIG. 2 is read by the CCD line image sensor. FIG. 4 is a diagram showing read output data of the CCD line image sensor corresponding to the image in FIG. 3. FIGS. 5A, 5B, and 5C are diagrams chronologically showing how processes a to d are applied to the data shown in FIG. 4. FIG. 6 is a two-dimensional array of data labeled 1-d, 2-d, . . . , 22-d in FIGS. 5A, 5B, and 5C. FIG. 7 is a diagram showing an image with three-dimensional shading based on the data shown in FIG. FIG. 8 is a diagram showing another example of an image with a three-dimensional shadow. FIG. 9 is a schematic diagram of the overall configuration of a digital copying machine to which a digital double-image data processing apparatus according to an embodiment of the present invention is applied. FIG. 10 is a block diagram showing the configuration of image processing related parts in the digital copying machine. FIG. 11 is a block diagram showing the configuration of the image processing circuit. FIG. 12 is a block diagram showing a more specific example of the configuration of the circuit shown in FIG. 11. FIG. 13 is a circuit showing a modification of the circuit shown in FIG. 12. FIG. 14 is a diagram for explaining stereoscopic shadowing in a conventional digital copying machine, in which (A) is an original image, (B)
2 is a diagram showing a copy image when a document image is copied with a three-dimensional shadow; FIG. In the figure, 20... CCD line image sensor,
43... Image processing section, 45... 1 line synchronization signal generation circuit, 46... 1 dot clock oscillator, 51...
・Manual binary conversion circuit, 52...OR circuit, 53...
FIFO memory, 54...output 21iff conversion circuit, 5
5 shows a subtraction circuit, and 56 shows a FIFO timing circuit.

Claims (1)

[Scope of Claims] 1. 1-line memory means capable of storing one line of digital image data given; feedback means for feeding back the output of the 1-line memory means to the input side of the 1-line memory means; , a change processing means provided in the feedback means for generating shadow image data by subtracting a predetermined value from the fed-back data; A calculation means calculates the logical sum with the shadow image data obtained and supplies the obtained data to the one-line memory means, and the output of the one-line memory means is divided into data consisting of the image component and background component and data consisting of the shadow component. A digital image data processing device comprising: output means for binarizing and outputting the digital image data. 2. The digital image data processing device according to claim 1 is further characterized in that it further includes timing shift means provided in the feedback means for shifting the output timing of the data to be fed back.