JPH03174872A - Digital picture data processor - Google Patents

Abstract

PURPOSE:To attain miniaturization and to reduce the cost by using a storage means having a memory area for one line to apply processing such as stereoscopic shading. CONSTITUTION:A picture data read by a CCD line image sensor 40 is amplified by an amplifier 41 and converted into a digital data from an analog data by an A/D converter 42 and the converted signal is fed to a picture processing section 43. A one-line memory is used to subtract a prescribed value from a digital picture data by one line and fed to the digital picture data by one line given newly. When a prescribed value to be subtracted is varied, a shade data is changed. Since the storage means having the memory area by one line is used for the processing in this way, the small sized and inexpensive picture forming device is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Use> The present invention relates to a processing device for digitally processing image data, and particularly to a digital image data processing device for a digital copying machine, a digital printer, or the like. More particularly, the present invention relates to a digital image data processing apparatus capable of adding stereoscopic shadows to images.

<Prior Art> Taking a digital copying machine as an example, a recent digital copying machine has the following problems when copying the original image shown in FIG. 14(A), as shown in FIG. 14(B).
There is something that can add 3D shadows to copy images! :do.

In order to perform such stereoscopic shadowing in a digital copying machine, arrow Therefore, it is necessary to provide a memory with a capacity corresponding to the width of the shadow in the sub-scanning direction Y, for example, a line memory for 40 lines.

This is because, in order to add a shadow to one line of document image data read by a line sensor, it is necessary to hold data for the width of the shadow.

<Problems to be Solved by the Invention> As described above, in order to perform stereoscopic shadow casting with a conventional digital copying machine, a line memory capable of storing multiple lines is required to store shadow data in the sub-scanning direction Y. This has the drawback of increasing the cost of line memory.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital image data processing device capable of eliminating such drawbacks and performing necessary data processing using a one-line memory.

<Means for Solving the Problems> The present invention provides a one-line memory means for inputting and storing one line of given digital image data;
a feedback means for feeding back the output data of the one line memory means to the one line memory means; a subtraction means provided in the feedback means for subtracting a predetermined value from the output data of the one line memory means to be fed back; a changing means for changing a predetermined value to be subtracted by the means; and a changing means for changing a predetermined value to be subtracted by the means;
calculation means for calculating the digital image data for a line and the feedback data changed by the data change processing means and inputting the result to the one-line memory means;
It is characterized by including.

Further, the digital image processing device of the present invention further includes a unit provided in the feedback means and configured to provide feedback.
The device is characterized in that it includes timing shift means for shifting the output timing of the output data of the line memory means.

The digital image data processing device is characterized in that it further includes preprocessing means for converting the digital image data into multiple values before the digital image data is applied to the one-line memory means.

In the digital image data processing device described above, it is preferable that the calculation means includes an OR circuit.

Furthermore, in the digital image data processing device,
The preprocessing means is 21i1! for converting digital image data into 2Vi. It may also be used as a chemical treatment means.

The digital double-image data processing device is characterized in that it further includes post-processing means for multi-valued output data of the one-line memory means to create final output data.

In the above-mentioned digital image data processing device, it is preferable that the post-processing means is a binarization processing means for binarizing the output data of the one-line memory means.

According to the present invention, feedback data serving as shadow data is created by subtracting a predetermined value from one line of digital image data, and is added to one line of newly provided digital image data. . By changing the predetermined value to be subtracted, the shadow data changes and the length of the shadow image can be considered.

<Embodiment> An embodiment of the present invention will be described in detail below, taking a digital copying machine as an example.

Principle of stereoscopic shading When a document image is read by a CCD line image sensor in a digital copying machine, the data read from the CCD line image sensor is divided into two images at each image sensor reading pitch (for example, 400 dots/inch). It is divided into a dimensional array of pixels and processed.

In other words, if the reading direction (lengthwise direction) of the CCD line image sensor is the main scanning direction X, and the relative displacement direction between the CCD line image sensor and both images of the document is the sub-scanning direction Y, then As shown in FIG. 1, the read original image data is 2 of (Xi, Yj).
It can be represented as a set of dimensional arrays.

The data read by the CCD line image sensor as shown in FIG. 1 is one line ((XO.

Y j) ~(Xm, Y j): However, j is 0 to n
) are given to the processing circuit in chronological order.

Next, a specific example will be given and explained.

The original image shown in Fig. 2 is transferred to the CCD line image sensor 2.
Consider the case of reading with 0. In FIG. 2, X indicates the main scanning direction and Y indicates the sub-scanning direction. When the original image shown in FIG. 2 is read by the CCD line image sensor 20, it is recognized as an image of a large number of pixel sets as shown in FIG. 3, for example. In this case, the read output data of the CCD line image sensor 20 is a set of two-dimensional arrays (Xi, Yj) shown in FIG.

In this case, the black data of the original image in FIG.
” (hexadecimal representation), and the own data is read as “OO” (hexadecimal representation).If you change the expression, the second
It can be said that the original image shown in the figure has been binarized with "FF" and "00".

Next, when the data shown in FIG. 4 is output in time series from the CCD line image sensor 20, a processing procedure for processing this data to perform stereoscopic shadow projection will be explained.

(1) Prepare a line memory having a memory area for one line.

Here, this line memory is prepared to have a memory area equal in number to the number of read pixels of the CCD line image sensor 20 (the number of read pixels in the main scanning direction X). for example,
F I F O (flrsL in first stout
) memory or random access memory.

For convenience, it is assumed that the memory area of the line memory is numbered as (Zo)(Z+)-(Zi)-(Zm) in contrast to the pixel number (Xi) of the CCD line image sensor 20. .

(2) Initialize all memory areas of the line memory to own data (00). That is, if expressed as a formula, it is set as Zi-00 (i=0 to m).

(3) From the data in each memory area of the line memory,
Constant K (for example, K-22h: However, h is "22#
The code indicating that is expressed in hexadecimal (the same applies below) is subtracted. This process will be referred to as process a.

In this process a, by changing the constant K to be subtracted, for example, by setting it to -11h, the length of the three-dimensional shadow can be increased. That is, by changing the constant K to be subtracted, the length of the three-dimensional shadow can be varied.

Note that when processing a is performed, if the data in the memory area is the own data (OO), the data will not become lower than that, so the data will remain as the white data (OO).

(4) Next, the data subjected to process a is shifted one by one in the 0→m direction within the memory area. This shift processing will be called processing.

As a result of processing, the data in the memory area (Zm) is discarded, and the memory area (Zo) is filled with white data (00).
) is stored.

Note that if this processing is not performed, the data will not be shifted in the main scan direction (X direction), so it is possible to cast shadows that extend only in the sub scan direction (Y direction).

(5) Processed line memory data and CC
A logical sum is calculated with the data of the first line RO (line data indicated by ■ in FIG. 4) provided from the D line image sensor 20, and the result is stored again in the line memory.

This process will be referred to as process C.

If the above processing a to processing C are expressed as a formula, Zo ” (
00) V (Xo, Yo)Z i←(Z i
-, -K) v (X t, yo ) (where the symbols i-1 to m mean the logical sum of every two bits of V).

(6) Output the contents of the line memory subjected to process C to the printer section. This process will be referred to as process d.

(7) Processes a to d described above are performed in synchronization with each line of read data from the CCD line image sensor 20 until the output of line data from ■ to ■ is completed, i.e. Repeat until sub-scanning is completed.

Expressing it as a mathematical formula, Zo − (00) v (Xo, Yj) Z i ← (Z i −, −K) v (X t, Y
j) (However, ① = symbols i-1 to m meaning bitwise logical sum.

j-1~n) Zi-image output (However, i -0~m) becomes.

Further, FIGS. 5A, 5B, and 5C show how the data shown in FIG. 4 is subjected to processes a to d in chronological order. The process proceeds in the order of FIG. 5A→FIG. 5B→FIG. 5C.

1 in FIGS. 5A, 5B, and 5C.
-d, 2-d, 3-d, 4-d... The data marked with 22-d is output to the printer section, and when it is put together, it becomes the two-dimensional array data shown in FIG.

Of the data shown in Figure 6, when the data excluding white data (00) is binarized into black data (F An image is obtained.

The above is the principle of stereoscopic shadowing in this invention.

Specific Apparatus Next, a specific apparatus for realizing the above-mentioned principle of stereoscopic shading will be explained.

FIG. 8 is a schematic diagram of the overall configuration of a digital copying machine to which a digital image data processing apparatus according to an embodiment of the present invention is applied.

The digital copying machine is equipped with a contact glass 13 for setting a document 12 on the top surface of a main body 11, and a document cover 14 that can be opened and closed is provided above the contact glass 13.

A light source 15 is provided above the western part of the main body 11 and is movable along the lower surface of the contact glass 13 in the direction of arrow A1. The light source 15 has a long cylindrical shape extending perpendicular to the paper surface, and the document 12 illuminated by the light source 15
The reflected light is reflected by mirrors 16, 17, 18 and condenser lens 1.
The signal is applied to the CCD line image sensor 20 through one. Then, the image sensor 20 reads the original image.

The CCD line image sensor 20 is a longitudinal sensor extending perpendicularly to the paper surface, and its length direction is the main scanning direction X.

The Harafuku image read by the CCD line image sensor 20 is provided from the image sensor 20 to an image processing circuit 21, where it is subjected to image processing to be described later. The output of the image processing circuit 21 is then applied to the laser diode 22, causing the laser diode 22 to emit light. laser diode 2
The laser beam outputted from 2 is guided by a polygon mirror 23 and applied to a photosensitive drum 25 via a mirror 24.

Known members such as a charging charger 26, a developing device 27, a transfer 1 separation charger 28, and a cleaner 29 are arranged around the photoreceptor drum 25, and an electrostatic latent image is formed on the surface of the photoreceptor drum 25 by an electrophotographic method. The latent image is formed and the latent image is developed into a toner image.

Then, the toner image is taken in from the paper cassette 30 and transferred onto the paper applied to the photosensitive drum 25 with the timing adjusted by the registration rollers 31 . and,
The paper onto which the toner image has been transferred is transported by a transport belt 32 and sent to a fixing device 33. The toner image on the paper is fixed by the fixing device 33, and the copied paper on which the fixing has been completed is discharged to the discharge tray 34.

FIG. 9 is a block diagram showing the configuration of image processing related parts in the digital copying machine described above.

Image data read by the CCD line image sensor 20 is amplified by an amplifier 41, converted from analog data to digital data by an A/D converter 42, and provided to the image processing circuit 21.

The output image data processed by the image processing circuit 21 is output to the laser diode 22, causing the laser diode 22 to emit light.

Further, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is generated by the timing generation circuit 44,
Line synchronization signal Hsync, which is applied to A/D converter 42 and image processing circuit 21 and output from line synchronization signal generation circuit 45, is applied to image processing circuit 21 and timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 operates in synchronization with the reference clock CK output from the clock oscillator 46, and synchronizes each line with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. perform an action. The image processing circuit 21 similarly operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is placed under the control of a CPU 47 for controlling the overall operation of the digital copying machine.

Next, a more detailed configuration of the image processing circuit 21 shown in FIG. 9 will be explained.

FIG. 10 is a block diagram showing the circuit configuration of the image processing circuit 21. The image processing circuit 21 is provided with an input 2ffi conversion circuit 51 to which image data converted into digital data is provided, an OR circuit 52 to which the output of the input binarization circuit 51 is provided, and an output of the OR circuit 52. FI that can be used
It includes an FO memory 53, an output binarization circuit 54 to which the output of the FIFO memory 53 is applied, and a subtraction circuit 55 to which the output of the FIFO memory 53 is applied. and,
The output of the subtraction circuit 55 is given to an OR circuit 52, where the output is logically summed with the output of the input binarization circuit 51. The output of the OR circuit 52 is applied to the FIFO memory 53 as described above.

The FIFO memory 53 is a CCD line image sensor 2
This is a line memory that has a memory area equal to the number of pixels to be read.

Further, a FIFO timing circuit 56 for controlling the FIFO memory 53 is provided. The clock CK output from the clock oscillator 46 described above is input to the input binarization circuit 51, the OR circuit 52, and the output binarization circuit 5.
4 and FIFO timing circuit 56 as an operating clock.

The FIFO timing circuit 56 also receives a line synchronization signal H output from the line synchronization signal generation circuit 45 described above.
sync is given.

Furthermore, the image processing circuit 21 includes a control CPU 57.
The input binarization circuit 51, the subtraction circuit 55, and the output binarization circuit 54 are controlled by the control CPU 57.

Next, the operation of the circuit shown in FIG. 10 will be explained with reference to the previous explanation of the principle of stereoscopic shading.

By controlling the input 2m converting circuit 51 by the control CPU 57, the memory area of the FIFO memory 53 is initialized to white data (00) (see explanation (2) of the principle of stereoscopic shading).Next, the digital image data is When supplied to the input binarization circuit 51, the input binarization circuit 51 converts the digital image data into 1 based on the clock CK.
The data is converted into 2vi dot by dot and applied to the OR circuit 52.

On the other hand, the output of the FIFO memory 53 is given to the subtraction circuit 55, and in the subtraction circuit 55, the control CPU 5
A predetermined constant K given by 7 (for example −
22h) is subtracted from the output of the memory 53. Therefore, the data after the subtraction is provided to the OR circuit 52.

The OR circuit 52 performs the logical sum of the data provided from the input binarization circuit 51 and the data provided from the subtraction circuit 55.

Then, in response to the next clock CK, the OR circuit 52
The output is sent to the FIFO memory 53.

By the above processing, processing a explained in the principle of stereoscopic shadowing is
1 processing and processing C are performed.

The data stored in the FIFO memory 53 is applied to the output binarization circuit 54 in a first-in, first-out order, where it is converted into 2M original data and shadow data, and is applied to the laser diode 22 as print output data. That is, process d is performed.

FIG. 11 is a block diagram showing a more specific example of the configuration of the circuit shown in FIG. 10.

Next, the circuit of single 11 diagram will be explained.

The input binarization circuit 51 of the image processing circuit 21 receives a clock C.
Image data latch circuit 5 that performs a latch operation in response to K
11, a CPU data latch circuit 512 for latching the binarized threshold data given from the control CPU 57, and an 8-bit comparison calculation circuit 513. The 8-bit comparison calculation circuit 513 compares the output of the image data latch circuit 511 and the output of the CPU data latch circuit 512, that is, a threshold value, and performs binarization processing.

Furthermore, the OR circuit 52 can be configured by, for example, an 8-bit OR circuit 521 and an 8-bit gate circuit 522 connected in series. 8-bit gate circuit 522
is a circuit required to initialize the FIFO memory 1.

Further, the subtraction circuit 55 is, for example, an 8-bit addition circuit 55.
1 and a CPU data latch circuit 552. If the output data of the control CPU 57 is changed, the output of the latch circuit 552 is changed, so that the subtraction constant can be changed.

Further, the output binarization circuit 54 can be configured by an 8-bit comparison calculation circuit 541 and a CPU data latch circuit 542.

In the circuit shown in FIG. 11, the FIFO timing circuit 56 (see FIG. 10) is integrated into the FIFO memory 53.

Instead of the specific circuit example shown in FIG. 11, the image processing circuit 21 may be configured as shown in FIG. 12.

Next, the circuit shown in FIG. 2 will be explained.

Image data latch circuit 51 instead of input 2M conversion circuit 51
1, and image data is processed as multivalued data. For this purpose, an 8-bit comparison calculation circuit 523 for selecting the maximum value and an image data latch circuit 51 are provided.
8 for selectively passing data given from 1.
A bit gate circuit 524, an 8-bit gate circuit 525 for selectively passing the subtraction result data, and a FIF
The configuration includes an 8-bit gate circuit 526 necessary for initializing the O memory 53.

Further, the subtraction circuit 55 includes a RAM for generating a subtraction value function.
553, a CPU data latch circuit 554 for holding data to be written to the RAM 553 as a subtraction value function,
It can be configured to include an 8-bit data selector 555 for selecting whether to initialize or operate the RAM 553, and a CPU latch circuit 556 for holding initial drop number data.

Further, the FIFO timing circuit 56 can be configured by a programmable shift circuit 561 for shifting the read timing and a CPU data latch circuit 562 for holding the shift amount. By covering the shift amount of the shift circuit 561, the shift amount of the processing unit can be changed.

Furthermore, the output binarization circuit 54 includes an 8-bit comparison calculation circuit 543 for performing dither binarization, a RAM 544 for holding the dither matrix, and a selection of whether to initialize or execute the dither matrix. 8-bit data selector 545 for counting the line synchronization signal and R
Counter 5 for generating the upper address of AM545
46, a counter 547 for counting clocks and generating a lower address of the RAM, a CPU data latch circuit 548 for holding the RAM initialization address of the dither matrix, and initialization data of the RAM of the dither matrix. CPU day latch circuit 54 for holding
9.

Explanation of example food types Next, various modifications of this embodiment will be explained.

In FIG. 10, the output of the FIFO memory 53 is binarized by the output binarization circuit 54, and image data (FF
) and shadow data with stereoscopic shading, but instead of this, an output multi-value conversion circuit may be provided to convert the output into multi-value data.

When the output is multi-valued, gradation (gradation) can be given to stereoscopic shadowing.

Furthermore, by setting the shift amount for shifting the data by 1 in the processing to 2, 3, 4, . . . other than 1, or 0, the slope of stereoscopic shadowing can be changed.

In this case, if the data shift means is removed or the data shift amount in the data shift means is set to "0", shadowing occurs only in the sub-scanning direction. Conversely, by increasing the shift amount, the shadow can be made closer to the main scanning direction X. This shift amount can also be changed using Control C.
Can be performed by PU57, control CPU
If the shift amount is changed in step 57, the value of the CPU data latch circuit 562 in the circuit of FIG. 12, for example, changes.

Furthermore, in process a, the subtraction value K may not be a constant, but may be a value that depends on the data value to be subtracted. In other words, K that has a specific relationship with the data value Zi to be subtracted
It may also be a subtraction value given by a function (Zl).

In this way, when adding a gradation to stereoscopic shadowing, the gradation can be varied. For example, rather than having the gradation change sequentially according to the length of the shadow, it is possible to change the change in the gradation.

Furthermore, as mentioned in the circuit description of FIG. 12, the OR circuit 52 may be replaced with a circuit that performs maximum value selection calculation.

If you do that, the input data will not be binary data,
Even in the case of multivalued data, stereoscopic shadowing can be performed.

Furthermore, in the explanation of the principle of stereoscopic shading, it has been explained that data processing is performed line by line, but data processing may be performed pixel by pixel.

That is, processes a to d described in the section on the principle of stereoscopic shadowing are performed for each pixel.

Furthermore, by selecting the output of process d, it is also possible to perform linear three-dimensional shadowing, as shown in FIG.

Further, the present invention can also be used in a full-color image forming apparatus, such as a full-color copying machine, to colorize a gradation with a three-dimensional shadow.

Further, in the above-described embodiment, an example was shown in which a FIFO memory was used as the one-line memory, but a random access memory may be used instead of the FIFO memory.

<Effects of the Invention> Since the present invention is configured as described above, there is provided a digital image data processing device that can perform processing such as stereoscopic shadowing by using one storage means having a one-line memory area. can be provided. In particular, it is possible to obtain a shadow of a desired length by varying the length of the shadow image.

Further, according to the present invention, one line of memory area is
Processing can be done by using storage means that
By applying the present invention to an image processing device, it is possible to provide a small and inexpensive image forming device.

[Brief explanation of drawings]

Drawing 1 is a diagram showing document image data read by a CCD line image sensor as a set of two-dimensional arrays. FIG. 2 is a diagram showing an example of a document image read by a CCD line image sensor. FIG. 3 is a diagram showing an image recognized by the CCD line image sensor when the original image shown in FIG. 2 is read by the CCD line image sensor. FIG. 4 is a diagram showing read output data of the CCD line image sensor corresponding to the image in FIG. 3. FIGS. 5A, 5B, and 5C are diagrams chronologically showing how processes a to d are applied to the data shown in FIG. 4. FIG. 6 is a two-dimensional array of data labeled 1-d, 2-d, . . . , 22-d in FIGS. 5A, 5B, and 5C. FIG. 7 is a diagram showing an image with three-dimensional shading based on the data shown in FIG. FIG. 8 is a schematic diagram of the overall configuration of a digital copying machine to which a digital image data processing apparatus according to an embodiment of the present invention is applied. FIG. 9 is a block diagram showing the configuration of image processing related parts in the digital copying machine. FIG. 10 is a block diagram showing the configuration of the image processing circuit. FIG. 11 is a block diagram showing a more specific example of the configuration of the circuit shown in FIG. 10. FIG. 12 is a block diagram showing another more specific example of the configuration of the circuit shown in FIG. 10. FIG. 13 is a diagram showing an example of a change in stereoscopic shading. 14th v! J is a diagram for explaining stereoscopic shadowing in a conventional digital copying machine, (A) is a document image, (
B) is a diagram showing a copy image when a document image is copied with a three-dimensional shadow. In the figure, 20... CCD line image sensor,
43... Image processing section, 45... 1 line synchronization signal generation circuit, 46... 1 dot clock oscillator, 51...
- Input binarization circuit, 52... OR circuit, 53...
FIFO memory, 54... Output binarization circuit, 55...
・Subtraction four-way, 56...FIFO timing circuit is shown.

Claims (1)

[Claims] 1. 1-line memory means for inputting and storing 1 line of digital image data given; and 1-line memory means for feeding back output data of the 1-line memory means to the 1-line memory means. Feedback means; Subtraction means provided in the feedback means for subtracting a predetermined value from the output data of the one-line memory means to feed back; Changing means for changing the predetermined value subtracted by the subtraction means; New one-line memory means. and a calculation means for calculating one line of digital image data given to the data change processing means and feedback data changed by the data change processing means and inputting the result to the one line memory means. Digital image data processing device. 2. The digital image processing device according to claim 1 further comprises: timing shift means provided in the feedback means for shifting the output timing of the output data of the one-line memory means to be fed back. It is something to do. 3. The digital image data processing device according to claim 1 further comprises: preprocessing means for converting the digital image data into multiple values before the digital image data is provided to the one-line memory means. That is. 4. The digital image data processing device according to claim 1, wherein the arithmetic means includes an OR circuit. 5. The digital image data processing apparatus according to claim 3, wherein the preprocessing means includes a binarization processing means for binarizing the digital image data. 6. The digital image data processing device according to claims 1 to 5 further includes post-processing means for multi-valued output data of the one-line memory means to create final output data. This is a characteristic feature. 7. The digital image data processing device according to claim 6, wherein the post-processing means includes a binarization processing means for binarizing the output data of the one-line memory means. .