JP2977608B2 - Image edge processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for digitally processing an image to perform image trimming, and more particularly, to an image trimming apparatus for a digital copying machine, a digital printer, and the like. It relates to a processing device.

<Related Art> For example, some recent digital copying machines can perform image trimming processing. Conventionally, an image trimming processing device provided in this type of apparatus focuses on a large number of pixels constituting an image sequentially, and determines whether a surrounding pixel of the focused pixel has the same density as the focused pixel or a different density. In the case where the density of one of the surrounding pixels is different from the density of the target pixel, it is determined that there is a boundary of the image, and the image is trimmed.

<Problems to be Solved by the Invention> Meanwhile, in a digital copying machine or the like, an image is read in the main scanning direction by a line CCD or the like, and the relative positional relationship between the line CCD or the like and the image is different from that in the main scanning direction. The mechanism is such that the image is read in the sub-scanning direction while being changed in the orthogonal sub-scanning direction.

For this reason, in the conventional image edge processing device,
In order to increase the width of the border line, it is necessary to provide a line memory for the width to be increased in the width scanning direction. This is because one line of image data read by a line CCD or the like must be held by the width of the trimming line.

Now, when the resolution of the digital copying machine is, for example, about 200 dots / inch (DPI), a border line having a width of about 1/8 mm can be drawn by one line memory.
Therefore, for example, if the width of the outline line is set to 0.5 mm, four line memories may be provided.

However, the higher the resolution of digital copiers is, for example, 600 DPI, 800 DPI, and 1200 DPI, the more twelve line memories, 16 line memories, 24 A large number of line memories are required, such as one line memory.

Providing a large number of line memories not only leads to an increase in the cost of the entire device, but also has a drawback that the control circuit becomes complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks and to provide an image trimming processing apparatus capable of drawing a sufficiently thick trimming line with a small number of line memories.

<Means for Solving the Problems> The present invention relates to an image trimming processing device, which has a plurality of shadowing circuits, each of which stores given digital image data. Feedback means for feeding back the output of the one-line memory means to the input side of the one-line memory means, provided in the feedback means, and subtracting a predetermined value from the fed-back data to obtain a shadow image Change processing means for generating data;
Shift setting means for shifting the data to be fed back, calculating the logical sum of the newly given digital image data and the shadow image data generated by the change processing means,
An arithmetic means for providing the obtained data to the one-line memory means; and an output processing means for binarizing the output of the one-line memory means into shadow image data and data other than the shadow image data, and A shift direction is set in the shift setting means of each of the shadow-casting circuits so that the directions in which the shadows obtained by the shadow-casting circuits extend are different from each other, and the outputs of the plurality of shadow-casting circuits are combined. And a synthesizing means for performing the processing.

Further, according to the present invention, in the image trimming device, three pairs of two shadowing circuits are provided.
Each of the shift setting circuits is adjusted so that the direction in which the shadow output from the three shadowing circuits extends is the lower left 45 ° direction, the lower right direction, and the lower right 45 ° direction of the given image, respectively. It is a feature.

<Operation> According to the present invention, shadow image data is created in each of the plurality of shadowing circuits, and a shadow image is output. The directions in which the shadows output from the respective shadowing circuits extend are different from each other. Then, the combining means combines the shadow images output from the plurality of shadowing circuits and extending in mutually different directions, and forms a border line surrounding the image as a whole and outputs.

Embodiment Hereinafter, as one embodiment of the present invention, an image trimming processing device provided in a digital copying machine will be described in detail.

First, the principle of shadowing in the shadowing circuit included in the image trimming processing device will be described.

Principle of shadowing When an original image is read by a CCD line image sensor in a digital copying machine, the data read from the CCD line image sensor is based on a two-dimensional arrangement of the original image at each reading pitch of the image sensor (for example, 400 dots / inch). And processed.

That is, if the reading direction (length direction) of the CCD line image sensor is defined as the main scanning direction X and the relative displacement direction between the CCD line image sensor and the original image is defined as the sub-scanning direction Y, the reading is performed by the CCD line image sensor. The original image data to be obtained can be represented as a set of a two-dimensional array of (Xi, Yj) as shown in FIG.

Then, the read data of the CCD line image sensor as shown in FIG. 2 includes one line ((X ₀ , Yj) to (Xm, Y
j): However, j is given to the processing circuit in a time series for every 0 to n).

 Next, a specific example will be described.

The case where the original image shown in FIG. 3 is read by the CCD line image sensor is given. In FIG. 3, X indicates the main scanning direction, and Y indicates the sub-scanning direction. When the original image shown in FIG. 3 is read by the CCD line image sensor, it is recognized as, for example, an image of a large number of images as shown in FIG. In this case, the read output data of the CCD line image sensor is shown in FIG. 5 (Xi, Y
j) is a set of two-dimensional arrays.

In this case, the black data of the original image in FIG.
F "(hexadecimal notation) and white data are read as" 00 "(hexadecimal notation). In other words, the original image shown in FIG. 3 is binary with" FF "and" 00 ". It can be said that it was made.

Next, when the data shown in FIG. 5 is output in chronological order from the CCD line image sensor, a processing procedure for processing the data and performing three-dimensional shadowing will be described.

(1) A line memory having a memory area for one line is prepared.

Here, a line memory having a memory area equal to the number of read images (the number of read pixels in the main scanning direction X) of the CCD line image sensor is prepared. For example, FIFO
(First in first out) memory or random access memory.

For convenience, it is assumed that the memory area of the line memory is numbered as (Z ₀ ) (Z ₁ )... (Zi)... (Zm) in comparison with the pixel number (Xi) of the CCD line image sensor. .

(2) Initialize the entire memory area of the line memory to the occupation data (00). That is, when expressed by an equation, Zi ← 00 (i = 0 to m).

(3) From the data in each memory area of the line memory,
A constant K (for example, K = 22h: where h is a code indicating that “22” is a hexadecimal number, the same applies to the following) is subtracted. This processing line will be referred to as processing a.

In the case where the process a is performed, if the data in the memory area is white data (00), the data does not become less than that, so the data remains white data (00).

(4) Next, the data subjected to the processing a is shifted one by one in the 0 → m direction in the memory area. This shift process will be referred to as process b.

As a result of the processing b, the data in the memory area (Zm) is discarded, and the white data (00) is stored in the memory area (Z ₀ ).

(5) The data of the line memory that performed the process b and the CCD
The logical sum with the data of the first line (the line data shown in FIG. 5) given from the line image sensor is obtained, and the result is stored again in the line memory. This process is called process c.

The above processing a to processing c can be expressed by the following equation: Zo ← (00) v (Xo, Yo) Zi ← (Zi ₋₁₋ K) v (Xi, Yo) (where, v: logic for each bit) The symbol i = 1 to m which means the sum is obtained.

(6) Output the contents of the line memory that has been subjected to the process c to the printer unit. In this case, adjust the output to match the printer.
Value conversion etc. This process is called process d.

(7) Each time one line of read data is supplied from the CCD line image sensor, the processes a to d described above are performed in synchronization with the read data, and until the output of the line data of Repeat until done.

If it is represented by a mathematical expression, Zo ← (00) v (Xo, Yj) Zi ← (Zi ₋₁₋ K) v (Xi, Yj) (where, v: a symbol meaning a logical sum for each bit i = 1 to m, j = 1 to n) Zi → image output (where i = 0 to m).

FIG. 6A and FIG. 6A show the time sequence of performing the processes a to d on the data shown in FIG.
FIG. 6B and FIG. 6C. The processing proceeds from FIG. 6A to FIG. 6B to FIG. 6C.

6A, 6B and 6C, 1-d,
Data marked with 2-d, 3-d, 4-d ..., 22-d is output to the printer unit, and when the data is put together, it becomes data in a two-dimensional array shown in FIG.

By the process d, the data shown in FIG. 7 is ternarized into white data (00), black data (FF) or intermediate data,
When it is printed out, an image with a three-dimensional shadow as shown in FIG. 8 is obtained.

By changing the constant K to be subtracted in the above-described process a, the length of stereoscopic shadowing can be changed.

Also, by setting the data shift amount in the process b to “−1” or “0” instead of “+1” in the direction from 0 to m, the inclination of the stereoscopic shadow is set to the lower left. 45
It can be in the ゜ direction or just below.

The above is the principle of shadowing in the shadowing circuit provided in the present invention, in particular, the principle of three-dimensional shadowing.

Next, a specific configuration of an embodiment of the present invention will be described.

Specific Apparatus FIG. 9 is a schematic diagram of the entire configuration of a digital copying machine provided with an image trimming processing apparatus according to one embodiment of the present invention.

The digital copying machine is provided with a contact glass 13 for setting a document 12 on an upper surface of a main body 11, and an openable / closable document cover 14 is provided thereon.

Above the inside of the main body 11, a light source 15 that is movable in the direction of arrow A1 along the lower surface of the contact glass 13 is provided. The light source 15 has a long cylindrical shape extending in the direction perpendicular to the plane of the drawing, and the reflected light of the document 12 illuminated by the light source 15 is given to the CCD line image sensor 20 via the mirrors 16 and 1718 and the condenser lens 19. . Then, the original image is read by the image sensor 20.

The CCD line image sensor 20 is a sensor having a longitudinal shape extending in a direction perpendicular to the paper surface, and its length direction is the main scanning direction X.

The document image read by the CCD line image sensor 20 is provided from the image sensor 20 to an image processing circuit 21 and subjected to image processing described later. Then, the output of the image processing circuit 21 is given to the laser diode 22 to cause the laser diode 22 to emit light. The laser light output from the laser diode 22 is guided by the polygon mirror 23,
The light is supplied to the photosensitive drum 25 via 24.

Known members such as a charger 26, a developing device 27, a transfer / separation charger 28, and a cleaner 29 are arranged around the photoconductor drum 25. An electrostatic latent image is formed on the surface of the photoconductor drum 25 by an electrophotographic method. Once formed, the latent image is developed into a toner image. Then, the toner image is taken from the paper cassette 30, and is transferred to the paper supplied to the photosensitive drum 25 at a timing adjusted by the registration roller 31. Then, the sheet on which the toner image has been transferred is conveyed by the conveying belt 32 and sent to the fixing device 33. The toner image on the paper is fixed by the fixing device 33, and the copied paper on which the fixing is completed is discharged to the discharge tray.

FIG. 10 is a block diagram showing a configuration of a part related to image processing in the digital copying machine described above. The image data read by the CCD line image sensor 20 is supplied to the amplifier 41
, And is converted from analog data to digital data by the A / D converter 42 and supplied to the image processing circuit 21. Then, the output image data processed by the image processing circuit 21 is output to the laser diode 22 to cause the laser diode 22 to emit light.

Further, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is supplied to the timing generation circuit 44, the A / D converter 42, and the image processing circuit 21, and the line synchronization signal Hs output from the line synchronization signal generation circuit 45
ync is supplied to the image processing circuit 21 and the timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 is
The operation is performed in synchronization with the reference clock CK output from the CPU, and the operation is performed in synchronization with each line by the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. Similarly, the image processing circuit 21 operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is under the control of a CPU 47 for controlling the entire operation of the digital copying machine.

FIG. 1 is a block diagram showing a configuration of the image processing circuit 21 shown in FIG. As shown in FIG. 1, the image processing circuit 21 has six shadowing circuits 211, 212, 21 connected in parallel.
3, 214, 215, and 216, and the image data supplied to the image processing circuit 21 is supplied in parallel to these six shadowing circuits 211 to 216. Also, six shadowing circuits 211
Image inverting circuits 217, 218, and 219 are inserted in the preceding stages of the three shadowing circuits 214, 215, and 216 among the circuits 216 to 216, respectively. Therefore, these three shadowing circuits 214, 21
5,216 is supplied with inverted image data.

Further, the image processing circuit 21 is provided with an OR gate circuit 220 as a synthesizing means. The OR gate circuit 220 combines the image data processed by the six shadowing circuits 211 to 216, and outputs a trimmed image as described later.

All of the six shadowing circuits 211 to 216 in FIG. 1 have the same circuit configuration. Therefore, next, the shadowing circuit 211 will be taken up and its detailed configuration will be described.

FIG. 11 is a block diagram showing a circuit configuration of the shadowing circuit 211, and FIG. 12 is a block diagram more specifically showing the circuit of FIG.

First, a description will be given with reference to FIG.
Is an input processing circuit to which digital image data is given.
And an OR circuit 52 to which the output of the input processing circuit 51 is given
And a FIFO memory 53 to which an output of the OR circuit 52 is given,
An output processing circuit 54 to which an output of the FIFO memory 53 is given;
And a subtraction circuit 55 to which the output of the FO memory 53 is given. Then, the output of the subtraction circuit 55 is given to the OR circuit 52, and the OR of the output of the input processing circuit 51 is obtained by the OR circuit 52.

The FIFO memory 53 is a line memory having a memory area equal to the number of read pixels of the CCD line image sensor 20.

Further, the above-described processing b performed in the FIFO memory 53
FIFO timing circuit to control the amount of data shift
56 are provided.

The clock CK output from the above-described clock oscillator 46 is supplied to the input processing circuit 51, the OR circuit 52, the output processing circuit 54, and the FIFO timing circuit 56 as operation clocks. The FIFO timing circuit 56 is supplied with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45 described above.

Further, the shadowing circuit 211 receives an instruction from the CPU 47 (see FIG. 10) and starts the operation of the control CPU 5.
7 are provided. From the control CPU 57, an input processing circuit 51, a subtraction circuit 55, an output processing circuit 54 and a FIFO
Data and control processing are applied to the timing circuit 56.

Next, the operation of the circuit of FIG. 11 will be described with reference to the explanation of the principle of the shadowing.

By controlling the input processing circuit 51 by the control CPU 57, the memory area of the FIFO memory 53 is initialized to white data (00) (see the explanation of the shaded principle (2)).

Next, when the digital image data is given to the input processing circuit 51, the input processing circuit 51
The digital image data is binarized instead of one dot, and supplied to the OR circuit 52.

On the other hand, the output of the FIFO memory 53 is
Is given to the subtraction circuit 55 at a predetermined read timing set by (1) (processing b is performed), and the subtraction circuit 55
In, a predetermined constant K (for example, K = 22h) given by the control CPU 57 is subtracted from the output of the memory 53 (processing a is performed). Therefore, the data after the subtraction is supplied to the OR circuit 52.

The logical sum circuit 52 performs a logical sum of the data supplied from the input processing circuit 51 and the data supplied from the subtraction circuit 55 (processing c is performed).

Then, in response to the next clock CK, the output of the OR circuit 52 is stored in the FIFO memory 53.

By the above processing, the processing a described with the shadowing principle,
Processing b and processing c are performed. Processing a and processing b
Although the order is reversed, there is no problem.

The data stored in the FIFO memory 53 is supplied to the output processing circuit 54 in a first-in first-out order. Then, in the output processing circuit 54, a process d is performed so that the image data is binarized into the shadow image data, the original image and the background data, and only the shadow image is output, for example, blackened.

 Next, the circuit of FIG. 12 will be described.

The input processing circuit 51 of the shadowing circuit 211 includes an image data latch circuit 511 that performs a latch operation in response to the clock CK,
It can be composed of a CPU data latch circuit 512 for latching binarized threshold data provided from the control CPU 57, and an 8-bit comparison operation circuit 513. The 8-bit comparison operation circuit 513 performs a binarization process by comparing the output of the image data latch circuit 511 with the output of the CPU data latch circuit 512, that is, the threshold value.

The OR circuit 52 is, for example, an 8-bit OR circuit.
It can be configured by connecting a 521 and an 8-bit gate circuit 522 in series. The 8-bit gate circuit 522 is a FIFO
This is a circuit necessary to initialize the memory 53.

The subtraction circuit 55 includes, for example, an 8-bit addition circuit 551.
And the CPU data latch circuit 552. If the output data of the control CPU 57 is changed, the output of the latch circuit 552 is changed, so that the subtraction constant can be changed.

Further, the output processing circuit 54 has a border setting selection RAM 54.
1. It can be configured by a trimming data setting latch circuit 542, a trimming data address selection circuit 543, and a trimming data address setting latch circuit 544.
The operation of these circuits will be briefly described as follows.

By initialization, predetermined data is written to the frame data setting selection RAM 541. This is done by making the control signal from the control CPU 57 high so that the B input of the trimming data address selection circuit 543 becomes the Q output, and sequentially from the trimming data address setting latch circuit 544 to "F".
F ”,“ FE ”,“ FD ”... Output data of“ 01 ”and“ 00 ”, and sort the data to a data address selection circuit 54
The Q output of 3 is given to the address input of the trimming data setting selection RAM 541. In addition, in synchronization with this processing, “0”, “1”, “1”,.
… Select data of “1” and “0” as trimming data
Give to RAM541 data input. Frame data setting selection
RAM 541 is in the write mode because the control signal from control CPU 57 is high,
RAM 541 contains "FF" → "0", "FE"-"01" →
An address and data corresponding to the address are stored, such as “1”, “00” → “0”.

The above initialization processing is performed. And control
The control signal from the CPU 57 becomes low, and the trimming data address selection circuit 543 is set so that its A input becomes a Q output. Also, select the border data setting
The RAM 541 is in a state where data is read according to the address input.

Therefore, data is output from the FIFO memory 53, and when the data is the original image data of “FF” and the background data of “00”, 1-bit data of “0” is output from the frame setting selection RAM 541. On the other hand, when the shadow image data of “FE” to “01” is output from the FIFO memory 53, 1-bit data of “0” is output from the trimming setting selection RAM 541 correspondingly.

As described above, when the data output from the FIFO memory 53 is the black data (FF) as the original image data and the white data (00) as the background data, the 1-bit data “0” is output from the trimming setting selection RAM 541. Is output.

On the other hand, when the data output from the FIFO memory 53 is shadow image data expressed in halftone between black data and white data, 1-bit data “1” is output from the frame setting selection RAM 541. You.

Meanwhile, in the shadowing circuit 211 of FIG. 11, the FIFO timing circuit 56 includes a programmable shift circuit 561 for shifting the read timing and a CPU data latch circuit 562 for setting and holding the shift amount. The CPU data latch circuit 562 has a control CP
The data and control signal from U are supplied, and the shift amount is set and held.

The shift amount of the processing b in the shadowing circuit 211 is set to “−1” in the main scanning direction.

Other shadowing circuits 212, 213, 214, 215, 216 shown in FIG.
As described above, the configuration is the same as that of the shadowing circuit 211 shown in FIG. 12, but the shift amount by the programmable shift circuit 561 and the CPU data latch circuit 562 is different from the shift amount of the shadowing circuit 211. .

That is, the shadowing circuit 212 sets the shift amount to “0” in the main scanning direction, the shadowing circuit 213 sets the shift amount to “+1” in the main scanning direction, and the shadowing circuit 214 sets the shift amount to “1” in the main scanning direction. For the shadowing circuit 215, the shift amount is set to "0" in the main scanning direction, and for the shadowing circuit 216, the shift amount is set to "+1" in the main scanning direction.

In any of the shadowing circuits 211 to 216, the amount of shift of the image in the sub-scanning direction is delayed by one line with respect to the input data because the subtraction circuit 55 subtracts the data. Therefore, the shift amount in the sub-scanning direction is “+1” in any circuit.

Next, for example, the image shown in FIG. 13, that is, the colored circle is read by the CCD line image sensor 20 of the digital copying machine shown in FIG. 9, and the read data is processed by the circuit shown in FIG. A case where a framed image of the illustrated image is obtained will be described.

The image data in FIG. 13 is processed by the shadowing circuit 211 in FIG. 1 to become an image in FIG. 14 (A). When processed by the shadowing circuit 212, an image shown in FIG. 14B is obtained. Similarly, when processed by the shadowing circuit 213, an image shown in FIG. 14C is obtained.

When processed by the shadowing circuit 214, the image before processing is an image obtained by inverting the image in FIG.
FIG. 14D shows the output image of FIG. Similarly, the image of the shadowing circuit 215 is added to the image shown in FIG.
The 16 output images become the images shown in FIG. 14 (F).

Then, the OR gate circuit 220 generates six shadowing circuits 211 to 21.
When the outputs of 6 are combined, the output image is as shown in FIG. Strictly speaking, the image of FIG. 15 does not accurately trace the outline of the colored circle shown in FIG. 13 and, due to the nature of the shadowing process, is a slightly distorted circle frame image. I have.

However, except for such a slight image distortion, only six line memories and a few peripheral circuits allow the thickness of the outline to be up to 254 lines (because of eight lines).
Since bit = 256 and black data (FF) representing the original image and white data (00) representing the background image are not involved, 25
(2−2 = 254 lines) can be obtained.

In the embodiment described above, the border setting selection RA shown in FIG.
M541, a trimming data setting latch circuit 542, a trimming data address selection circuit 543, and an output processing circuit 54 including a trimming data address setting latch circuit 544.
For example, the configuration can be easily made using only the trimming setting ROM in which the relationship between the trimming data and the address is set in advance.

Further, in the above-described embodiment, as shown in FIG. 1, the image processing circuit 21 is provided with the six shadowing circuits 211 to 216. twenty one
It is also possible to use four shading circuits 3, 214 and 216. This is because, as is apparent from the output image shown in FIG. 14, a framed image of the image shown in FIG. 13 can be obtained by the outputs of these four shadowing circuits. However, the width of the framed image may be slightly thicker or thinner depending on the location.

<Effects of the Invention> According to the present invention, a trimming processing circuit can be configured by using a plurality of, for example, four or six, shading circuits each including a line memory and a small number of peripheral circuits. With the number of line memories, it is possible to provide an image trimming processing circuit capable of obtaining a trimmed image having a much wider width than the conventional one.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an image trimming processing circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing document image data read by a CCD line image sensor as a set of two-dimensional arrays. FIG. 3 is a diagram illustrating an example of a document image read by a CCD line image sensor. FIG. 4 is a diagram showing an image recognized by the CCD line image sensor when the original image of FIG. 3 is read by the CCD line image sensor. FIG. 5 is a diagram showing read output data of a CCD line image sensor corresponding to the image of FIG. FIG. 6C is a diagram showing in chronological order the manner in which processes a to d are performed on the data shown in FIGS. 6A, 6B, 6C, and 5. FIG. 7 shows 1-d, FIG. 6A, FIG. 6B and FIG. 6C.
It is the figure which expressed the data to which 2-d, ..., 22-d was attached by a two-dimensional array. FIG. 8 is a diagram showing an image shaded three-dimensionally based on the data shown in FIG. FIG. 9 is a schematic diagram of an entire configuration of a digital copying machine to which a digital image data processing device according to one embodiment of the present invention is applied. FIG. 10 is a block diagram showing a configuration of a part related to image processing in the digital copying machine. FIG. 11 is a block diagram showing the configuration of the shadowing circuit. FIG. 12 is a block diagram showing a more specific configuration example of the circuit of FIG. FIG. 13 is a diagram showing an example of an original image provided to the digital copying machine according to this embodiment. FIGS. 14 (A) to (F) show the shadowing circuits 211 to 2 respectively.
FIG. 14 is a diagram showing output images when the images of FIG. 13 are processed by 16 respectively. FIG. 15 is a diagram illustrating a framed image output from the image processing circuit 21. In the figure, 20 ... CCD line image sensor, 21 ...
Image processing circuit, 45 ... Line synchronization signal generation circuit, 46 ...
Clock oscillator, 51: Input processing circuit, 52: OR circuit, 53: FIFO memory, 54: Output processing circuit, 55: Subtraction circuit, 56: FIFO timing circuit, 211, 212, 213, 214,
215, 216: shadowing circuit; 217, 218, 219: image inverting circuit; 220: OR gate circuit.

Claims (2)

(57) [Claims] 1. A plurality of shadowing circuits, each of which has a one-line memory means for storing given digital image data, and an output of the one-line memory means. Feedback means for feeding back to the input side; change processing means provided in the feedback means for subtracting a predetermined value from the fed back data to generate shadow image data; shift setting for shifting the fed back data Means for calculating a logical sum of newly provided digital image data and shadow image data generated by the change processing means, and applying the obtained data to the one-line memory means; Output processing means for binarizing the shadow image data and data other than the shadow image data The shift direction is set in the shift setting means of each shadow-casting circuit so that the directions in which the shadows obtained by the shadow-casting circuits extend are different from each other. An image trimming processing device, comprising: synthesizing means for synthesizing an output of an attaching circuit. 2. The image trimming processing device according to claim 1, wherein the shadowing circuit comprises three pairs of pairs, and the direction in which the shadow output from the three shadowing circuits extends is 45 °, lower right, lower right 45 ° of the given image, respectively
Each shift setting circuit is adjusted to be in the ゜ direction.