JPH03174874A - Digital picture data processor - Google Patents

Abstract

PURPOSE:To attain miniaturization and to reduce the cost by using a storage means having a 1-line memory area to apply processing such as stereoscopic shade. CONSTITUTION:A picture data read by a CCD line image sensor 40 is amplified by an amplifier 41 and converted into a digital data from an analog data by an A/D converter 42 and the resulting data is given to a picture processing section 43. Then the 1-line memory is used to give a predetermined change to a digital picture data by one line to generate a shade picture data as a feedback data and it is added to a digital picture data by one line given newly. Then an output processing means eliminates selectively the shade picture data to obtain an acquired shade data to be a stripe shade. Since the storage means having one-line memory area is used for the processing, the small sized and inexpensive picture forming device is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a processing device for digitally processing image data, and particularly to a digital image data processing device for a digital copying machine, a digital printer, or the like. More particularly, the present invention relates to a digital image data processing apparatus capable of adding stereoscopic shadows to images.

<Prior Art> Taking a digital copying machine as an example, a recent digital copying machine has the following problems as shown in FIG. 16(B) when copying the original image shown in FIG. 16(A).
There are devices that can add three-dimensional shadows to copy images.

In order to perform such stereoscopic shadowing in a digital copying machine, arrow Therefore, it is necessary to provide a memory with a capacity corresponding to the width of the shadow in the sub-scanning direction Y, for example, a line memory for 40 lines.

This is because for one line of original elm image data read by a line sensor, in order to add a shadow, it is necessary to hold data for the width of the shadow.

<Problems to be Solved by the Invention> As described above, in order to perform stereoscopic shadow casting with a conventional digital copying machine, a line memory capable of storing multiple lines is required to store shadow data in the sub-scanning direction Y. This has the drawback of increasing the cost of line memory.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital image data processing device capable of eliminating such drawbacks and performing necessary data processing using a one-line memory.

Means for Solving the Problems The present invention relates to a digital image data processing device, and the present invention relates to a one-line memory means capable of storing one line of given digital image data, and an output of the one-line memory means. feedback means for feeding back the data to the input end of the one-line memory means; change processing means provided in the feedback means for generating shadow image data by subtracting a predetermined value from the fed-back data; Computing means calculates the logical sum of the given digital image data for one line and the shadow image data generated by the change processing means, and supplies the obtained data to the one line memory means, and the output of the one line memory means. After the shadow image data has been selectively removed, the shadow image data is selectively removed according to its data value so that the obtained shadow image becomes a plurality of parallel belt-shaped shadow images along the outline of the original image. The apparatus is characterized in that it includes an output processing means for binarizing the image data and the shadow image data into first data and the background data into second data.

Furthermore, the present invention is characterized in that, in the digital image data processing apparatus, the output processing means further includes means for distinguishing the first data into original image data and shadow image data.

Furthermore, the present invention is characterized in that, in the digital image data processing apparatus, the output processing means determines the differentiated shadow image data to have intermediate density two-image values in which the density does not change.

Further, the present invention provides the digital image data processing device, wherein the output processing means outputs the differentiated shadow image data.
This method is characterized by determining image values whose density gradually changes as the distance from the original image increases.

Effects> According to the present invention, a predetermined change is applied to one line of digital image data to produce shadow image data as feedback data, and this is applied to one line of newly provided digital image data. In addition to As a result, the output digital image data consists of an original image component, a shadow image component, and a background component. The output processing means selectively removes shadow image data,
The obtained shadow image is made to be a so-called striped shadow. Furthermore, the output processing means binarizes the output data into first data consisting of the original image data and shadow image data after being selectively removed, and second data consisting of background data.

Further, the output processing means is configured such that the obtained stripe shadow image is
The value of the shadow image data may be determined so that the density becomes a gray stripe shadow image that does not change, or the value of the shadow image data may be determined so that the stripe shadow image becomes a shadow image that has gradations whose density gradually changes. In addition, the value of the shadow image data may be determined.

Embodiment> Hereinafter, an embodiment of the present invention will be described in detail by taking a digital copying machine as an example.

Principle of stereoscopic shading When an original image is read by a CCD line image sensor in a digital copying machine, the data read from the CCD line image sensor is a two-dimensional image of the original image at each reading pitch of the image sensor (for example, 400 dots/inch). It is divided into array pixels and processed.

In other words, if the reading direction (lengthwise direction) of the CCD line image sensor is the main scanning direction X, and the relative displacement direction between the CCD line image sensor and the document image is the sub-scanning direction Y, then As shown in FIG. 1, the original image data that is
It can be represented as a collection of dimensional arrays.

The data read by the CCD line image sensor as shown in FIG. 1 is one line ((XO.

Yj) ~(Xm, Yj): where j is given to the processing circuit in gji series for each of 0 to n).

Next, a dimensional example will be given and explained.

Consider the case where the original image shown in FIG. 2 is read by a CCD line image sensor. In FIG. 2, X indicates the main scanning direction and Y indicates the sub-scanning direction.

When the original image shown in FIG. 2 is read by a CCD line image sensor, it is recognized as an image of a large number of pixel sets as shown in FIG. 3, for example. In this case, the read output data of the CCD line image sensor is
Shown in FIG. 4 (Xi.

Yj) is a set of two-dimensional arrays.

In this case, the black data of the original image in FIG.
” (hexadecimal representation), white data is read as “OO” (hexadecimal representation).If you change the expression, the second
It can be said that the original image shown in the figure has been converted into 21ifL with "FF" and "00".

Next, when the data shown in FIG. 4 is output in time series from the CCD line image sensor, a processing procedure for processing the data to perform stereoscopic shadowing will be explained.

(1) Prepare a line memory having a memory area for one line.

Here, the line memory is prepared to have a memory area equal in number to the number of read pixels of the CCD line image sensor (number of read pixels in the main scanning direction X). For example, F
I F O (f'1rst in first out
) memory or random access memory.

For convenience, it is assumed that the memory area of the line memory is numbered as (Zo)(Z+)・”(Zi)−(Zm) in contrast to the pixel number (Xi) of the CCD line image sensor. .

(2) Initialize all memory areas of the line memory to white data (00). That is, if expressed as a formula, Zi=OO(i −0 to m).

(3) From the data in each memory area of the line memory,
A constant K (for example, K-22h, where h is a sign indicating that "22" is a hexadecimal number, and the same applies hereinafter) is subtracted. This process will be referred to as process a.

Note that when performing process a, if the data in the memory area is white data (00), the data will not become lower than that, so the data will remain its own data (00).

(4) Next, the data subjected to process a is shifted one by one in the O→m direction within the memory area. This shift processing will be called processing.

As a result of processing, the data in the memory area (Zm) is discarded, and the memory area (Zo) is filled with white data (00).
) is stored.

(5) Processed line memory data and CC
A logical sum is calculated with the first line data (line data indicated by ■ in FIG. 4) given from the D-line image sensor, and the result is stored in the line memory again. This process will be referred to as process C.

If the above processing a to processing C are expressed as a formula, Zo ” (
00)v (Xo, Yo)Z i ←(Z i−+−
K) v (Xi, Yo) (where ■=symbols i-1 to m meaning logical sum for each bit).

(6) Output the contents of the line memory subjected to process C to the printer section. In this case, the output is binarized or the like according to the printer. This process will be referred to as process d.

(7) Processes a to d explained above are performed in synchronization with each line of read data from the CCD line image sensor until the output of line data from ■ to @ is completed, that is, the sub Repeat until scanning is completed.

If we express it mathematically, we get Zo ” (OO) v (Xo , Y j)Z i
+ (Z 1-1-K)v (Xi, Yj) (However, V
Symbols i-1 to m mean the logical sum of every two bits.

j-1~n) Zi-image output (However, 1-0~m) becomes.

Further, FIGS. 5A, 5B, and 5C show in chronological order how processes a to d are applied to the data shown in FIG. 4. The process proceeds from FIG. 5A to section 5B and then to FIG. 5C.

1 in FIGS. 5A, 5B, and 5C.
-d, 2-d, 3-d, 4-d... The data marked with 22-d is output to the printer section, and when it is put together, it becomes the two-dimensional array data shown in FIG.

By processing d, the data shown in FIG. 6 is converted into white data (0
0), black data (FF) or intermediate data and print it out, an image with a three-dimensional shadow as shown in FIG. 7 is obtained.

Furthermore, in the process d, by selecting shadow image data, it is also possible to perform linear three-dimensional shadowing, as shown in FIG.

In the above process d, black data (F
F) and the intermediate data representing the shadow image are the first ffi, and the white data (00) representing the background is the second value.
It may be converted to Wi.

The above is the principle of stereoscopic shadowing in this invention.

Specific Apparatus Next, a specific apparatus for realizing the above-mentioned principle of stereoscopic shading will be explained.

FIG. 9 is a schematic diagram of the overall configuration of a digital copying machine to which a digital image data processing apparatus according to an embodiment of the present invention is applied.

The digital copying machine is equipped with a contact glass 13 for setting a document 12 on the top surface of a main body 11, and a document cover 14 that can be opened and closed is provided above the contact glass 13.

A light source 15 is provided inside and above the main body 11 and is movable along the lower surface of the contact glass 13 in the direction of arrow A1. The light source 15 has a long cylindrical shape extending perpendicular to the paper surface, and the document 12 illuminated by the light source 15
The reflected light is reflected by mirrors 16, 17, 18 and condenser lens 1.
The signal is applied to the CCD line image sensor 20 through one. Then, the image sensor 20 reads the original image.

The CCD line image sensor 20 is a longitudinal sensor extending perpendicularly to the paper surface, and its length direction is the main scanning direction X.

The original yuzu image read by the CCD line image sensor 20 is sent from the image sensor 20 to an image processing circuit 21, where it is subjected to image processing to be described later. The output of the image processing circuit 21 is then applied to the laser diode 22, causing the laser diode 22 to emit light. laser diode 2
The laser beam outputted from 2 is guided by a polygon mirror 23 and applied to a photosensitive drum 25 via a mirror 24.

Around the photoreceptor drum 25 are a charging charger 26, a developing device t27, a transfer 1 separation charger 28, and a cleaner 29.
An electrostatic latent image is formed on the surface of the photoreceptor drum 25 by an electrophotographic method, and the latent image is developed into a toner image.

Then, the toner image is taken in from the paper cassette 30 and transferred onto the paper applied to the photosensitive drum 25 with the timing adjusted by the registration rollers 31 . and,
The paper onto which the toner image has been transferred is transported by a transport belt 32 and sent to a fixing device 33. The toner image on the paper is fixed by the fixing device 33, and the copied paper on which the fixing has been completed is discharged to the discharge tray 34.

FIG. 10 is a block diagram showing the configuration of image processing related parts in the digital copying machine described above. Image data read by the CCD line image sensor 20 is amplified by an amplifier 41, converted from analog data to digital data by an A/D converter 42, and provided to the image processing circuit 21. The output double image data processed by the image processing circuit 21 is output to the laser diode 22, causing the laser diode 22 to emit light.

Further, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is generated by the timing generation circuit 44,
Line synchronization signal Hsync, which is applied to A/D converter 42 and image processing circuit 21 and output from line synchronization signal generation circuit 45, is applied to image processing circuit 21 and timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 operates in synchronization with the reference clock CK output from the clock oscillator 46, and synchronizes each line with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. perform an action. The image processing circuit 21 similarly operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is placed under the control of a CPU 47 for controlling the overall operation of the digital copying machine.

Next, a more detailed configuration of the image processing circuit 21 shown in FIG. 10 will be explained.

FIG. 11 is a block diagram showing the circuit configuration of the image processing circuit 21. As shown in FIG. The image processing circuit 21 includes a human processing circuit 51 to which image data converted into digital data is supplied.
, the output of the human processing circuit 51 is 5. an OR circuit 52 that can be input, a FIFO memory 53 to which the output of the OR circuit 52 is applied, an output processing circuit 54 to which the output of the FIFO memory 53 is applied, and a subtraction llJ path 55 to which the output of the FIFO memory 53 is applied. include. The output of the subtraction circuit 55 is then given to the OR circuit 52, where it is ORed with the output of the human processing circuit 51. Then, the output of the OR circuit 52 is F as described above.
The data is applied to the IFO memory 53.

The FIFO memory 53 is a CCD line image sensor 2
This is a line memory that has a memory area equal to the number of pixels to be read.

Further, a FIFO timing circuit 56 for controlling the FIFO memory 53 is provided. The clock CK output from the clock oscillation 'S46 mentioned above is
Human processing circuit 51, OR circuit 52, output processing circuit 54
and is given to the FIFO timing circuit 56 as an operating clock.

The FIFO timing circuit 56 also receives a line synchronization signal H output from the line synchronization signal generation circuit 45 described above.
sync is given.

Furthermore, the image processing circuit 21 includes a control CPU 57.
The control CPU 57 controls the human processing circuit 51, the subtraction circuit 55, and the output processing circuit 5.
4 is controlled.

Next, the operation of the circuit shown in FIG. 11 will be explained with reference to the previous explanation of the principle of stereoscopic shading.

By controlling the input processing circuit 51 by the control CPU 57, the memory area of the FIFO memory 53 is initialized to white data (00) (see explanation (2) of the principle of stereoscopic shading).

Next, when the digital image data is given to the human power processing circuit 51, the human power processing circuit 51 converts the digital image data into 2fti dots at a time based on the clock CK, and gives it to the OR circuit 52.

On the other hand, the output of the FIFO memory 53 is sent to the subtraction circuit 55.
In the subtraction circuit 55, the control CPU
57 is subtracted from the output of memory 53 by a predetermined constant K (eg -22h). Therefore,
The data after the subtraction is given to the OR circuit 52.

The OR circuit 52 performs the logical sum of the data provided from the human processing circuit 51 and the data provided from the subtraction circuit 55.

Then, in response to the next clock CK, the OR circuit 52
The output is sent to the FIFO memory 53.

By the above processing, processing a explained in the principle of stereoscopic shadowing is
1 processing and processing C are performed.

Data stored in FIFO memory 53 is provided to output processing circuit 54 in first-in, first-out order. Then, in the output processing circuit 54, the original image, shadow image data, and background data are binarized, and the shadow image data is selectively converted to white data so that the resulting shadow becomes a so-called striped shadow. Process d is performed.

FIG. 12 is a block diagram showing a more specific example of the configuration of the circuit shown in FIG. 11.

Next, the circuit shown in FIG. 12 will be explained.

The input processing circuit 51 of the image processing circuit 21 receives the clock CK.
An image data latch circuit 51 that performs a latch operation in response to
1, a CPU data latch circuit 512 for latching the binarized threshold data given from the control CPU 57, and an 8-bit comparison calculation circuit 513. The 8-bit comparison calculation circuit 513 is
2 by comparing the output of the image data latch circuit 511 and the output of the CPU data latch circuit 512, that is, the threshold value.
Perform value processing.

Further, the OR circuit 52 can be configured by, for example, an 8-bit OR circuit 521 and an 8-bit gate circuit 522 connected in series. 8-bit gate circuit 522
is a circuit required to initialize the FIFO memory 53.

Further, the subtraction circuit 55 is, for example, an 8-bit addition circuit 55.
1 and a CPU data latch circuit 552. If the output data of the control CPU 57 is changed, the output of the latch circuit 552 is changed, so that the subtraction constant can be changed.

Further, the output processing circuit 54 includes a stripe setting selection RA.
M541, stripe data setting latch circuit 542,
It can be configured by a stripe data address selection circuit 543 and a stripe data address setting latch circuit 544.

The operation of these circuits will be briefly explained as follows.

By initialization, the stripe data setting selection RAM 541
Write the specified data to. This is the control CPU
The control signal from 57 is made high so that the eight outputs of the stripe data address selection circuit 543 become Q outputs, and the stripe data address setting latch circuit 544 sequentially rFFJ rFEJ... rFOJ r
EFJ..."EO"rDFJ...rDOJ rc
FJ...rcOJ rBFJ...rolJ r
Data ooJ is output, and the data is applied to the address input of the stripe data setting selection RAM 541 as the Q output of the stripe data address selection circuit 543. In addition, in synchronization with this process, rlJ rlJ... rlJ r
OJ..."0""1"...rlJ rOJ...
rOJ rlJ...rOJ "0" data,
Provide data to the stripe data setting selection RAM 541. Since the stripe data setting selection RAM 541 is in the write mode because the control signal from the control CPU 57 is 11, the RAM 541 is in write mode.
541 includes rFFJ → "1", rFEJ ~ "FOJ-
NJ, rEFJ~rEOJ -rOJ, rDFJ~rD
OJ-rlJ, rcFJ~rcOJ→rOJ, rBF
J ~ "BO" → "1", ... "OF" ~ "01" → "
Addresses and their corresponding data are stored in the order of "0", "00" → "0".

The above initialization processing is performed. And control C
The control signal from the PU 57 becomes low, and the stripe data address selection circuit 543 selects
is set to be the output. Further, the stripe data setting selection RAM 541 is in a state in which data is read out according to the address input.

Therefore, data is output from the FIFO memory 53, and the data is the original image data of rFFJ and rFEJ.
~rFOJ, rDFJ~ “DO”, “BF” ~ “BO”
, "9F" to "90", etc., 1-bit data of "1" is output from the stripe setting selection RAM 541. On the other hand, from the FIFO memory 53, rEFJ ~ “EO”, rCFJ ~ “CO”, l”AF
J ~ "AO"... When dedicated shadow image data is output,
Correspondingly, from the stripe setting selection RAM 541, “
1-bit data of "0" is output. Furthermore, FIFO
When the background data of “00” is output from the memory 53,
The stripe setting selection RAM 541 outputs 1-bit data of "0".

In this way, when the data output from the FIFO memory 53 is black data (FF), which is the original image data, 1-bit data of "1" is output from the stripe setting selection RAM 541, and the data is output from the FIFO memory 53. When the data to be read is the own data (00) which is background data, 1-bit data of rOJ is output from the stripe setting selection RAM 541.

On the other hand, if the data output from the FIFO memory 53 is shadow image data expressed in a halftone between the black data and the own data, " 1-bit data of ``1'' or ``0'' is output. When a shadow image is formed based on this output 1-bit data, the shadow image becomes a plurality of parallel band-shaped shadow images along the outline of the Genfuku image, as shown in Fig. 8, that is, a striped shadow. .

In addition, by initialization, the stripe data setting selection RAM
By changing the data written in the stripe 541, the width of the stripe shadow, the interval between the stripe shadows, the number of stripe shadows, etc. can be changed.

In the circuit shown in FIG. 12, the FIFO timing circuit 56 (see FIG. 11) is integrated into the FIFO memory 53.

The image processing circuit 21 may be configured by a circuit shown in FIG. 13 instead of the circuit shown in FIG. 12.

The feature of the circuit shown in FIG. 13 is that the circuit shown in FIG. 12 has an output processing consisting of a stripe setting selection RAM 541, a stripe data setting latch circuit 542, a stripe data address selection circuit 543, and a stripe data address setting latch circuit 544. The circuit 54 is comprised only of a stripe setting selection ROM 545. This simplifies the configuration of the output processing circuit 54.

A stripe setting selection ROM 545 as the output processing circuit 54 shown in FIG. 13 stores addresses and corresponding data in advance.

This address and the data corresponding to it are the same as the data written in the initialization performed in the stripe setting selection RAM 541 in FIG.

In the circuit of FIG. 13, the stripe setting selection ROM
Since the contents of 545 are fixed, the width of the stripe shadows, the interval between stripe shadows, the number of stripe shadows, etc. cannot be changed. However, if a plurality of such stripe setting selection ROMs 545 are connected in parallel, and the contents stored in each ROM 545 are different, so that one of the ROMs 545 can be selected, the width of the stripe shadow obtained You can change the number etc.

FIG. 14 is a specific circuit example showing still another configuration of the image processing circuit 21 shown in FIG. 11.

The circuit shown in FIG. 14 is a circuit that can process manually input image data as multivalued data. For this purpose, an image data latch circuit 511 is provided as the input processing circuit 51.

Further, on the output side of the image data latch circuit 511, an 8-bit comparison calculation circuit 523 for selecting the maximum value and an 8-bit gate circuit 524 for selectively passing the data given from the image data latch circuit 511 are provided. , an 8-bit gate circuit 525 for selectively passing subtraction result data, and an 8-bit gate circuit 526 necessary for initializing the FIFO memory 53.

Further, the subtraction circuit 55 includes a RAM for generating a subtraction value function.
553, a CPU data latch circuit 554 for holding data to be written as a subtraction/replacement number to the RAM 553,
It is composed of an 8-bit data selector 555 for selecting whether to initialize or operate the RAM 553, and a CPU latch circuit 556 for holding initial operation data.

It also includes a FIFO timing circuit 56, a programmable shift circuit 561 for shifting read timing, and a CPU data latch circuit 562 for holding the shift amount. Shift circuit 561
By changing the shift amount of , the shift amount of the process can be changed.

Further, the output processing circuit 54 includes a data selection circuit 5400 that performs processing that will be explained in detail later, an 8-bit comparison calculation circuit 5410 that performs dither processing, a RAM 5411 that holds the dither matrix, and a data selection circuit 5400 that performs processing that will be explained in detail later. 8-bit data selector 5412 for selecting initialization or execution, and line synchronization signal Hsync
a counter 5413 for counting the clock CK and generating the upper address of the RAM 5411, a counter 5414 for counting the clock CK and generating the lower address of the RAM 5411, and a CPU data latch circuit for holding the initialization address of the RAM 5411. 5415 and R
The configuration includes a CPU data latch circuit 5416 for holding initialization data of the AM5411.

Of the above configuration, the data selection circuit 5400 includes a stripe selection RAM 540 as shown in FIG.
1, a stripe data setting latch circuit 5402, a stripe data address selection circuit 5403, and a stripe data address setting latch circuit 5404.

The operation of this data selection circuit 5400 will be briefly explained as follows.

By initialization, predetermined data is written into the stripe selection RAM 5401. This is the control CPU 57 (
(see Figure 14), set the control signal from
Stripe data address selection [r! B of l road 5403
The input is made to be the Q output, and the rF, FJ r
FEJ...rFOJ rEFJ...rEOJ
rDFJ...rDOJ rcFJ..."CO"r
BFJ... Outputs the data "00" and sends the data to the Q of the stripe data address selection circuit 5403.
It is given as an output to the address input of the stripe selection RAM 5401. In addition, in synchronization with this process, rFFJ r77J is sent from the stripe data setting latch circuit 5402.
...r77J roll...roOJ r77
J..."77""00"..."00""77"
...The data "00" is stored in the Strive selection RAM 5.
401 data input. Stripe selection RAM5
401 is in write mode because the control signal from the control CPU 57 is high, so the RAM 5401 stores data "FF" for address "FFJ" and data "77" for address rFEJ.
”, similarly, “77” for rFDJ~rFOJ, r
"OO" for EFJ ~ "EO", rDFJ ~ "DO"
"77" for rCFJ ~ "CO", "0" for rCFJ ~ "CO"
Addresses and corresponding data are stored respectively, such as ``0'', ``77'' for ``BF'' to ``BO'', and so on.

The above initialization processing is performed. And control C
The control signal from the PU 57 becomes low, and the stripe data address selection circuit 5403 is set so that its A input becomes the Q output. Furthermore, the stripe selection RAM 5401 enters a state in which data is read in response to address input.

Therefore, when the data output from the FIFO memory 53 (see FIG. 14) is rFFJ image data,
8-bit black data of rFFJ is output from the stripe selection RAM 5401.

Furthermore, when the background data of "00" is output from the F summer FO memory 53, the 8-bit white data of "00" is output from the stripe selection RAM 5401.

On the other hand, the data output from the FIFO memory 53 is rF
In the case of intermediate data from El to "01", that is, shadow image data, the stripe selection R is selected according to the size of the data.
8-bit data of "77" or "00" is output from AM5401.

Therefore, the shadow image data is expressed with a constant halftone of "77" and is output in a striped form as a whole.

In the circuit shown in FIG. 15, if the data written to the stripe selection RAM 5401 during initialization is set to the data described below, the shadow image data obtained at the time of output can be changed to the density of data expressed in a certain halftone. Instead of gray data that does not change, it is possible to use data that has gradations that gradually become lighter as the distance from the original image data increases.

That is, for initialization, the control signal from the control CPU 57 is set high so that the 8 outputs of the stripe data address selection circuit 5403 become the Q output, and the stripe data address setting latch circuit 54
Sequentially from 04 rF FJrFEJ...rFOJ r
EFJ...rEOJ rDFJ"DE"...rD
OJ rCFJ...rcOJ rBFJ..."
00" is output, and the stripe selection RAM is
5401 address input. In addition, in synchronization with this process, rFFJ rFEJ..."FOJ roll..." is sent from the stripe data setting latch circuit 5402.
・rol” rDFJ rDEJ・・・”DOJ
rooJ...roOJ rDFJ...Gives the data "00" to the data input of the stripe selection RAM 5401. Since the stripe selection RAM 5401 is in the write mode because the control signal from the control CPU 57 is high, the stripe selection RAM 5401
01, the stripe data address selection circuit 5403
The address given from the stripe data setting latch circuit 5402 and the corresponding data given from the stripe data setting latch circuit 5402 are stored. In this case, data "FF" is stored corresponding to address rFFJ, data rFEJ is stored corresponding to address rFEJ, data "FO" is stored corresponding to address "FO". Also, address rEFJ~
Data "00" is stored corresponding to "EO". Further, data "DF" to "DO" are stored corresponding to addresses rDFJ to "DO". Furthermore, corresponding to addresses “CF” to “CO”, data “
00'' is stored, and other addresses and data are stored in the same way.

When the initialization process is performed as described above, the data output from the FIFO memory 53 will be "FF" and "00".
In the case of other shadow image data, the corresponding data output from the stripe selection RAM 5401 becomes stripe data whose gradation gradually changes.

Description of variants Next, various modifications of this embodiment will be explained.

In the process a in the subtraction circuit 55, the constant K to be subtracted
By changing , the length of the three-dimensional shadow can be changed. Changes to constants are made by the control CPU 57.
You can do it by

In addition, the shift amount for shifting the data in the processing step by 1 is set to 2, 3, 4, etc. other than "1". ..., or O, the slope of stereoscopic shadowing can be changed.

In this case, if the data shift means is removed or the data shift amount in the data shift means is set to 0 degrees, shadowing will occur only in the sub-scanning direction.Conversely, by increasing the shift amount, You can make the shadow approach direction X.You can also change this shift amount using control C.
Can be performed by PU57, control CPU
If the shift amount is changed in step 57, the value of the CPU day latch circuit 562 in the circuit of FIG. 14, for example, changes.

Furthermore, in process a, the subtraction value K may not be a constant, but may be a value that depends on the data value to be subtracted. In other words, K that has a specific relationship with the data value Zi to be subtracted
It may also be a subtraction value given by a function (Zl).

In this way, when adding a gradation to stereoscopic shadowing, the gradation can be varied. For example, rather than having the gradation change sequentially according to the length of the shadow, it is possible to change the change in the gradation.

Furthermore, the OR circuit 52 may be replaced with a circuit that performs a maximum value selection operation. In this way, stereoscopic shadowing can be performed even when the input data is not binary data but multivalued data.

Furthermore, in the explanation of the principle of stereoscopic shading, it has been explained that data processing is performed line by line, but data processing may be performed pixel by pixel.

That is, processes a to d described in the section on the principle of stereoscopic shadowing are performed for each pixel.

Further, the present invention can also be used in a full-color image forming apparatus, such as a full-color copying machine, to colorize a gradation with a three-dimensional shadow.

Further, in the above embodiment, an example was shown in which a FIFO memory was used as the one-line memory, but a random access memory may be used instead of the FIFO memory.

<Effects of the Invention> Since the present invention is configured as described above, it is possible to provide a digital image data processing device that can perform processing such as stereoscopic shadowing by using a storage means having a one-line memory area. can be provided.

In particular, according to the present invention, the shadow image added to the image data can be a so-called stripe shadow, and the stripe shadow can be a black stripe shadow, a gray stripe shadow whose density does not change, or you can choose either a striped shadow with gradually lighter tones,
Various changes can be made to the contents of the three-dimensional shadow.

Further, according to the present invention, processing can be performed by using a storage means having a one-line memory area.
By applying the present invention to an image processing device, it is possible to provide a small and inexpensive image forming device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing data of both original images read by a CCD line image sensor as a set of two-dimensional arrays. FIG. 2 is a diagram showing an example of a document image read by a CCD line image sensor. FIG. 3 is a diagram showing an image recognized by the CCD line image sensor when the original image shown in FIG. 2 is read by the CCD line image sensor. FIG. 4 is a diagram showing read output data of the CCD line image sensor corresponding to the image of FIG. 3. FIGS. 5A, 5B, and 5C are diagrams chronologically showing how processes a to d are applied to the data shown in FIG. 4. FIG. 6 is a two-dimensional array of data labeled 1-d, 2-d, . . . 22-d in FIGS. 5A, 5B, and 5C. FIG. 7 is a diagram showing an image with three-dimensional shading based on the data shown in FIG. FIG. 8 is a diagram showing an example in which three-dimensional shadowing is a striped shadow. FIG. 9 is a schematic diagram of the overall configuration of a digital copying machine to which a digital image data processing apparatus according to an embodiment of the present invention is applied. FIG. 10 is a block diagram showing the configuration of image processing related parts in the digital copying machine. FIG. 11 is a block diagram showing the configuration of the image processing circuit. FIG. 12 is a block diagram showing a more specific example of the configuration of the circuit shown in FIG. 11. FIG. 13 is a circuit block diagram showing a modification of the circuit shown in FIG. 12. FIG. 14 is a block diagram showing another configuration example in which the circuit of FIG. 11 is made more specific. FIG. 15 shows a data selection circuit 5400 of the circuit in FIG.
FIG. 2 is a block diagram showing a more detailed configuration example. FIG. 16 is a diagram for explaining stereoscopic shadowing in a conventional digital copying machine, in which (A) shows both images of the original, (B>
2 is a diagram showing a copy image when a document image is copied with a three-dimensional shadow; FIG. In the figure, 20... CCD line image sensor,
43...Both image processing unit, 45...Line synchronization signal light/
l extension 11 path, 46...clock oscillator, 51...manual processing M path, 52...OR circuit, 53...FIF
O memory, 54...output processing circuit, 55...subtraction 1
11 paths, 56...FIFO timing circuits are shown. Figure (XO, Yn) (Xl, Yn)... (Xl, Yn) - (XOI-1, Yn) (Xa+, Yn > Figure Figure -■■■■■-■■ Figure 4 A Figure 4-C Figure B DD DD DD DD DD BB 9977553
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uuuuuυυ0000DO00GO-22-dFigure Figure Figure North JLILILILILIL North''0 Figure Mouth Rororororororo Figure 10 Figure Figure (A) Figure (B) Width of Shadow

Claims (1)

[Scope of Claims] 1. One-line memory means capable of storing one line of digital image data given; Feedback means for feeding back the output of the one-line memory means to the input side of the one-line memory means. , a change processing means provided in the feedback means for generating shadow image data by subtracting a predetermined value from the fed-back data; A computing means calculates a logical sum with the shadow image data obtained and supplies the obtained data to the one-line memory means, and the shadow image obtained from the output of the one-line memory means is processed into a plurality of parallel images along the outline of the original image. The shadow image data is selectively removed according to its data value so as to become a band-shaped shadow image, the image data after the shadow image data has been selectively removed and the shadow image data are used as first data, and the background data is used as first data. A digital image data processing device comprising: output processing means for binarizing second data. 2. The digital image data processing apparatus according to claim 1, wherein the output processing means further includes means for distinguishing the first data into original image data and shadow image data. 3. The digital image data processing apparatus according to claim 2, wherein the output processing means determines the differentiated shadow image data to an intermediate density image value whose density does not change. 4. The digital image data processing device according to claim 2, wherein the output processing means determines the differentiated shadow image data to image values whose density gradually changes as the distance from the original image increases. It is something to do.