JP3137334B2 - Digital image data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device for digitally processing image data, and more particularly to a digital image data processing device for a digital copying machine, a digital printer, and the like. More specifically, the present invention relates to a digital image data processing device capable of giving a three-dimensional shadow to an image.

<Prior Art> For example, taking a digital copying machine as an example,
Some recent digital copiers, when copying a document image shown in FIG. 14 (A), can give a three-dimensional shadow to the copy image as shown in FIG. 14 (B).

In a digital copying machine, to perform such three-dimensional shadowing, an arrow X indicates a main scanning direction which is a reading direction of a line sensor, and an arrow Y indicates a sub-scanning direction which is a relative moving direction of a line sensor and a document. Then, it is necessary to provide a memory having a capacity corresponding to the width of the shadow in the sub-scanning direction Y, for example, a line memory for 40 lines.

This is because, for one-line document image data read by the line sensor, data for the width of the shadow had to be held for shadowing.

<Problems to be Solved by the Invention> As described above, in order to perform three-dimensional shadowing with a conventional digital copying machine, a line memory capable of storing multiple lines is required to store shadow data in the sub-scanning direction Y. However, there is a disadvantage that the cost of the line memory is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital image processing apparatus capable of solving the above-mentioned disadvantages and performing a shadowing process using a one-line memory.

<Means for Solving the Problems> The invention according to claim 1 for achieving the above object,
1 for storing one line of digital image data
Line memory means, feedback means for feeding back output data of the one-line memory means to the one-line memory means, provided in the feedback means, and subtracting a predetermined value from the output data of the one-line memory means Subtraction processing means, data shift processing means for shifting digital image data by a predetermined amount in the memory area of the one-line memory means, and new one-line data sent to the one-line memory means. Arithmetic means for obtaining a logical OR for each pixel of digital image data and feedback data processed by the subtraction processing means and the data shift processing means, and using the obtained digital image data as input data for the one-line memory means Digital image data comprising: It is a management apparatus.

<Operation> According to the present invention, feedback data is created by changing the output data of the one-line memory means by a predetermined value, and the created feedback data and the new data sent to the one-line memory means are generated. The logical sum with the digital image data for one line is obtained for each pixel. Then, the obtained image data is input to the one-line memory means.

As a result, the image data given to the line memory means becomes image data which has been subjected to a shadowing process based on the image data of the immediately preceding line, and an image output based on this image data has a desired shadowing. Is done.

Further, the provision of the data shift processing means makes it possible to increase or decrease the shift amount of the image data in the memory area of the one-line memory means to change the inclination of the shadow.

<Embodiment> Hereinafter, an embodiment of the present invention will be described in detail using a digital copying machine as an example.

Principle of three-dimensional shadowing When an original image is read by a CCD line image sensor in a digital copying machine, data read from the CCD line image sensor is converted into a two-dimensional image at an image sensor reading pitch (for example, 400 dots / inch). It is divided into pixels in the array and processed.

In other words, if the reading direction (length direction) of the CCD line image sensor is the main scanning direction X and the relative displacement direction between the CCD line image sensor and the document image is the sub-scanning direction Y, the reading is performed by the CCD line image sensor. The original image data can be combined as a set of a two-dimensional array of (Xi, Yj) as shown in FIG.

The read data of the CCD line image sensor as shown in FIG. 1 is composed of one line ((X ₀ , Yj) to (Xm, Y
j): However, j is given to the processing circuit in a time series for every 0 to n).

 Next, a specific example will be described.

The original image shown in FIG.
Consider reading with. In FIG. 2, X indicates the main scanning direction, and Y indicates the sub-scanning direction. When the original image shown in FIG. 2 is read by the CCD line image sensor 20, it is recognized as, for example, an image of a large number of pixels as shown in FIG. In this case, the read output data of the CCD line image sensor 20 is shown in FIG. 4 (Xi, Y
j) is a set of two-dimensional arrays.

In this case, the black data of the original image in FIG.
F "(hexadecimal notation), white data is read as" 00 "(hexadecimal notation). In other words, the original image shown in FIG. 2 is binary with" FF "and" 00 ". It can be said that it was made.

Next, when the data shown in FIG. 4 is output in chronological order from the CCD line image sensor 20, a processing procedure for processing this data to perform three-dimensional shadowing will be described.

(1) A line memory having a memory area for one line is prepared.

Here, a line memory having a memory area equal to the number of read pixels of the CCD line image sensor 20 (the number of read pixels in the main scanning direction X) is prepared. For example, FI
An FO (first in first out) memory or a random access memory may be used.

For convenience, the memory area of the line memory is numbered as (Z ₀ ) (Z ₁ )... (Zi)... (Zm) in comparison with the pixel number (Xi) of the CCD line image sensor 20. I do.

(2) Initialize all memory areas of the line memory to white data (00). That is, when expressed by an equation, Zi ← 00 (i = 0 to m).

(3) From the data in each memory area of the line memory,
A constant K (for example, K = 22h: where h is a code indicating that “22” is a hexadecimal number, the same applies to the following) is subtracted. This process is called process a.

In the case where the process a is performed, if the data in the memory area is white data (00), the data does not become less than that, so the data remains white data (00).

(4) Next, the data subjected to the processing a is shifted one by one in the 0 → m direction in the memory area. This shift process will be referred to as process b.

As a result of the processing b, the data in the memory area (Zm) is discarded, and the white data (00) is stored in the memory area (Z ₀ ).

(5) The data of the line memory that performed the process b and the CCD
The logical sum with the data of the first line (the line data shown in FIG. 4) given from the line image sensor 20 is obtained, and the result is stored again in the line memory. This process is called process c.

The above processing a to processing c can be expressed by the following equation: ZO ← (00) v (X ₀ , Y ₀ ) Zi ← (Zi ₋₁ −K) v (Xi, Y ₀ ) (where v: each bit (I = 1 to m) meaning the logical sum of

(6) Output the contents of the line memory that has been subjected to the process c to the printer unit. This process is called process d.

(7) Each time the CCD line image sensor 20 supplies one line of read data, the processes a to d described above are performed in synchronism with the read data, and until the output of the line data of Repeat until is completed.

If it is expressed by a mathematical formula, Z ₀ ← (00) v (X ₀ , Yj) Z _i ← (Zi ₋₁ −K) v (Xi, Yj) (where v: means a logical sum for each bit) Symbol i = 1 to m, j = 1 to n) Zi → image output (where i = 0 to m).

FIG. 5A and FIG. 5A show, in chronological order, how data a to d are applied to the data shown in FIG.
FIG. 5B and FIG. 5C. The processing proceeds from FIG. 5A to FIG. 5B to FIG. 5C.

5A, 5B and 5C, 1-d,
Data marked with 2-d, 3-d, 4-d ..., 22-d is output to the printer unit, and when it is put together, it becomes data in a two-dimensional array shown in FIG.

Of the data shown in FIG. 6, data excluding white data (00) is binarized into black data (FF) and intermediate data,
When it is printed out, an image with a three-dimensional shadow as shown in FIG. 7 is obtained.

 The above is the principle of three-dimensional shadowing in the present invention.

Specific Apparatus Next, a specific apparatus for realizing the above-described principle of three-dimensional shadowing will be described.

FIG. 8 is a schematic diagram of an entire configuration of a digital copying machine to which a digital image data processing device according to one embodiment of the present invention is applied.

The digital copying machine is provided with a contact glass 13 for setting a document 12 on an upper surface of a main body 11, and an openable / closable document cover 14 is provided thereon.

Above the inside of the main body 11, a light source 15 that is movable in the direction of arrow A1 along the lower surface of the contact glass 13 is provided. The light source 15 has a long cylindrical shape extending in a direction perpendicular to the plane of the drawing, and the reflected light of the document 12 illuminated by the light source 15 is transmitted to the CCD line image sensor 20 via mirrors 16, 17, 18 and a condenser lens 19. Given. Then, the original image is read by the image sensor 20.

The CCD line image sensor 20 is a sensor having a longitudinal shape extending in a direction perpendicular to the paper surface, and its length direction is the main scanning direction X.

The document image read by the CCD line image sensor 20 is provided from the image sensor 20 to an image processing circuit 21 and subjected to image processing described later. Then, the output of the image processing circuit 21 is supplied to the laser diode 22 to cause the laser diode 22 to emit light. The laser light output from the laser diode 22 is guided by the polygon mirror 23,
The light is supplied to the photosensitive drum 25 via 24.

Known members such as a charger 26, a developing device 27, a transfer / separation charger 28, and a cleaner 29 are arranged around the photoconductor drum 25. An electrostatic latent image is formed on the surface of the photoconductor drum 25 by an electrophotographic method. Once formed, the latent image is developed into a toner image. Then, the toner image is taken from the paper cassette 30, and is transferred to the paper supplied to the photosensitive drum 25 at a timing adjusted by the registration roller 31. Then, the sheet on which the toner image has been transferred is conveyed by the conveying belt 32 and sent to the fixing device 33. The toner image on the paper is fixed by the fixing device 33, and the copied paper on which the fixing is completed is discharged to the discharge tray.

FIG. 9 is a block diagram showing a configuration of a part related to image processing in the digital copying machine described above. The image data read by the CCD line image sensor 20 is supplied to the amplifier 41
, And is converted from analog data to digital data by the A / D converter 42 and supplied to the image processing circuit 21. Then, the output image data processed by the image processing circuit 21 is output to the laser diode 22 to cause the laser diode 22 to emit light.

Further, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. The reference clock CK output from the clock oscillator 46 is supplied to the timing generation circuit 44, the A / D converter 42, and the image processing circuit 21, and the line synchronization signal Hs output from the line synchronization signal generation circuit 45
ync is supplied to the image processing circuit 21 and the timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. That is, the CCD line image sensor 20 is
The operation is performed in synchronization with the reference clock CK output from the CPU, and the operation is performed in synchronization with each line by the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. Similarly, the image processing circuit 21 operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is under the control of a CPU 47 for controlling the entire operation of the digital copying machine.

Next, a more detailed configuration of the image processing circuit 21 shown in FIG. 9 will be described.

FIG. 10 is a block diagram showing a circuit configuration of the image processing circuit 21. The image processing circuit 21 includes an input binarization circuit 51 to which image data converted into digital data is provided,
An OR circuit 52 to which the output of the input binarization circuit 51 is provided;
A FIFO memory 53 to which an output of the OR circuit 52 is given;
An output binarizing circuit 54 to which the output of the memory 53 is given;
And a subtraction circuit 55 to which an output of the memory 53 is provided. Then, the output of the subtraction circuit 55 is given to the OR circuit 52, and the OR circuit 52 performs an OR operation with the output of the input binarization circuit 51. The output of the OR circuit 52 is provided to the FIFO memory 53 as described above.

The FIFO memory 53 is a line memory having a memory area equal to the number of read pixels of the CCD line image sensor 20.

Further, a FIFO timing circuit 56 for controlling the FIFO memory 53 is provided. The clock CK output from the clock oscillator 46 is input to the input binarization circuit 5.
1. The operation clock is supplied to the OR circuit 52, the output binarization circuit 54 and the FIFO timing circuit 56.

The FIFO timing circuit 56 is supplied with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45 described above.

Further, the image processing circuit 21 is provided with a control CPU 57, which controls the input binarization circuit 51, the subtraction circuit 55, and the output binarization circuit 54.

Next, the operation of the circuit of FIG. 10 will be described with reference to the explanation of the principle of the three-dimensional shadowing.

By controlling the input binarization circuit 51 by the control CPU 57, the memory area of the FIFO memory 53 is initialized to white data (00) (Explanation of the principle of three-dimensional shadowing (2)
Next, when the digital image data is supplied to the input binarization circuit 51, the input binarization circuit 51 binarizes the digital image data one dot at a time based on the clock CK, and converts it into a logical sum circuit. Give to 52.

On the other hand, the output of the FIFO memory 53 is given to the subtraction circuit 55,
The subtraction circuit 55 subtracts a predetermined constant K (for example, K = 22h) given by the control CPU 57 from the output of the memory 53. Therefore, the data after the subtraction is supplied to the OR circuit 52.

The OR circuit 52 performs an OR operation on the data supplied from the input binarization circuit 51 and the data supplied from the subtraction circuit 55.

Then, in response to the next clock CK, the output of the OR circuit 52 is stored in the FIFO memory 53.

Through the above processing, the processing a, the processing b, and the processing c described on the principle of the stereoscopic shadowing are performed.

The data stored in the FIFO memory 53 is supplied to the output binarizing circuit 54 in the order of first-in first-out, binarized into document data and shadow data, and supplied to the laser diode 22 as print output data. That is, the process d is performed.

FIG. 11 is a block diagram showing a more specific configuration example of the circuit of FIG.

 Next, the circuit of FIG. 11 will be described.

The input binarization circuit 51 of the image processing circuit 21 includes an image data latch circuit 511 that performs a latch operation in response to the clock CK.
A CPU data latch circuit 512 for latching binarized threshold data provided from the control CPU 57;
An 8-bit comparison operation circuit 513 can be used. The 8-bit comparison operation circuit 513 performs a binarization process by comparing the output of the image data latch circuit 511 with the output of the CPU data latch circuit 512, that is, the threshold value.

The OR circuit 52 is, for example, an 8-bit OR circuit.
It can be configured by connecting a 521 and an 8-bit gate circuit 522 in series. The 8-bit gate circuit 522 is a FIFO
This is a circuit necessary for initializing the memory 1.

The subtraction circuit 55 includes, for example, an 8-bit addition circuit 551.
And the CPU data latch circuit 552. If the output data of the control CPU 57 is changed, the output of the latch circuit 552 is changed, so that the subtraction constant can be changed.

Further, the output binarization circuit 54 is an 8-bit comparison operation circuit.
541 and the CPU data latch circuit 542.

In the circuit shown in FIG. 11, the FIFO timing circuit 56
(See FIG. 10) is shown integrated with the FIFO memory 53.

Instead of the specific circuit example of FIG. 11, the image processing circuit 21
It may be as shown in FIG.

 Next, the circuit of FIG. 12 will be described.

An image data latch circuit 511 instead of the input binarization circuit 51
, And the image data is processed as multi-valued data. For this purpose, an 8-bit comparison operation circuit 523 for selecting the maximum value, an 8-bit gate circuit 524 for selectively passing the data supplied from the image data latch circuit 511, and a selective passage for the subtraction result data And an 8-bit gate circuit 526 required to initialize the FIFO memory 53.

Further, the subtraction circuit 55 has a RAM 553 for generating a subtraction value function.
, A CPU data latch circuit 554 for holding data to be written as a subtraction value function to the RAM 553, an 8-bit data selector 555 for selecting whether to initialize or operate the RAM 553, and holding initial performance data. And a CPU latch circuit 556.

Further, the FIFO timing circuit 56 can be constituted by a programmable shift circuit 561 for shifting the read timing and a CPU data latch circuit 562 for holding the shift amount. By changing the shift amount of the shift circuit 561, the shift amount of the process b can be changed.

Further, the output binarization circuit 54 has an 8-bit comparison operation circuit 543 for performing dither binarization, a RAM 544 for holding a dither matrix, and a circuit for selecting whether to initialize or execute the dither matrix. An 8-bit data selector 545, a counter 546 for counting a line synchronization signal to generate an upper address of the RAM 545, a counter 547 for counting a clock and generating a lower address of the RAM 545, and a RAM of a dither matrix. A configuration including a CPU data latch circuit 548 for holding an initialization address and a CPU data latch circuit 549 for holding initialization data of a dither matrix RAM can be employed.

Description of Modified Examples Next, various modified examples of this embodiment will be described.

In FIG. 10, the output of the FIFO memory 53 is binarized by the output binarization circuit 54 to be divided into image data (FF) and shadow data with three-dimensional shadows. May be provided to make the output multi-valued.

When the output is multi-valued, gradation (gradation) can be given to stereoscopic shadowing.

Further, in the process a in the subtraction circuit 55, the length of the solid shadow can be changed by changing the constant K to be subtracted. Change of constant K is control CPU5
You can do it by 7.

By setting the shift amount of shifting the data in the process b one by one to 2, 3, 4,... Or 0 other than “1”, the inclination of the three-dimensional shadow can be changed.

In this case, if the data shift means is omitted or the data shift amount in the data shift means is set to "0", the shadowing occurs only in the sub-scanning direction. Conversely, a shadow approaching the main scanning direction X can be obtained by increasing the shift amount. Control CP also changes this shift amount
If the shift amount is changed by the control CPU 57, for example, the CPU in the circuit of FIG.
The value of the data latch circuit 562 changes.

Further, in the process a, without setting the subtraction value K as a constant,
It may be a value depending on the data value to be subtracted.
That is, K which has a specific relationship with the data value Zi to be subtracted.
It may be a subtraction value given by a function (Zi).

In this way, the gradation can be changed in the case where the solid shadow has a gradation. For example, the gradation does not change in order according to the length of the shadow, but the change in the gradation can be changed.

Furthermore, as mentioned in the description of the circuit in FIG. 12, a circuit that performs a maximum value selection operation may be used instead of the OR circuit 52.

By doing so, even when the input data is not binary data but multivalued data, stereoscopic shadowing can be performed.

Further, in the description of the principle of three-dimensional shadowing, it has been described that data processing is performed for each line, but data processing may be performed for each pixel.

That is, the processes a to d described in the principle of the stereoscopic shadowing are performed for each pixel.

Further, by selecting the output of the process d, it is also possible to perform linear solid shadowing as shown in FIG.

Further, the present invention can be applied to a full-color image forming apparatus, for example, a full-color copying machine, to colorize a gradation with a three-dimensional shadow.

Further, in the above-described embodiment, an example in which the FIFO memory is used as the one-line memory has been described, but a random access memory may be used instead of the FIFO memory.

<Effect of the Invention> Since the present invention is configured as described above, a digital image data processing apparatus capable of performing processing such as three-dimensional shadowing by using storage means having a one-line memory area is provided. Can be provided.

Further, according to the present invention, since processing can be performed by using a storage unit having a memory area of one line, a small and inexpensive image forming apparatus can be provided by applying the present invention to an image processing apparatus. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing document image data read by a CCD line image sensor as a set of two-dimensional arrays. FIG. 2 is a diagram illustrating an example of a document image read by a CCD line image sensor. FIG. 3 is a diagram showing an image recognized by the CCD line image sensor when the original image of FIG. 2 is read by the CCD line image sensor. FIG. 4 is a diagram showing read output data of a CCD line image sensor corresponding to the image of FIG. FIGS. 5A, 5B, and 5C are diagrams showing, in chronological order, the manner in which processing a to processing d is performed on the data shown in FIG. FIG. 6 shows 1-d, FIG. 5A, FIG. 5B and FIG.
It is the figure which expressed the data to which 2-d, ..., 22-d was attached by a two-dimensional array. FIG. 7 is a diagram showing an image shaded three-dimensionally based on the data shown in FIG. FIG. 8 is a schematic diagram of an entire configuration of a digital copying machine to which a digital image data processing device according to one embodiment of the present invention is applied. FIG. 9 is a block diagram showing a configuration of a part related to image processing in the digital copying machine. FIG. 10 is a block diagram showing a configuration of the image processing circuit. FIG. 11 is a block diagram showing a more specific configuration example of the circuit of FIG. FIG. 12 is a block diagram showing another more specific configuration example of the circuit of FIG. FIG. 13 is a diagram showing an example of a change in solid shadowing. FIGS. 14A and 14B are diagrams for explaining three-dimensional shadowing in a conventional digital copying machine, in which FIG. 14A shows an original image, and FIG. 14B shows a copy image when the original image is subjected to three-dimensional shadow copying. It is. In the figure, 20 ... CCD line image sensor, 21 ...
Image processing circuit, 45 ... 1-line synchronization signal generation circuit, 46 ...
... 1 dot clock oscillator, 51 ... Input binarization circuit, 52
.., An OR circuit, 53, a FIFO memory, 54, an output binarization circuit, 55, a subtraction circuit, 56, a FIFO timing circuit.

Claims (1)

(57) [Claims] 1. One-line memory means for storing digital image data for one line, feedback means for feeding back output data of the one-line memory means to the one-line memory means, and feedback means Subtraction processing means for subtracting a predetermined value from output data of the one-line memory means; data shift processing means for shifting digital image data by a predetermined amount within a memory area of the one-line memory means; A new one sent to the one-line memory means
A logical OR for each pixel of the digital image data for the line and the feedback data processed by the subtraction processing means and the data shift processing means is obtained, and the digital image data obtained by this is input to the input data of the one-line memory means. A digital image data processing device, comprising: