JPH04153783A - Digital image processor - Google Patents

Abstract

PURPOSE:To attain the repetitive processing of an image without using a memory of large capacity by providing a repeat data generating means and a composing means which composes the image data inputted to an input means and the repeat data outputted from the repeat data generating means and outputs the composite data. CONSTITUTION:The output of a repeat data generating circuit 302 is given to an OR circuit 306 and the original image data is given to the circuit 306 respectively. Thus the circuit 306 composes the original image data and the output of the circuit 302. Meanwhile the original image data inputted to an image processing circuit 21A is given to an X direction repeat selection circuit 307 via the circuit 306. The circuit 307 is switched by the output of an X direction range detecting circuit 105 and therefore selects and outputs the A input data when the output of the circuit 105 is equal to '1', i.e., active. Thus an image can be repetitively processed by a memory of small capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an image processing device that digitally processes image data. In particular, the present invention relates to an image processing apparatus for digital image forming apparatuses such as digital copying machines, digital printers, and digital facsimiles.

<Prior Art> Taking a digital copying machine as an example, some recent digital copying machines repeatedly output image data of a specific area so that the image of the specific area is displayed in both the main scanning direction and the sub-scanning direction. There are copying machines with a so-called repeat function that can produce aligned copies.

In conventional digital copying machines, in order to realize such a repeat function, a relatively large capacity image memory is required to store images to be repeated.

<Problems to be Solved by the Invention> As described above, in order to realize the repeat function, it is necessary to provide an image memory with a large capacity, which has the disadvantage of increasing the cost of the memory.

Other digital image processing devices similarly have the drawback of requiring a large capacity memory in order to add a repeat function.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital image processing apparatus that can eliminate the drawbacks of the prior art and perform repeat processing without using a large capacity memory.

Means for Solving the Problems> The present invention provides a digital image processing device for processing given digital image data, where the digital image data is composed of a plurality of line data lined up. an input means into which the digital image data is sequentially inputted in chronological order; a method for determining whether or not subsequent image data has changed with respect to preceding image data input to the input means; and outputting when a change has occurred; a data change point detecting means for deriving the image data, an address assigning means for sequentially assigning addresses to the image data input to the input means, and outputting a shift amount necessary for repeat processing the image data, A shift amount output means in which the shift amount includes a shift amount in the line arrangement direction, and a storage means for storing addresses in the same order as the storage order.
Address storage means capable of sequentially outputting stored addresses, repeat address calculation means for calculating a repeat address by adding the shift amount output from the shift amount output means to the address output from the storage means, and address assignment. A match signal output means that compares the address given by the means with the address calculated by the repeat address calculation means and outputs a match signal when the two match, each time a match signal is output from the match signal output means. A read control means updates the address output from the address storage means to a new one, and an address is assigned each time there is an output from the data change point detection means, and each time a match signal is output from the match signal output means. write control means for storing the current address given by the means in the storage means;
repeat data generation means for always deriving either a first level or a second level binary output and inverting the output level in response to the coincidence signal; and image data input to the input means and The present invention is characterized in that it includes a synthesizing means for synthesizing and outputting the repeat data output from the repeat data generating means.

Further, in the present invention, the digital image processing device is further provided at the output stage of the combining means, so that when each line data is output, a part of the line data is repeatedly output in the line length direction. The invention is characterized in that it includes a line longitudinal direction repeating means.

Furthermore, in the digital image processing apparatus according to the present invention, the repeat data generation means further converts the output of at least one of the first level and the second level into an output of an intermediate level between the first level and the second level. It is characterized in that it includes intermediate level signal output means for converting into an output.

Effects> According to the present invention, when a change point occurs in input image data, an address corresponding to the change point is stored in the storage means. Then, an address obtained by adding a predetermined shift amount to the address read from the storage means is compared with the address of the input image data at that time, and when both addresses match, a match signal is output, Repeat data is generated. Further, the address at which the coincidence signal is output is stored in the storage means. This specifies the address for repeatedly outputting the image data.

<Embodiment> An embodiment of the present invention will be described below by taking a digital copying machine as an example.

FIG. 8 is a schematic diagram of the entire digital copying machine to which an image processing apparatus according to an embodiment of the present invention is applied.

The digital copying machine is equipped with a contact glass 13 for setting a document 12 on the top surface of a main body 11, and a document cover 14 that can be opened and closed is provided above the contact glass 13.

A light source 15 is provided inside and above the main body 11 and is movable along the lower surface of the contact glass 13 in the direction of arrow A1. The light source 15 has a long cylindrical shape extending perpendicular to the paper surface, and the document 12 illuminated by the light source 15
The reflected light is reflected by mirrors 16, 17, 18 and condenser lens 1.
9 to the CCD line image sensor 20. Then, the image sensor 20 reads the original image.

The CCD line image sensor 20 is a longitudinal sensor extending perpendicularly to the plane of the paper, with its length direction being the main scanning direction X, and reads image data line by line.

The original image data read by the CCD line image sensor 20 is provided to an image processing circuit 21 and subjected to image processing described below. The output of the image processing circuit 21 is then applied to the laser diode 22, causing the diode 22 to emit light. The laser light output from the laser diode 22 is scanned by a polygon mirror 23 and applied to the photosensitive drum 25 via the mirror 24.

Known members such as a charging charger 26, a developing device 27, a two-transfer separation charger 28, and a cleaner 29 are arranged around the photoreceptor drum 25, and an electrostatic latent image is formed on the surface of the photoreceptor drum 25 by an electrophotographic method. The latent image is formed and the latent image is developed into a toner image.

Then, the toner image is taken in from the paper cassette 3o, and is transferred onto the paper applied to the photoreceptor drum 25 with the timing adjusted by the registration row 231. Then, the paper onto which the toner image has been transferred is transported by a transport belt 32 and sent to a fixing device 33. The fixing device 33 fixes the toner image on the paper, and the copied paper on which the fixing has been completed is discharged to the discharge tray 34.

FIG. 9 is a block diagram showing the configuration of image processing related parts in the digital copying machine described above.

The original image data read by the CCD line image sensor 20 is amplified by the amplifier 41 and then sent to the A/D converter 4.
2, the analog data is converted into digital data and provided to the image processing circuit 21. The output image data processed by the image processing circuit 21 is then applied to the laser diode 22, causing the laser diode 22 to emit light. Furthermore, a clock oscillator 46 and a line synchronization signal generation circuit 45 are provided. Clock oscillator 46
The reference clock CK output from the timing generation circuit 44, the A/D converter 42 and the image processing circuit 21
The line synchronization signal Hsync supplied to the image processing circuit 2 and output from the line synchronization signal generation circuit 45 is
1 and to the timing generation circuit 44.

Here, the timing generation circuit 44 is for controlling the image data reading timing and the image data output timing of the CCD line image sensor 20. In other words, the CCD line image sensor 20 operates in synchronization with the reference clock CK output from the R072 oscillator 45, and synchronizes each line with the line synchronization signal Hsync output from the line synchronization signal generation circuit 45. perform the operation. The image processing circuit 21 similarly operates in synchronization with the reference clock CK and the line synchronization signal Hsync.

Further, the image processing circuit 21 is placed under the control of a CPU 47 for controlling the overall operation of the digital copying machine.

Next, as a specific example of the configuration of the image processing circuit 21 shown in FIG. 9, the image processing circuits 21A and 21B will be described below.

FIG. 1 is a block diagram showing the configuration of an image processing circuit 21A according to an embodiment. First, this image processing circuit 21
If we explain each component included in A block by block,
It is as follows.

101...X coordinate counter This counter is a circuit for counting the reference clock CK given from the clock oscillator 46 (see FIG. 9) and calculating the coordinate X in the X direction, which is the main running direction. .

The X coordinate counter 101 is connected to the line synchronization signal generation circuit 45
Line synchronization signal Hsyn given from (see Figure 9)
It is reset to 1 by c. Thereby, the X coordinate counter 101 calculates the coordinate X of the predetermined starting position for each line.

03...First-in first-out memory for X coordinate (FIFO memory for X coordinate) X coordinate counter 101
This is a memory for storing count values.

04...X coordinate comparison circuit This circuit compares the coordinate value stored in the X coordinate FIFO memory 103 with the current coordinate X, and outputs a match signal when they match.

105...X direction range detection circuit The coordinate X is within the range set in the CPU 501, which will be described later.
This is a circuit for determining whether or not the

201...Y coordinate counter This counter counts the line synchronization signal Bsync given from the line synchronization signal generation circuit 45 (see FIG. 9) and calculates the coordinate y1 in the Y direction, which is the sub-scanning direction, that is, the line number y. This is a circuit for calculation.

The Y coordinate counter 201 is reset to 1 by a vertical synchronization signal Vsync, which is a reading start signal for each page.

203...Y-coordinate first-in-first-out memory (Y-coordinate FIFO memory) Y-coordinate counter 20
This is a memory for storing a count value of 1.

202...Y-coordinate addition circuit This is a circuit for adding the shift amount KV in the Y direction (given as B input) to the output value of the Y-coordinate FIFO memory 203 (given as A input).

204...Y coordinate comparison circuit This circuit compares the output value of the Y coordinate addition circuit 202 and the current coordinate y, and outputs a coincidence signal when they match.

205...Y direction range detection circuit The coordinate y is within the range set in the CPU 501, which will be described later.
This is a circuit for determining whether or not the

301 Coordinate matching logical product circuit This circuit is a circuit that calculates the logical product of the matching signals of the X coordinate comparison circuit 104 and the Y coordinate comparison circuit 204.

302...Repeat data generation circuit This circuit is constituted by a D flip-flop in this example.

The signal output from the coordinate matching AND circuit 301 is a change point signal of repeat data. Therefore, in this flip-flop 302, by using the change point signal as a clock input, the output signal changes from the first level (for example, low level) to the second level (for example, high level) or from the second level to the first level every clock. Invert the level and output repeat data.

The repeat data generation circuit 302 generates a line synchronization signal Hs.
ync, and the output is set to the initial state for each line, that is, the first level (low level) in this example.
will be returned to.

306...OR circuit This circuit is a circuit for calculating the OR between the original image data and the repeat data in the Y direction.

307...X-direction repeat selection circuit This circuit is necessary for repeating image data in the
IFO memory input or FI for X direction repeat
The data output from the FO memory is transferred to the FIFO again.
This is a circuit for selecting whether to use memory manually or not.

308...First-in-first-out memory for X-direction repeat (FIFO memory for X-direction repeat) Memory necessary for repeating image data in the X-direction, and FIF for storing image data in the X-direction.
O memory.

401: Image data latch circuit A circuit for sequentially latching minimum unit input image data (pixels) expressed in binary levels of high level or low level in synchronization with a reference clock.

402... Change point extraction circuit This is a circuit that outputs a signal when the input pixel changes, for example, from black to white (from high level to low level) or from white to black (from low level to high level).

More specifically, the current pixel is compared with the previous pixel latched by the image data latch circuit 401 one clock ago, and if the two do not match, the current pixel is changed from the previous pixel. Therefore, it is a circuit that outputs a change point signal.

403...Logic product circuit In this image processing circuit, the change point signal output from the change point extraction circuit is used as the write signal WCK of the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203. If it is outside the predetermined range, the AND circuit 403 prevents the write signal WCK from being output, thereby prohibiting the write.

That is, the aforementioned X direction range detection circuit 105 and Y
The direction range detection circuit 205 detects the current coordinates (x, y
) is within a predetermined range, the gate is opened and the change point signal passes through the AND circuit 403.

Next, the operation of the image processing circuit 21A shown in FIG. 1 will be explained with reference to specific image data.

Consider a case in which the data read by the computer (see FIG. 9) is the image data shown in FIG.

In FIG. 2, the horizontally extending X direction is the main scanning direction, and the vertically extending Y direction is the sub-scanning direction. Furthermore, in FIG. 2, one square indicated by a small square is the minimum unit of data, that is, a pixel. A white square indicates a state where the pixel is 0 (low level), and a black square indicates a state where the pixel is 1 (high level).

Further, the numerical values attached along the upper side and the left side represent the X coordinate value and Y coordinate value of each pixel, respectively.

Consider a case where image processing is performed on the image data shown in FIG. 2 without shifting the image at all in the X direction, but by shifting the amount Ky-12 in the Y direction. It is also assumed that image processing is performed on an image in an area of coordinates (1 to 10) in the X direction and coordinates (1 to 12) in the Y direction.

The image data read by the CCD line image sensor 20, amplified by the amplifier circuit 41, and converted to a digital signal by the A/D converter 42 is time-series, pixel by pixel, as follows: D (1, 1), D ( 2,1), D (3,1
)D (1,2), D (2,2), D (3,2
)...D (1,3), D (2,3), D (3
, 3)... flow into the image processing circuit 21A.

Here, D (x, y) indicates image data at the coordinates (x, y), and this image data is a pixel and has a value of "0" or "1".

The image processing circuit 21A shown in FIG. 1 is reset by a line synchronization signal Hsync and a vertical synchronization signal Vsync immediately before image data is input.

Therefore, the image data latch circuit 401 has been reset, and its Q output is "0".

Also, immediately before the first reference clock CK (hereinafter simply referred to as "clock CKJ") is given, the change point extraction circuit 4
The Q output "0" of the image data latch circuit 401 is set to the A input of 02, and the first image data D (1, 1) is set to the B input. Therefore, since the eight-person power data B input data is 〇, the change point extraction circuit 40
The output of 2 is inactive.

Furthermore, at this point, both the X coordinate counter 101 and the Y coordinate counter 201 remain reset to "1".

Next, when the first clock CK is applied from the clock oscillator 46 (see FIG. 9), the image data latch circuit 40
1, image data D (1, 1) is latched.

Therefore, immediately before the next clock CK is applied, the image data latch circuit 40
Image data D (1°1) latched at 1 is set, and image data D (2°1) is set to the B input.

Since these image data D(1°1) and D(2,1) are both "0" as shown in FIG. 2, the output of the change point extraction circuit 402 is inactive.

At this time, the X coordinate counter 101 counts one clock CK and becomes "2", and the second counter 201 counts "2".
1" remains.

Similarly, every time the clock CK is applied, the image data latch circuit 401 latches the image data D (x-1, y), and the change point extraction circuit 402 latches the image data D (x, y) at the change point. It is determined whether or not.

The first change point in the image data D (x, y) occurs at D (4, 1).

At this time, D(3,1) latched by the image data latch circuit 401 is set to the A input of the change point extraction circuit 402, and D(4°1) is set to the B input.

Here, since D (3,1) is 'O' and D (4,1) is '1', the output of the change point extraction circuit 402 becomes active.

Further, the values of the X coordinate counter 101 and the Y coordinate counter 102 at this time are "4" and "1", respectively.

At this time, "4" is given to the C input of the X direction range detection circuit 105, and "1" is given from the CPU 501 to the A input and B input of the X direction range detection circuit 105.
” and “10”.

Furthermore, since "1" is given to the C input of the Y direction range detection circuit 205, this also applies to the A input and B input of the same circuit 205.
It is determined that the value is within the range of "1" and "12" given to the input.

Therefore, the outputs of the X-direction range detection circuit 105 and the Y-direction range detection circuit 205 are each "1", and the output of the change point extraction circuit 402 passes through the AND circuit 403 and the OR circuit 404. The write signal WCK is applied to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 via the X-coordinate FIFO memory 10
3 takes in the count value "4" of the X coordinate counter 101, and the Y coordinate FIFO memory 203 takes in the count value "4" of the X coordinate counter 101.
The count value of 1 is taken in as "1".

Since the next image data D (5, 1) is also a change point, similar processing is performed and “5, 1” is stored in the X coordinate FIFO memory 103.
” is written in the Y-coordinate FIFO memory 203 rlJ.

In this way, the same processing is repeated one after another, and when the outputs of the X-direction range detection circuit 101 and the Y-direction range detection circuit 205 are each within the range of "1", a change point occurs in the image data, and the change point extraction circuit Every time the output of 402 becomes active, a write signal WCK is given to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203.
The count values of the X coordinate counter 101 and the Y coordinate counter 201 are respectively taken in.

As a result, when the coordinate y-line number-13 is reached,
In the coordinate FIFO memory 103, (4, 5, 3,
6,4,5,3,6,4,6゜4.6.4,6.4.6
, 4.6.4.8, 5° are stored, and (1, 1, 2, 2, 3, 3, 5, 5, 6, 6°) are stored in the Y coordinate FIFO memory 203. 7, 7
．． 8.8.9. 9. 10. 10. 11. 11
, 12. 12) is stored.

In other words, if expressed differently, the FIFO memory 10 for the X coordinate
3 and Y coordinate FIFO memory 203.
Coordinate values (4, 1) (5, 1) (3, 2) (6° 2) (4
,3)(5,3)(3,5)(6,5)(4,6)(6
,6)(4,7)(6,7)(4°8)(6,8)(4
,9)(6,9)(4,10)(6,10)(4,11
)(8,11)(5,12)(7,12) are stored.

Then, an X coordinate counter 101 and a Y coordinate counter 2
When the current coordinates counted by 01 become (4, 13), the X coordinate comparison circuit 10
4 and Y coordinate comparison circuit 204 output a coincidence signal.

To be more specific, the current coordinates to be counted are the coordinates (
4, 13), "4" is input to the B input of the X coordinate comparison circuit 104, and "4" is input to the B input of the Y coordinate comparison circuit 204.
13j is given.

On the other hand, the output of the X-coordinate FIFO memory 103 is "4" which was accumulated first, which
It is given to the A input of 04. Therefore, the eight inputs of the X coordinate comparison circuit 104 and the B input match, and the comparison circuit 10
A coincidence signal is output from 4.

Further, the output of the Y-coordinate FIFO memory 203 is the first stored “1”, and this output is given to the A input of the Y-coordinate addition circuit 203. Y coordinate addition circuit 202
A shift amount Ky-12 is given to the B input of the CPU 501. Therefore, the output of the Y-coordinate addition circuit 202 where the eight inputs and the B input are added becomes "13", and the output is given to the eight inputs of the Y-coordinate comparison circuit 204. Therefore, the A input and B input of the Y coordinate comparison circuit 204 match, and a match signal is output from the comparison circuit 204.

In this way, since the coincidence signals of both comparison circuits 104 and 204 are output simultaneously, the output of the coordinate coincidence AND circuit 301 becomes active as a result.

The output of the coordinate matching AND circuit 301 is fed back to the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203, and is given to each memory as a read signal RCK. Therefore, the first data in the X-coordinate FIFO memory 103 and the Y-coordinate FIFO memory 203 are discarded, and the next data "
5" and "1", that is, the coordinate values (5, 1) are set.

Further, since the output of the coordinate coincidence AND circuit 301 is given as a clock input to the repeat data generation circuit 302, the Q output of the repeat data generation circuit 302 changes from "0" to "1".

Furthermore, the output of the coordinate coincidence AND circuit 301 is sent to the X coordinate FIFO memory 103 and the Y coordinate through the OR circuit 404.
It is fed back to the coordinate FIFO memory 203 and given to each memory as a write signal WCK. Therefore, the current coordinate values (4, 13) at this time are two
The data is newly stored in the FIFO memories 103 and 203 consisting of a set of data.

In other words, the X coordinate value of the changing point and the Y coordinate value of the changing point + n
-Y direction shift amount KV (however, n-12, 3,...
) is a set of two FIFO memories 103 and 2.
It is stored in 03.

In this way, the "X coordinate of the change point" is sequentially added to the X coordinate FIFO memory 103 and the "Y coordinate of the change point+n-Ky" to the Y coordinate FIFO memory 203 as coordinate values. Therefore, the output of the coordinate coincidence AND circuit 301 becomes active for each coordinate value, and is supplied to the repeat data generation circuit 302.

Thereafter, when the current coordinates to be counted become the coordinates (5, 13), the output of the coordinate coincidence AND circuit 301 becomes active, and the output from the X coordinate FIFO memory 103 and the Y coordinate FIFO memory 203 is The read signal RCK is input, and the output of each memory 103 and 203 is the coordinate value ('3
．． 2), the Q of the repeat data generation circuit 302
The output is inverted from "1" to 0.

The same processing is performed thereafter.

Therefore, if the outputs of the repeat data generation circuit 302 are arranged in chronological order, they will be as shown in FIG. From a comparison between FIG. 2 and FIG. 3, it can be seen that the original image data is repeated in the Y direction by the repeat data generation circuit 302.

The output of the repeat data generation circuit 302 is given to the OR circuit 306, and since the OR circuit 306 is given the original image data, the output of the repeat data generation circuit 302 is input to the circuit 306. are synthesized. Therefore, the output is as shown in FIG.

On the other hand, the original image data input to the image processing circuit 21A is provided to the X-direction repeat selection circuit 307 via the OR circuit 306. The X-direction repeat selection circuit 307 is a circuit that is switched by the output of the X-direction range detection circuit 105, and when the output of the X-direction range detection circuit 105 is "1", that is, active, it selects and outputs the A person data.

Therefore, in the FIFO memory 308 for X-direction repeat,
The above-mentioned original image data is given. Since the clock CK is given to the X-direction repeat FIFO memory 308 as a write signal WCK and a read signal RCK, the original image data is sequentially stored in synchronization with the clock CK, and the original image data is stored in real time. Image data is output.

On the other hand, the X coordinate value X of the input original image data is x>1
When it becomes 0, the output of the X direction range detection circuit 105 becomes “0”
In other words, it becomes non-active.

Therefore, the X-direction repeat selection circuit 308 selects and outputs the B input data. In other words, the data read from the X-direction repeat FIFO memory 308 is given to the FIFO memory 308 again.

Therefore, the same image data is repeatedly written into the X-direction replay FIFO memory 308, and the X-direction coordinate (1
The image data of 10) to 10) are repeatedly output. In other words, X
Repeat processing of directional image data is performed.

Since the repeat processing in the X direction is performed not only on the original image data but also on the data provided from the repeat data generation circuit 302, the output of the image processing circuit 21A is as shown in FIG.

FIG. 6 is a block diagram showing the configuration of an image processing circuit 21B according to another embodiment of the invention.

A feature of the configuration of the image processing circuit 21B shown in FIG. 6 is that a series connection of a multi-value conversion circuit 303 and a dither comparison circuit 304 is inserted between the repeat data generation circuit 302 and the OR circuit 306. And the dither comparison circuit 304
The dither matrix memory 305 is connected to.

Data from the CPU 501 is given to the A input and B input of the multi-level conversion circuit 303, respectively. These data are, for example, 8-bit data, and are expressed in hexadecimal notation as "77h" and "00h" (h is 16
A code is given to indicate that it is expressed in decimal notation.

When the output "1" of the repeat data generation circuit 302 is given to the multi-value conversion circuit 303, the output of the multi-value conversion circuit 303 becomes "77h" which is the A input data. On the other hand, the output “0” of the repeat data generation circuit 302 is
3, the output of the multi-level conversion circuit 303 becomes "00h" which is B input data. Therefore, the multi-value conversion circuit 303 outputs halftone density data '77h' or white data '00h'.

The dither comparison circuit 304 compares the output from the multi-level conversion circuit 303, which is given as an input signal, and the output from the dither matrix memory 305, which is given as the B input.
When the 8-person data is smaller than the B input data, that is, when the output data of the multilevel conversion circuit 303 is smaller than the output data of the dither matrix memory 305, it outputs "1", otherwise it outputs "0". do.

That is, in the dither comparison circuit 304, the halftone density data "77
h'' is converted into dithered halftone data by referring to the dither matrix memory 305.

Therefore, it is synthesized by the OR circuit 306, and the selection circuit 307 for X-direction repeat and the FIF for X-direction repeat
The data output via the O memory 308 is a combination of original image data and halftone data that is repeated in the Y direction.
The result is the one shown in FIG. 7, which is repeated in the direction.

Note that in FIG. 7, for convenience, the halftone data is not expressed in dither, but simply expressed by reducing the minimum unit pixel.

Furthermore, in the case of a display device such as a CRT display that is capable of expressing the smallest unit of data (pixel) in multiple values rather than a digital copying machine, the output of the multi-value conversion circuit 303 may be fed as is to the OR circuit 306. , dither comparison circuit 304 and dither matrix memory 305 can be omitted.

In the circuit shown in FIG. 1 or FIG. 6, if image repeat only in the Y direction is required, it goes without saying that the selection circuit for X direction repeat and the FIFO memory for X direction repeat may be omitted.

Furthermore, although the above-described embodiments have been explained using a digital copying machine as an example, the digital image processing apparatus according to the present invention can be applied to digital image forming apparatuses other than digital copying machines, and can be applied to digital image forming apparatuses other than digital copying machines. It should be noted that it can also be used for equipment.

<Effects of the Invention> According to the present invention, it is possible to repeat images with a relatively small memory capacity compared to conventional devices.

In particular, image repeat in the sub-scanning direction can be realized with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a digital image processing circuit 21A according to an embodiment of the present invention. FIG. 2 is a diagram representing an example of current image data to be processed. FIG. 3 is a diagram showing an example of Y-direction repeat data obtained as a result of processing. FIG. 4 is a diagram showing an example of image data obtained as the output of the OR circuit 306. FIG. 5 is a diagram showing an example of output data of the image processing circuit 21A. FIG. 6 is a block diagram showing an example of the configuration of an image processing circuit 21B according to another embodiment of the invention. FIG. 7 is a diagram showing an example of output data of the image processing circuit 21B. FIG. 8 is a schematic diagram of the entire digital copying machine to which an image processing apparatus according to an embodiment of the present invention is applied. FIG. 9 is a block diagram showing the configuration of image processing related parts in the digital copying machine according to this embodiment. In the figure, 21, 21A, 21B...image processing circuit, 101...X coordinate counter, 103...X coordinate FIFO memory, 104...X coordinate comparison circuit, 105...
...X direction range detection circuit, 201...Y coordinate counter, 202...Y coordinate addition circuit, 203...FIFO memory for Y coordinate, 204...Y coordinate comparison circuit, 205
. . . Y direction range detection circuit, 301 . . . Coordinate matching AND circuit, 302 . . . Repeat data generation circuit, 303
. . . Multi-value conversion circuit, 304 . . . Dither comparison circuit, 30
5... Dither matrix memory, 306... OR circuit, 307... X-direction repeat selection circuit, 308
...FIFO memory for X direction repeat, 401...
Image data latch circuit, 402... change point extraction circuit,
403: AND circuit; 404: OR circuit.

Claims (1)

[Claims] 1. A digital image processing device for processing given digital image data, where the digital image data is composed of a plurality of line data lined up, in which the digital image data is An input means that inputs data sequentially in chronological order, and a data change that determines whether or not subsequent image data has changed with respect to the preceding image data that is input to the input means, and derives an output when a change occurs. A point detecting means, an address assigning means for sequentially assigning addresses to the image data inputted to the input means, and a shift amount necessary for repeat processing of the image data, and the shift amount includes a line. A shift amount output means that includes a shift amount in the alignment direction; an address memory means for storing addresses, and capable of sequentially outputting the stored addresses in the same order as the memory order; repeat address calculation means for calculating a repeat address by adding the shift amount output from the shift amount output means to the address output from the means; A match signal output means that compares and outputs a match signal when the two match, and a read that updates the address output from the address storage means to a new one each time a match signal is output from the match signal output means. control means; write control means for storing the current address assigned by the address assignment means in the storage means each time there is an output from the data change point detection means and every time a coincidence signal is output from the coincidence signal output means; , a repeat data generation means for always deriving either a first level or a second level binary output and inverting the output level in response to the coincidence signal, and image data input to the input means. and a synthesizing means for synthesizing and outputting the repeat data output from the repeat data generating means. 2. The digital image processing device according to claim 1 is further provided in the output stage of the synthesizing means, and when each line data is output, a part of the line data is repeatedly output in the line length direction. The present invention is characterized in that it includes a line longitudinal direction repeating means. 3. In the digital image processing apparatus according to claim 1, the repeat data generating means further converts the output of at least one of the first level and the second level into an intermediate level between the first level and the second level. The present invention is characterized in that it includes intermediate level signal output means for converting into a level output.