JPH0364166A - Picture processing unit - Google Patents

Abstract

PURPOSE:To prevent deterioration in the reduction processing of a picture data by applying a specific processing to a multi-value picture data being an output of a thinning means which thins an input or an output of an interpolation means in response to a minimum multiplication. CONSTITUTION:A sub scanning speed V is obtained in response to a designated read magnification m% and the sub scanning control at a speed V is applied to a motor 314, a CPU 301 reads various control parameters from a ROM table 316 in response to the designated multiplication of m% and gives them to a main scanning magnification processing circuit 307. Then a consecutive multi-value picture data is subject to interpolation processing in the reduction processing, a binary data corresponding to the multi-value picture data is calculated logically, each input or each output of the interpolation means and the arithmetic means is thinned in response to the reduction or magnification rate of m% and the multi-value picture data being an output of the thinning means is processed in response to the content of a binary data being an output of the thinning means. Thus, the picture processing unit is obtained, in which the deterioration in the picture quality attended with magnification is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that performs zero-magnification processing on image data.

[Prior Art] Conventionally, a main scanning magnification method using a memory has been proposed for this type of device.

[Problems to be Solved by the Invention] However, in conventional image data enlargement processing, gradation becomes rough due to mere enlarging of pixel data.
In image data reduction processing, image quality deteriorates due to missing pixel data.

Furthermore, the same thing can be said about edge processing on images, and the deterioration of image quality was significant.

The present invention eliminates the drawbacks of the prior art described above, and its purpose is to provide an image processing device that does not cause deterioration in image quality due to scaling.

[Means and Effects for Solving the Problems 1] In order to achieve the above object, the image processing apparatus of the present invention performs an interpolation process on continuous multivalued image data in an image processing apparatus that performs image data reduction processing. means for performing a logical operation on the binary data corresponding to the continuous multivalued image data; a thinning means for thinning each input or each output of the interpolating means and the calculating means according to a reduction magnification; The outline of the present invention is to include processing means for processing the multivalued image data output from the thinning means in accordance with the content of the binary data output from the pulling means. This allows proper images and edges to be reproduced even if pixel data is missing.

Preferably, the apparatus further includes an extracting means for extracting edge information from continuous multivalued image data and converting the extracted edge information into binary data to be input to the arithmetic means.

As a result, a reduced copy that is faithful to the original image can be obtained.

Preferably, the arithmetic means performs an AND operation, a logical OR operation, or any one selection operation on the corresponding binary data.

This allows for various edge processing methods.

Particularly in the case of reduction, a logical sum operation is preferable to prevent loss of edge information.

Further, in order to achieve the above object, the image processing device of the present invention includes an interpolation unit that performs interpolation processing on continuous multi-valued image data, in an image processing device that performs image data enlargement processing;
a calculation means for logically performing a logical operation on binary data corresponding to the continuous multivalued image data; an overlapping means for duplicating each input of the interpolation means and the calculation means according to an enlargement magnification; and binary data output from the calculation means. The outline of the present invention is to include processing means for processing the multivalued image data output from the interpolation means according to the contents of the interpolation means. This allows for smooth image enlargement and appropriate edge processing.

Preferably, the apparatus further includes an extracting means for extracting edge information from continuous multivalued image data and converting the extracted edge information into binary data to be input to the arithmetic means.

As a result, an enlarged copy that is faithful to the original image can be obtained.

Preferably, the arithmetic means performs an AND operation, a logical OR operation, or any one selection operation on the corresponding binary data. This allows for various edge processing methods.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic cross-sectional view of the image processing device of the embodiment. In the figure, 201 is an image league, which electrically reads a document image and performs scaling processing on the read image data. A printer 203 prints image data sent from the image league 201.

In the image reader 201, a document 204 is placed on a document table glass 203, and the document presser 200 is pressed against the document 204. An image of the original 204 is illuminated by a lamp 205, and the reflected light is guided by mirrors 206, 207 and 208, and is imaged on a CCD 211 via a lens 210.

When reading the original 204, the lamp 205 and mirror 2
Unit 06 has a speed V and mirrors 207 and 20
The units 8 are each mechanically scanned in the sub-scanning direction at a speed of 1/2v, and by making this scanning speed V variable, variable-magnification reading in the sub-scanning direction is performed.

That is, if the value of the scanning speed V when the reading magnification is 10'O% (same magnification) is Vo, then the scanning speed ■ when the reading magnification is m% is (
1) Determined by formula.

00 V=XV, (1) The signal processing unit 216 also performs magnification processing in the main scanning direction and sends the resulting image signal to the printer 203.

In the printer 203, the laser driver 236 drives the semiconductor laser element 217 ON10FF based on the image signal from the image reader 201. The laser beam emitted from the semiconductor laser element 217 passes through the polygon mirror 21
8. An image is formed on a photosensitive drum 222 via an f-θ lens 219 and mirrors 220 and 221. Photosensitive drum 222
The image formed thereon is developed and visualized using a known electrophotographic process. That is, the electrostatic latent image on the photosensitive drum 222 is developed with toner by the developing device 223. On the other hand, paper is supplied from the paper cassette 224 or 225, and after being timed by the registration rollers 226, the toner image is transferred onto the photosensitive drum 222, and further transported by the transport system 227, and then transferred to the fixing unit 228. After the image is fixed at , it is output.

Figures 13A to 13D are diagrams illustrating an example of image processing in the embodiment, where (A) is an original image, (B) is a reduced copy image, and (C) is an equivalent image. Double copy image, same figure (D)
1 and 2 respectively show examples of enlarged copy images.

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment. In the figure, a CPU 301 performs main control of the image processing apparatus. That is, first input the specified reading magnification m% from the operation unit 312 via the I10 controller 311,
The sub-scanning speed V is determined by equation (1) according to the magnification m%. Then, sub-scanning control of the motor 314 is performed using the speed V via the I10 controller 311 and motor driver 313. In addition, the CPU 301 inputs the specified magnification m.
%, various control parameters are read from the ROM table 316 and provided to the following main scanning magnification processing circuit.

That is, the image signal read by C0D211 is sent to the amplifier (A
mp) 304, and is amplified by an A/D converter (A/D) 30.
5, each signal is converted into an 8-bit digital signal (multivalued image data) ranging from white (=255) to black (=O). A character edge determination unit 306 extracts edge portions of characters, line drawings, etc. in multivalued image data, and outputs the extracted 1-bit EDG data and the multivalued image data (8 bits). The scaling unit 307 converts the pair of EDG data and multivalued image data into R
Writing and reading are performed alternately on the AMs 309 and 310, and along with the control of the address controller 302, main scanning magnification processing to be described later is performed. The scaling unit 307 also performs interpolation processing on image data. The filter 310 performs filter processing on the scaled image data, and its output is input to the laser driver 236 to obtain an output image 315.

FIG. 3 is a block diagram of the magnification changing section 307 of the embodiment. In the figure, the input to the scaling section 307 is a total of 9 bits consisting of 8 bits of multivalued image data sent from the character edge determining section 306 and 1 bit of EDG data, and the output of the scaling section 307 is also 9 bits.

VSYNC is a synchronization signal in the sub-scanning direction, HSYNC is a synchronization signal in the main-scanning direction, CLK is a pixel clock signal, and VE is a signal indicating an image valid section in the main-scanning direction. FIG. 5 is a timing chart of these basic signals.

Furthermore, 401, 406, 407, and 408 are 9-bit selectors, respectively, and when the selection signal S is at logic O level, A
When the logic level is 1, B inputs are selected and output. Reference numerals 414 and 415 each indicate a 1-bit selector, and their relationship with the selection signal S is the same as described above. 40
2,403.degree. 405 are 9-bit D-type flip-flops (DFF), each of which latches input data at the rising edge of each CLK signal. An interpolator 404 performs linear interpolation between two consecutive image data (including EDG data) according to an interpolation rate α.

413 is an interpolation coefficient determiner, which determines the interpolation rate α according to parameter information corresponding to the specified magnification ratio m% from the CPU 301.
(=O-15) information is generated. Similarly, the update of the address in the address controller 302 is controlled. Further, 409, 411 are bidirectional buffers, 410, 41
6 is an inverter, and 412 is a DFF constituting a 1-bit counter.

With this configuration, the DFF 412 is reset by the VSYNCS signal and then inverted by the H6YNC signal. That is, when the EVEN signal is at the logic O level, the CCD 211 reads the odd lines of the original 204, writes the read data to the RAM 309, and reads the stored data for the immediately preceding even line of the original 204 from the RAM 310. When the EVEN signal is at logic 1 level, the C0D 211 reads even lines of the original 204, writes the read data to the RAM 310, and reads the stored data for the odd line immediately before the original 204 from the RAM 309. handle.

The MOD signal is a signal sent by the CPU 301, and is a logic 1 level signal when image enlargement is specified (m>100), and is a logic O level signal when reduction or equal credit is specified (m≦100).

That is, when specifying image enlargement, the image data read by the C0D 211 is transferred via the selector 408 to the RAM 309 for odd lines, and to the RAM 3 for even lines.
10, each one is sequentially written as is. On the other hand, the image data written in the RAM 309 or 310 is
The data is enlarged and read out via the selector 407 according to the magnification factor m%, interpolated with data by the interpolator 404, and output from the selector 406.

In addition, when the image is reduced or fixed, the image data read by the CCD 211 is thinned out according to the reduction magnification m%, data is interpolated by the interpolator 404, and the selector 4
08, the data is written to the RAM 309 when the line is an odd number, and to the RAM 310 when the line is an even number.

On the other hand, the image data written in the RAM 309 or 310 is read out via the selector 407 and further outputted from the selector 406.

FIG. 4 is a block diagram of the interpolator 404 of the embodiment. In the figure, 601 to 604 are 8-bit selectors, each of which selects and outputs A inputs when the selection signal S is at logic O level, and selects and outputs B inputs when it is at logic 1 level. 606 to 609 are adders, and input terminals A,
For each 8-bit multivalued image data of B, (A+B)/
2 is performed and 8-bit multivalued image data is output. However, numbers less than 1 are rounded down.

610 is an AND gate, and 611 is an OR gate. 6
Reference numeral 12 denotes a 1-bit selector, which selects and outputs A inputs when the selection is manually performed S2O, and selects and outputs B inputs when S=1. 6
Reference numeral 13 designates a 1-bit selector, which selects and outputs the C side input when the selection force S=2.

In this configuration, the input image data is image data A at the previous point in time and image data B at the current point in time. Each image data A and B are 8-bit multivalued image data Al and B, respectively.
l and 1 bit EDG data A2. It consists of B2.

For multivalued image data AI and El, selectors 601~
604, adders 606 to 609, and interpolation rate α (=0 to
15) performs linear interpolation calculation. If the circuit operation is expressed mathematically, the interpolated data Y1 can be found by equation (2).

1 6 1 6 (2)
However, numbers less than 1 are rounded down.

On the other hand, EDG data A2. For B2, CPU30
From the iM times signal sent by 1, AND% of A2 and B2, OR1 of A2 and B2, or the most significant bit (bit3) of the interpolation rate a.
Accordingly, three outputs can be obtained when selecting either A2 or B2. When the CPU 301 wants to change the magnification so as to save the current EDG data B2=O, i M =
EDG data before O1 A2 = 1 or current EDG
When changing the magnification to save data B2=1, use i M
Set = 1. Also, EDG data A2 before scaling
Or, if you want to change the magnification close to the shape of B2, set i M = 2. That is, according to equation (2), interpolated data Y1
When α is small (bit3=o), the selector 612 selects A2 because it reproduces a value close to A1, and when a is large (bit3=1), the selector 612 selects A2 because it reproduces a value close to B1. choose B2 (dog).

FIG. 5 is a block diagram of the interpolation coefficient determiner 413 of the embodiment. In the figure, 103 is a 4-bit down counter (DCNTR), and when the load input terminal is at logic 1 level, the value RO at the data input terminal is loaded by the CLK signal, and after that, the enable terminal E is at logic 1 level. During the level, it counts down at each rising edge of the CLK signal, and when the count output becomes O, it outputs a logic 1 level to the carry output terminal RC.

104 is an adder (ADD) and has an input terminal A.

The sum of B (A + B) is calculated and output, and when the 14th bit (=8192) carries out, it is output to terminal C.
A carry-out signal (Co) is output to O. 10 more
5 to 107 are 1-bit DFFs, 108 is 131:' cut(7) DFF, 109 is NANDA-bit, 110 is A
ND gate, 111 is a 13-bit AND gate, 11
3 and 114 are OR gates, and 115 to 117 are inverters.

Also, 101 is a 4-bit register (R), and 102 is 13
This is a bit register (R), and each register is preset by CPU3.
A value corresponding to the specified magnification m% is set from 01.

If the specified magnification m% is equal to or reduced (m≦100),
There is a relationship expressed by equation (3) between the magnification m%, the value RO set in the register 101, and the value R1 set in the register 102.

It functions to determine the multiple of (threshold number), roughly 1 to 1/2, 1/2 to 1/3.1 of the specified magnification m%.
It functions to divide sections such as /3 to 1/4. Note that this function is implemented on the circuit by DCNTR103 and AND in Figure 5.
Gate 110. This is handled by DFF107 and others. Furthermore, the contents of R1 function to supplement the minute magnification within each section.

Therefore, when copying is performed at the same magnification or reduction magnification of m%, the CPU 301 back-calculates equation (3) in advance and sets the values RO and R1 as shown in Table 1 in the registers RO and R1, respectively.

Below is a margin. However, O≦R1≦8192 In formula (3), the contents of RO are set to 8192 Table 1 O. Therefore, when copying is performed at an enlargement magnification of m%, R
1 and sets it in the register 102.

Also, if the specified magnification/m% is enlargement (m>100),
There is a relationship between the magnification m% and the value R1 set in the register 102 as shown in equation (4).

That is, since RO is not required, the RO term in equation (3) is written in the register 101 so that it does not function on the circuit. FIG. 6 is a block diagram of the address controller 302 of the embodiment. In the figure, 701 to 703 are each 13-bit counters. Of these, the counter 701 is the CCD 211
generates a read address. That is, while VE=O, it is reset, and while VE=1, it is counted up sequentially by each CLK signal, and continuous addresses from 0 to 8191 are generated. Further, the counter 702 generates a write address (WR-ADD) for the RAM 309 or 310. That is, counter 702 has VE=1 and WCN=
Count up only in section 1. Also counter 70
3 is the read address (RD-
ADD). That is, the counter 703 has VE=
1 and counts up only in the section where RCN=1.

FIG. 7 is a block diagram of the filter circuit 310 of the embodiment. In the figure, 901 and 902 are 8-bit first-in first-out memories (FIFO
), which gives a delay of one line to each input multivalued image data. These are connected in series, so
As a result, three lines of parallel data are obtained. Furthermore,
904 to 906, 908 to 910, and 912 are 8-bit DFFs, each of which latches multivalued image data in synchronization with the CLK signal.

Now, as shown in FIG. 8, if we consider XIJ as the pixel of interest and a 3×3 window around it, the DFF 908 is (
X,-,,J), DFF905 is (Xl, J-1)
DFF909 is (X,,,) DFF912 is (Xl
, J, ), and the DFF 910 stores (XI*0.J), respectively.

913 is an adder, which calculates the sum of 4 input terminals A-D (A+
Take B+C+D). 914 is a filter calculation unit;
A smoothing filter calculation of (A+4B)/8 is performed for two input terminals A and B. By substituting the pixel data within the window into this, the smoothing calculation output SO for the pixel of interest X is determined by equation (6).

(6) 915 is also a filter computing unit, and has two input terminals A,
For B, an edge enhancement filter calculation of (8B-A)/4 is performed. Similarly, when calculating the pixel data within the window, the pixel of interest x1. The edge enhancement calculation output EO for is determined by equation (7).

(7) Also, 903 is 1. It is a FIFO of bits, and it is a human-powered E.
A delay of one line is given to the DG data. Furthermore,
The pixel of interest XI of the multivalued image data is synchronized with the corresponding EDG data via the 1-bit DFFs 907 and 911, respectively.

In the selector 916, if EDG data = O, the multivalued image data is not an edge part, so the smoothing calculation output SO side is selected and output, and if EDG data = 1, the multivalued image data is an edge part, so the edge enhancement calculation output EO side is selected. Output.

<Operation when the magnification m% is equal magnification or reduction> FIG. 9 is an exemplary operation timing chart illustrating a case where the specified magnification m% is equal magnification or reduction.

(Write Operation) The write operation in this case is an operation in which the image data read by the C0D 211 is thinned out according to the magnification m%, the data is interpolated, and the data is written to the RAM 309 or 310.

Now, since m≦100, MOD=O. For example, if the specified magnification = 42%, then from Table 1, RO = 1. R1=
The setting will be 3121.

As described above, the LCLR signal is first generated in synchronization with the rise of VE, and DCO=O and DAB=0.

In the next CLK signal, DCNTR=0 (RC=1) and ADH=1 is satisfied. As a result, WEN=1
That is, it becomes possible to write image data and increment WR-ADD.

Also, AB=3121, which is 8192 (threshold)
Since it does not exceed , C0=O. Also, since DAB=O, the interpolation rate α=O, and the image data Y1=A1 is written to the RAM 309 or 310.

In the next CLK signal, WR-ADD=1. Also, DCNTR=1 (RC=O), and ADH=1 is not satisfied. - As a result, WEN=0, that is, writing of image data and incrementing of WR-ADD are disabled. Also, as a result of DAB holding 3121, AB=
3121, but this does not yet exceed 8192, so C0=O. Also, α=6 due to DAB=3121
become.

In the next CLK signal, WR-ADD=1 remains. Also, DCNTR=O (RC=1) and ADH=1
satisfy. As a result, WEN=1, that is, it becomes possible to write image data and increment WR-ADD. Also, AB=6242, which is still 819
Since it does not exceed 2, C0=O. Also, since α=6, image data A1 and C of CCD-ADD (1)
The image data B1 of CD-ADD (2) is Yl= (
Interpolated at a ratio of 10XA1+6XB1)/16,
It is written to RAM 309 or 310.

Proceeding in the same manner, and at the second CLK signal, DCN
TR=O (RC=1) and ADH=1 is satisfied.

As a result, WEN=1, that is, it becomes possible to write image data and increment WR-ADD. Also, AB=1171, which partially exceeds 8192, so C0=1. Also, since α=12, image data Al and CC of CCD-ADD (3)
The image data Bl of D-ADD (4) is Y1= (4
It is interpolated at the ratio of XAl+12XB1)/16, and R
Written to AM 309 or 310.

In the next CLK signal, WR-ADD=3. Also D
CNTR=1 (RC=O), and ADH=1 is not satisfied. As a result, WEN=0, that is, writing of image data and incrementing of WR-ADD are disabled. Regarding DCO, as a result of holding C0=1, DC
O=1.

On the next CLK signal, because DCO=1, DCNT
The enable terminal E of R103 becomes 0, and the countdown cannot be performed. That is, DCNTR=1 (RC=O) remains. Therefore, ADH=1 is not satisfied. As a result, WEN=O.

That is, writing of image data and incrementing of WR-ADD become impossible. Also, AB=1171 remains, which does not exceed 8192, so C0=O.

In this way, when DCO=1, the increment of WR-ADD is blocked (thinned out) by one pixel, and the above-mentioned rough sections 1 to 1/2, 1/2 to 1/3. l/3~l/4
Fine reduction and scaling within the same area is performed appropriately.

As described above, WR-ADD progresses at a rate according to the values of the parameters RO and R1, and at the timing of writing image data, image data Y1 of appropriate density is interpolated and written to the RAM 309 or 310. Comparing this with the progress status of the CCD-ADD for document reading, it can be seen that the thinning ratio is approximately 3/7 (approximately 42%).

(Reading Operation) The reading operation in this case is an operation of sequentially reading the image data written in the RAM 309 or 310 through data interpolation and thinning according to the above-mentioned magnification m% and outputting it to the printer.

Now, since m≦100, MOD=0. Therefore, REN=1 always, and RD-ADD is CCD-AD
Like D, it simply increases for each CLK signal. The image data thus read out is output via the selector 406 in FIG. 3.

In addition, if the specified magnification m% is reduction, there is a concern that EDG data may be missing, so in order to select the OR interpolation shown in Figure 4, i
Let M = 1.

<Operation when magnification m% is enlargement> FIG. 10 is an exemplary operation timing chart illustrating a case where designated magnification m% is enlargement.

(Write Operation) The write operation in this case is an operation of sequentially writing the image data read by the C0D 211 into the RAM 309 or 310 as is.

Now, since m>100, MOD=1. Therefore, WEN=1 always and WR-ADD is CCD-A
Like DD, it simply increases for each CLK signal. In this way, the image data sent from the CCD 211 side is sequentially written into the RAM 309 or 310 via the selector 408 in FIG.

(Reading Operation) The reading operation in this case is an operation of sequentially reading out the image data written as is in the RAM 309 or 310 described above, interpolating the data, and outputting the interpolated data to the printer.

Now, since m>100, MOD=1. For example, if the specified magnification = 142%, RO = 0, R1 = 576
The setting will be 9. Also, since RO=0, DCN is always
TR=O (RC=1).

As described above, the LCLR signal is first generated in synchronization with the rise of VE, and DCO=O and DAB=0.

The next CLK signal satisfies ADH=1.

This results in AB=5769, which does not exceed 8192, so C0=O. Also, since REN=O, RD-ADD=O remains, and the image data at address O of the RAM 309 or 310 is being read.

In the next CLK signal, DAB holds 5769, resulting in AB=3346. Since this partially exceeds 8192, CO=1. Also, since α=11, the image arcs A1 and RD of RD-ADD(0)
-ADD (0) image data B1 is Yl= (5X
A1+11XEl)/16 is interpolated and output from the selector 406.

In the next CLK signal, DAB holds 3346, resulting in AB=923. Since this exceeds 8192 once again, GO=1. Also, since α=6, the image data A1 of the same < RD-ADD (0) and the image data B1 of RD-ADD (0) are Y1=
It is interpolated and formed at a ratio of (10XA1+6XBl)/16 and output from the selector 406. Also, at this point, as a result of DCO holding 1, REN=1. That is, RD-
ADD can be incremented.

In the next CLK signal, RD-ADD=1. Further, as a result of DAB holding 923, AB=6692. Since this does not exceed 8192, C0=O
It is. Also, since α=1, RD-ADD (0)
The image data A1 of RD-ADD (1) and the image data B1 of RD-ADD (1) are interpolated at a ratio of Y1=(1,5XA1+IXBl)/16, and are output from the selector 406.

Also, since DCO holds 1 at this point, R
EN=1, ie, RD-ADD increment is possible.

In this way, RD-ADD progresses at a rate according to the value of R1, and image data Y1 of appropriate density is interpolated and output from the selector 406 at the output timing of each image data. Comparing this with the progress status of the original CCD-ADD, it can be seen that the magnification rate is approximately 142%.

In addition, when the specified magnification m% is enlargement, in order to preserve the shape of the original image using EDG data, iM
=2.

FIG. 11 is a flowchart of the main control of the embodiment. In the figure, in step 51301, the magnification ratio m% is input from the operation unit. In step S1302, the value of m is set to 1.
00 to determine whether it is enlarged, reduced, or the same size. When enlarging, data for enlarging (V, MOD, RO, R1, etc.) is set in step S1303.

If the size is reduced or the same size, data for reduction or equal borrowing is set in step 51304. In step 51305, a copy operation is performed.

[Other Embodiments] Although linear interpolation is used in the above-mentioned flow, the present invention is not limited to this. For example, 5-inch interpolation may be used.

FIG. 14 is a block diagram of a 5-inch interpolator according to another embodiment. In the figure, 8-bit DFFs 1401 to 1404 each provide a delay of one pixel to the image data.

1405 and 1406 are 4-bit DFFs, which give a delay of one pixel to each interpolation coefficient α (which may be the same as in the above embodiment). Reference numerals 1407 to 1410 are look-up tables (LUTs) in which the values of equations (8) to (11) are calculated in advance and stored in the ROM (LtJT).

a-2: b-2Xγ a-+ = b-IXγ ao = l) oXγ a+ = t) + ＋ b rsin
c(x)= Furthermore, 1411 to 1 are adders. Now, if the outputs of are respectively X, the interpolation output yt is yt==a-2° HX t-2 is determined by equation (12).

+a−+−Xt−+ +a, ・Xt◆1 (12) In the above embodiment, the output of the interpolator 404 is reduced by the reduction magnification m
It was thinned out according to the percentage, but it is not limited to this. The input of the interpolator 404 may be thinned out according to the reduction magnification m%.

[Effects of the Invention] As described above, according to the present invention, there is no deterioration in image quality when changing the size of an image.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an image processing device according to an embodiment, FIG. 2 is a schematic sectional view of an image processing device according to an embodiment, FIG. 3 is a block configuration diagram of a variable magnification unit 307 according to an embodiment, and FIG. FIG. 5 is a block diagram of the interpolation coefficient determiner 413 of the embodiment. FIG. 6 is a block diagram of the address controller 302 of the embodiment. FIG. 7 is a block diagram of the address controller 302 of the embodiment. A block configuration diagram of the filter circuit 310. FIG. 8 is a diagram showing the relationship between the target pixel XI and the surrounding pixels in a 3×3 window. FIG. 9 is a diagram showing the relationship between the pixel of interest XI and the surrounding pixels in a 3×3 window.
FIG. 10 is an example operation timing chart explaining the case where the specified magnification m% is enlargement. FIG. 11 is a flowchart of the main control of the embodiment. Fig. 12 is a timing chart of the basic timing signal, Figs. 13 (A) to (D) are diagrams explaining an example of image processing in the embodiment, and Fig. 14 is a block diagram of a 5-inch interpolator in another embodiment. . In the figure, 211...CCD, 236...Laser driver, 301-CPU, 304-...Amplifier (Amp)
305... A/D converter (A/D), 306...
Character edge determination unit, 307... Magnification changing unit, 308...
Filter circuit, 309, 310...RAM, 311.
... I10 controller, 312 ... operation unit, 313
...Motor driver, 314...Motor, 316.
...ROM table. Figure 13 (A) Figure 13 (D)

Claims (6)

[Claims] (1) An image processing device that performs image data reduction processing, comprising: an interpolation unit that performs interpolation processing on continuous multi-valued image data; and a calculation unit that performs a logical operation on binary data corresponding to the continuous multi-valued image data; a thinning means for thinning out each input or each output of the interpolation means and the calculation means according to a reduction magnification; An image processing device characterized by comprising processing means for performing processing. (2) The image forming apparatus according to claim 1, further comprising extraction means for extracting edge information from continuous multivalued image data and converting the extracted edge information into binary data input to the calculation means. Image processing device. (3) The image processing apparatus according to claim 1, wherein the arithmetic means performs an AND operation, a logical OR operation, or any one selection operation of the corresponding binary data. (4) In an image processing device that performs image data enlargement processing, interpolation means performs interpolation processing on continuous multi-valued image data; calculation means performs a logical operation on binary data corresponding to the continuous multi-valued image data; duplication means for duplicating each input of the interpolation means and the calculation means according to the enlargement magnification; processing for performing processing on the multi-valued image data output from the interpolation means according to the content of the binary data output from the calculation means; An image processing device comprising: means. (5) The image forming apparatus according to claim 4, further comprising extraction means for extracting edge information from continuous multivalued image data and converting the extracted edge information into binary data to be input to the calculation means. Image processing device. (6) The image processing apparatus according to claim 4, wherein the arithmetic means performs a logical product operation, a logical sum operation, or any one of a selection operation on the corresponding binary data.