JPH0414438B2 - - Google Patents

Info

Publication number
JPH0414438B2
JPH0414438B2 JP61058225A JP5822586A JPH0414438B2 JP H0414438 B2 JPH0414438 B2 JP H0414438B2 JP 61058225 A JP61058225 A JP 61058225A JP 5822586 A JP5822586 A JP 5822586A JP H0414438 B2 JPH0414438 B2 JP H0414438B2
Authority
JP
Japan
Prior art keywords
address
port
signal
input
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61058225A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62217481A (ja
Inventor
Keizo Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61058225A priority Critical patent/JPS62217481A/ja
Publication of JPS62217481A publication Critical patent/JPS62217481A/ja
Publication of JPH0414438B2 publication Critical patent/JPH0414438B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
JP61058225A 1986-03-18 1986-03-18 マルチポ−トメモリ回路 Granted JPS62217481A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61058225A JPS62217481A (ja) 1986-03-18 1986-03-18 マルチポ−トメモリ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61058225A JPS62217481A (ja) 1986-03-18 1986-03-18 マルチポ−トメモリ回路

Publications (2)

Publication Number Publication Date
JPS62217481A JPS62217481A (ja) 1987-09-24
JPH0414438B2 true JPH0414438B2 (ko) 1992-03-12

Family

ID=13078137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61058225A Granted JPS62217481A (ja) 1986-03-18 1986-03-18 マルチポ−トメモリ回路

Country Status (1)

Country Link
JP (1) JPS62217481A (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2618422B2 (ja) * 1988-02-08 1997-06-11 富士通株式会社 半導体記憶装置
JPH03187095A (ja) * 1989-12-15 1991-08-15 Mitsubishi Electric Corp マルチポートメモリ制御装置
JP2673390B2 (ja) * 1991-03-13 1997-11-05 三菱電機株式会社 マルチポートメモリ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59129989A (ja) * 1983-01-17 1984-07-26 Nec Corp デユアル・ポ−ト型ダイナミツク・ランダム・アクセス・メモリ・セル及びその動作方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59129989A (ja) * 1983-01-17 1984-07-26 Nec Corp デユアル・ポ−ト型ダイナミツク・ランダム・アクセス・メモリ・セル及びその動作方法

Also Published As

Publication number Publication date
JPS62217481A (ja) 1987-09-24

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees