JPH04134804U - chip resistor - Google Patents

Abstract

(57) [Summary] [Purpose] The top overcoat layer, which requires acid resistance and is strong in toughness, was devised so that it would not interfere with the dividing work at the manufacturing stage, and the trimming grooves were exposed. To provide a highly reliable chip resistor that has good dividing workability and suppresses the occurrence of chipping defects and pinholes in the top overcoat layer by devising a method that does not adversely affect the resistor. . [Structure] A middle coat layer 10 covering the trimming groove 6 is provided on the first overcoat layer 4, and a second overcoat layer 5 provided on the middle coat layer 10 is spaced apart from the periphery of the insulating substrate 1. Ta.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention is a chip resistor in which the resistor on an insulating substrate is protected by an overcoat layer. Regarding anti-vessels.

0002

[Conventional technology]

Fig. 4 is a plan view showing a conventional general chip resistor, and Fig. 5 is a cross section taken along line A-A in Fig. 4. It is a front view.

0003 In these figures, a rectangular parallelepiped ceramic substrate 1 is used to form slurry into a thin plate. This ceramic substrate 1 is made by firing and dividing the so-called green sheet that has been produced. A pair of plated electrodes 2 are formed on both sides of the plate. And Sera On the ceramic substrate 1, there is a resistor 3 connecting both electrodes 2, 2, and a ceramic substrate 1. A first overcoat layer 4 covering the resistor 3 across the widthwise direction, and a relatively a second overcoat layer 5 having a large thickness and covering the first overcoat layer 4; are formed respectively, and a trimming groove 6 for adjusting the set resistance value is formed in the first 1 is engraved on the resistor 3 through the overcoat layer 4 of the resistor 3.

0004 Both overcoat layers 4 and 5 are made by printing and firing glass paste. However, the first overcoat layer 4 is exposed to thermal shock from laser etc. during the trimming process. The second overcoat layer 5 is provided to protect the resistor 3 from This prevents the plating material from adhering to the resistor 3 during the plating process and ensures mechanical strength. established for the purpose of preserving Therefore, the first overcoat layer 4 is trimmed. The second overcoat layer 5 is formed after the trimming process, whereas the second overcoat layer 5 is formed before the trimming process. A second layer is formed to prevent corrosion during pickling prior to plating. For the overcoat layer 5, a material with high acid resistance is used.

[0005] When manufacturing such a chip resistor, first, as shown in FIG. 6(a), A large ceramic substrate 9 with vertical and horizontal dividing grooves 7 and 8 carved therein is prepared, and this large ceramic substrate 9 is A large number of electrodes 2, resistors 3, and first overcoat layer 4 were formed on a substrate 9. After that, laser trimming is performed to form a trimming groove 6, and then as shown in FIG. 6(b). The second overcoat layer 5 is formed in advance. After that, along the dividing groove 7 The large ceramic substrate 9 is first divided into strips, and the electrodes 2 are extended on each side. By forming the large ceramic substrate 9 and then dividing it into two parts along the dividing grooves 8, the large ceramic substrate 9 is formed. It is divided into ceramic substrates 1 and exposed on both sides of each ceramic substrate 1. Electrode 2 is plated to complete a single chip resistor. And when implementing, The top surface 5a of the second overcoat layer 5 is air-chucked with a mount nozzle. Automatic mounting is generally performed, and each chip resistor is surface mounted on a printed wiring board, etc. be done.

[0006]

[Problem that the idea aims to solve]

By the way, the material of the second overcoat layer 5 in such a chip resistor is As mentioned above, it is necessary to select a material with high acid resistance considering the plating process. However, materials with high acid resistance generally have strong toughness and are difficult to break, so they cannot be When the second overcoat layer 5 is formed across the dividing groove 8, the division at the time of secondary division is Since the workability is poor and burrs are likely to form on the fractured surface, subsequent mechanical center Mechanical impact is applied to the burr during ringing, etc., and chipping occurs in the overcoat layer 5. The problem was that it was easy to do. Furthermore, in the conventional example, the second overcoat layer 5 is Since it is printed to cover the trimming groove 6, it is sealed in the trimming groove 6. Another problem was that the air expanded during firing, easily creating pinholes.

[0007] Therefore, in order not to straddle the dividing groove 7, the second overcoat layer 5 is applied to each section. It is also possible to print in an independent shape separated from the periphery of the lamic substrate 1, In that case, an electric current is provided through the trimming groove 6 exposed from the second overcoat layer There is a risk that a part of resistor 3 may be plated during the plating process of pole 2, so The reliability of the value will be significantly impaired.

[0008] This invention was devised in view of these circumstances, and its purpose is to improve Good dividing workability and no chipping or pinholes in the top overcoat layer. An object of the present invention is to provide a highly reliable chip resistor capable of suppressing generation.

[0009]

[Means to solve the problem]

The purpose of the present invention described above is to provide a pair of electrodes on an insulating substrate and a connection between these two electrodes. a resistor that connects the resistor, and a first overlay that covers the resistor before forming the trimming groove. After the above trimming process, the above first layer is made of a bar coat layer and a material with high acid resistance. A second overcoat layer is provided to cover the resistor through the overcoat layer. In the digit chip resistor, the trimming groove is formed on the first overcoat layer. A middle coat layer is provided to cover the middle coat layer, and the second layer is provided on the middle coat layer. This is achieved by spacing the overcoat layer from the periphery of the insulating substrate. Ru.

0010

[Effect]

According to the above means, the second overcoat layer, which has strong toughness and is difficult to break, is formed in the manufacturing stage. Since it does not straddle the floor dividing groove, it is easier to divide, improving work efficiency, and Since no burrs are formed on the overcoat layer during cracking, it is possible that the burrs are caused by mechanical impact. In addition, the trimming groove is covered with the middle coat layer. Prevents plating material from adhering to the resistor, and also prevents pinholes from forming in the middle coat layer. However, since the pinholes are covered by the second overcoat layer, they do not pose a problem.

[0011]

【Example】

Hereinafter, embodiments of the present invention will be described based on the drawings.

0012 FIG. 1 is a plan view showing an embodiment of a chip resistor according to the present invention, and FIG. A cross-sectional view taken along line B, and FIG. 3 is a diagram of the manufacturing process of this chip resistor. Portions corresponding to those in FIGS. 4 to 6 are given the same reference numerals.

[0013] The chip resistor shown in FIGS. 1 and 2 has a ceramic substrate 1 on which a pair of electrodes 2, Trimming across the resistor 3 connecting the two and the ceramic substrate 1 in the short direction. A first overcoat layer 4 covering the resistor 3 before processing and after trimming processing. A middle coat layer 10 covering the first overcoat layer 4 and a first overcoat layer 10 The ceramic material that coats the resistor 3 through the coat layer 4 and the middle coat layer 10 The second overcoat layer 5 is slightly spaced apart from the periphery of the substrate 1. The trimming groove 6 for adjusting the set resistance value is formed in the middle coat. completely covered by layer 10. Here, the middle coat layer 10 is -It is made by printing and firing a glass paste equivalent to bar coat layer 4, and has high toughness. Use a material that is relatively weak and easy to break, in other words, it is difficult for burrs to form on the fracture surface. ing.

[0014] When manufacturing such a chip resistor, first, as shown in Figure 3(a), A large number of electrodes 2, 2, . Next, as shown in FIG. 3(b), a large number of resistors 3, 3, ... are formed by printing. The electrodes 2, 2 which form the same are connected. After this, as shown in FIG. 3(c), the adjacent divisions A first overcoat layer 4 extending vertically between the grooves 7, 7 is formed by printing. After coating each resistor 3 with A trimming groove 6 that penetrates the first overcoat layer 4 is cut into each resistor 3. Adjust the set resistance value. After the trimming process, as shown in Figure 3(e), A middle coat layer 10 having substantially the same shape as the first overcoat layer 4 is added to the overcoat layer. 4, and then, as shown in FIG. 3(f), the grooves 7 and 8 are masking and printing a large number of second overcoat layers 5, 5,..., Although not shown, a mark such as a resistance value display is placed on the top surface 5 of the second overcoat layer 5. Apply to a. After that, the large ceramic substrate 9 is first divided into strips along the dividing groove 7. Then, electrodes 2 are formed extending on each side surface, and then secondary division is performed along the dividing grooves 8. As a result, the large ceramic substrate 9 is subdivided into ceramic substrates 1, and each A single chip resistor is produced by plating the electrodes 2 exposed on both sides of the lamic substrate 1. complete.

[0015] In this way, in the above embodiment, the second overcoat, which has high acid resistance and strong toughness, is used. The base layer 5 is printed in an independent shape spaced apart from the periphery of the ceramic substrate 1. The overcoat layer 5 does not straddle the dividing groove 8 during the manufacturing stage, and therefore does not extend over the dividing groove 8 during the secondary division. The efficiency of dividing work is greatly improved. Also, at the time of secondary division, the second overcoat layer 5 There is no risk of creating burrs, so mechanical impact to the burrs during mechanical centering etc. Compared to conventional products, where the overcoat layer of the A chip resistor that is less prone to defects has been obtained. In addition, the second independent shape Although the overcoat layer 5 cannot completely cover the trimming groove 6, Since the plating groove 6 is completely covered by the middle coat layer 10, the plating of the electrode 2 is easy. There is no possibility that the plating material will adhere to the resistor 3 through the trimming groove 6 during processing.

[0016] Further, in the above embodiment, the air sealed in the trimming groove 6 expands during firing. Even if a pinhole occurs in the middle coat layer 10, the pinhole will be removed afterwards. This is not a problem because it is covered by the second overcoat layer 5, and it is caused by pinholes. Characteristic deterioration is avoided. Moreover, this middle coat layer 10 is not subjected to trimming treatment. It covers up the shavings that are removed during cleaning and adheres to the area around the trimming groove 6. No plating material will stick to the shavings.

[0017]

[Effect of the idea]

As explained above, the chip resistor according to the present invention is required to have acid resistance. A top overcoat layer with strong toughness is provided at a distance from the periphery of the insulating substrate. The overcoat layer is designed not to straddle the dividing grooves at the manufacturing stage, making it easy to divide the parts. In addition, chipping defects caused by burrs can be avoided, and trimming can be improved. Since the overcoat layer is provided on the middle coat layer that covers the groove, it is easy to attach the resistor to the resistor. This prevents the adhesion of key materials and prevents pinholes from occurring in the overcoat layer. It has various effects such as

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of a chip resistor according to the present invention.

FIG. 2 is a sectional view taken along line BB in FIG. 1;

3 is a manufacturing process diagram of the chip resistor shown in FIGS. 1 and 2. FIG.

FIG. 4 is a plan view showing a conventional chip resistor.

FIG. 5 is a cross-sectional view taken along line AA in FIG. 4;

6 is a manufacturing process diagram of the chip resistor shown in FIGS. 4 and 5. FIG.

[Explanation of symbols]

1 Ceramic substrate 2 electrodes 3 Resistor 4 First overcoat layer 5 Second overcoat layer 6 Trimming groove 7,8 Dividing groove 10 Middle coat layer

Claims (1)

[Scope of utility model registration request] 1. A pair of electrodes, a resistor connecting these two electrodes, and a first layer covering the resistor before forming a trimming groove for adjusting a set resistance value on an insulating substrate. In the chip resistor provided with an overcoat layer and a second overcoat layer made of a material with high acid resistance and covering the resistor through the first overcoat layer after the trimming treatment, the first A chip resistor characterized in that a middle coat layer covering the trimming groove is provided on the overcoat layer, and the second overcoat layer provided on the middle coat layer is spaced apart from the periphery of the insulating substrate. vessel.