JP2545546Y2 - Chip resistor - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip resistor in which a resistor on an insulating substrate is protected by an overcoat layer.

[0002]

2. Description of the Related Art FIG. 4 is a plan view showing a conventional general chip resistor, and FIG. 5 is a sectional view taken along the line A--A in FIG.

In these figures, a rectangular parallelepiped ceramic substrate 1 is formed by firing and dividing a so-called green sheet in which a slurry is formed in a thin plate shape, and both sides of the ceramic substrate 1 are subjected to plating. A pair of electrodes 2 are formed. On the ceramic substrate 1, a resistor 3 for connecting the two electrodes 2 and 2 and a first overcoat layer 4 for covering the resistor 3 by traversing the ceramic substrate 1 in the transverse direction are compared. A second overcoat layer 5 having a large target film thickness and covering the first overcoat layer 4 is formed, and a trimming groove 6 for adjusting a set resistance value is formed in the first overcoat layer 4. Are engraved on the resistor 3.

[0004] Both overcoat layers 4 and 5 are formed by printing and baking a glass paste. The first overcoat layer 4 protects the resistor 3 from thermal shock such as laser in a trimming step. To provide for
The overcoat layer 5 is provided in order to prevent the plating material from adhering to the resistor 3 in the plating step and to secure mechanical strength. Therefore, while the first overcoat layer 4 is formed before the trimming process, the second overcoat layer 5 is formed after the trimming process, and is not corroded by pickling prior to the plating process. For this purpose, a material having high acid resistance is used for the second overcoat layer 5.

When manufacturing such a chip resistor, first, as shown in FIG.
A large ceramic substrate 9 engraved with a substrate 8 is prepared, a large number of electrodes 2, resistors 3, and a first overcoat layer 4 are formed on the large ceramic substrate 9, and then a laser trimming is performed to trim the groove. 6 is formed, and then a second overcoat layer 5 is formed as shown in FIG.
Thereafter, the large ceramic substrate 9 is firstly divided into strips along the division grooves 7, the electrodes 2 are formed to extend on the respective side surfaces, and then the second division is performed along the division grooves 8. 9 is divided into the ceramic substrates 1 and the electrodes 2 exposed on both sides of each ceramic substrate 1 are plated to complete a single chip resistor. And
At the time of mounting, automatic mounting is generally performed in which the top surface 5a of the second overcoat layer 5 is air-chucked by a mount nozzle, and each chip resistor is surface-mounted on a printed wiring board or the like.

[0006]

As a material of the second overcoat layer 5 in such a chip resistor, it is necessary to select a material having a high acid resistance in consideration of the plating process as described above. In general, since a material having high acid resistance has high toughness and is difficult to be divided, when the second overcoat layer 5 is formed across the dividing groove 8 as in the conventional example,
Since the dividing workability at the time of the secondary division is poor and burrs are easily formed on the fractured surface, a mechanical shock is applied to the burrs at the time of subsequent mechanical centering or the like, so that the overcoat layer 5 is likely to be chipped. There was a problem. Further, in the conventional example, since the second overcoat layer 5 is formed by printing so as to cover the trimming groove 6, there is also a disadvantage that air sealed in the trimming groove 6 expands during firing and pinholes are easily generated. Atsuta.

In order to prevent the second overcoat layer 5 from straddling the dividing groove 7, it is conceivable to print the second overcoat layer 5 in an independent shape separated from the peripheral edge of each ceramic substrate 1. Since there is a possibility that a portion of the resistor 3 may be damaged during the plating process of the electrode 2 via the trimming groove 6 exposed from the overcoat layer 5 of the second layer 2, the reliability of the resistance value is significantly impaired. .

The present invention has been made in view of such circumstances, and has as its object the good workability of division at the manufacturing stage, and the occurrence of chipping defects and pinholes in the uppermost overcoat layer can be suppressed. An object of the present invention is to provide a highly reliable chip resistor.

[0009]

SUMMARY OF THE INVENTION The object of the present invention is to cover a pair of electrodes, a resistor connecting between the two electrodes, and the resistor before forming a trimming groove on an insulating substrate. A chip resistor provided with a first overcoat layer to be formed and a second overcoat layer made of a material having a high acid resistance and covering the resistor via the first overcoat layer after the trimming process. , The first
This is achieved by providing a middle coat layer covering the trimming groove on the overcoat layer, and separating the second overcoat layer provided on the middle coat layer from the periphery of the insulating substrate.

[0010]

According to the above-mentioned means, the second overcoat layer, which has high toughness and is difficult to split, does not straddle the dividing groove in the manufacturing stage, so that it is easy to divide and the workability is improved. Since no burrs are formed on the layer, chipping defects due to mechanical impact on the burrs can be avoided, and since the trimming groove is covered with the middle coat layer, adhesion of the plating material to the resistor can be prevented. Even if a pinhole is generated in the layer, there is no problem because the pinhole is covered by the second overcoat layer.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing an embodiment of a chip resistor according to the present invention, FIG. 2 is a sectional view taken along the line BB of FIG.
FIG. 3 is a view showing a manufacturing process of the chip resistor, and portions corresponding to those of FIGS. 4 to 6 described above are denoted by the same reference numerals.

The chip resistor shown in FIGS. 1 and 2 has a resistor 3 for connecting a pair of electrodes 2 and 2 on a ceramic substrate 1 and a transverse direction across the ceramic substrate 1 before trimming. A first overcoat layer 4 covering the resistor 3 and a first overcoat layer 4 after the trimming process.
And a second overcoat layer 5 which covers the resistor 3 via the first overcoat layer 4 and the middle coat layer 10 but is slightly separated from the periphery of the ceramic substrate 1. And trimming grooves 6 for adjusting the set resistance value.
Is completely covered by the middle coat layer 10. Here, the middle coat layer 10 is formed by printing and firing a glass paste equivalent to that of the first overcoat layer 4, and has relatively low toughness and is easy to split. In other words, burrs occur on the fractured surface. Uses difficult materials.

When manufacturing such a chip resistor, first, as shown in FIG.
A number of electrodes 2, 2,... Straddling the division groove 7 are printed thereon, and then, as shown in FIG. 3B, a number of resistors 3, 3,. Are connected to each other. Thereafter, as shown in FIG. 3 (c), a first overcoat layer 4 extending in the vertical direction is formed between adjacent divided grooves 7, 7 by printing to cover the resistors 3, and
Laser trimming is performed, and as shown in FIG. 3D, a trimming groove 6 penetrating the first overcoat layer 4 is cut in each resistor 3 to adjust a set resistance value. After the trimming step, as shown in FIG. 3E, a middle coat layer 10 having substantially the same shape as the first overcoat layer 4 is formed by printing on the overcoat layer 4, and then as shown in FIG. In this manner, a large number of second overcoat layers 5, 5,... Are formed by printing so as not to extend over the dividing grooves 7, 8, and, although not shown, marking such as resistance value display is performed. Is applied to the top surface 5 a of the second overcoat layer 5. Thereafter, the large ceramic substrate 9 is firstly divided into strips along the division grooves 7, the electrodes 2 are formed to extend on the respective side surfaces, and then the second division is performed along the division grooves 8. 9 is divided into the ceramic substrates 1 and the electrodes 2 exposed on both sides of each ceramic substrate 1 are plated to complete a single chip resistor.

As described above, in the above embodiment, since the second overcoat layer 5 having high acid resistance and high toughness is printed and formed in an independent shape separated from the peripheral edge of the ceramic substrate 1, the overcoat layer 5 is formed. 5 does not straddle the dividing groove 8 in the manufacturing stage, so that the dividing workability at the time of the secondary division is greatly improved. In addition, since there is no possibility that burrs are generated on the second overcoat layer 5 at the time of secondary division, the second overcoat layer 5 is easily chipped due to mechanical impact on burrs at the time of mechanical centering or the like. A chip resistor which is less likely to cause chipping failure in a manufacturing stage or a mounting stage has been obtained. Incidentally, the second overcoat layer 5 having such an independent shape is provided with a trimming groove 6.
Cannot be completely covered, but since the trimming groove 6 is completely covered by the middle coat layer 10, the electrode 2
There is no danger that the plating material will adhere to the resistor 3 via the trimming groove 6 during the plating process.

In the above embodiment, the air sealed in the trimming groove 6 expands during firing and the middle coat layer 1 is expanded.
Even if a pinhole is generated at 0, the pinhole is subsequently covered by the second overcoat layer 5 so that there is no problem, and deterioration of characteristics due to the pinhole is avoided. Moreover, since the middle coat layer 10 is removed at the time of the trimming process and covers the shavings adhering to the periphery of the trimming groove 6, the plating material does not adhere to the shavings.

[0017]

As described above, in the chip resistor according to the present invention, the uppermost overcoat layer having high toughness due to the requirement of acid resistance is provided at a distance from the periphery of the insulating substrate. Is not straddled by the dividing groove in the manufacturing stage, so that the dividing workability is improved, chipping defects due to burrs can be avoided, and the overcoat layer is provided on the middle coat layer covering the trimming groove. Therefore, it is possible to prevent the adhesion of the plating material to the resistor and to prevent pinholes from being generated in the overcoat layer.
It produces various effects.

[Brief description of the drawings]

FIG. 1 is a plan view showing one embodiment of a chip resistor according to the present invention.

FIG. 2 is a sectional view taken along line BB of FIG.

FIG. 3 is a manufacturing process diagram of the chip resistor shown in FIGS.

FIG. 4 is a plan view showing a conventional general chip resistor.

FIG. 5 is a sectional view taken along line AA of FIG. 4;

FIG. 6 is a manufacturing process diagram of the chip resistor shown in FIGS.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 ceramic substrate 2 electrode 3 resistor 4 first overcoat layer 5 second overcoat layer 6 trimming groove 7, 8 division groove 10 middle coat layer

Claims (1)

(57) [Scope of request for utility model registration] A first pair of electrodes, a resistor connecting between the two electrodes, and a first covering the resistor before forming a trimming groove for adjusting a set resistance value on the insulating substrate. A chip resistor provided with an overcoat layer and a second overcoat layer made of a material having a high acid resistance and covering the resistor via the first overcoat layer after the trimming process; Wherein a middle coat layer covering the trimming groove is provided on the overcoat layer, and the second overcoat layer provided on the middle coat layer is separated from a peripheral edge of the insulating substrate. vessel.