JPH04120516A - Matrix type display device - Google Patents
Matrix type display deviceInfo
- Publication number
- JPH04120516A JPH04120516A JP2241711A JP24171190A JPH04120516A JP H04120516 A JPH04120516 A JP H04120516A JP 2241711 A JP2241711 A JP 2241711A JP 24171190 A JP24171190 A JP 24171190A JP H04120516 A JPH04120516 A JP H04120516A
- Authority
- JP
- Japan
- Prior art keywords
- picture element
- electrode
- insulating film
- signal line
- scanning line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 238000009413 insulation Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 42
- 238000005530 etching Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000010407 anodic oxide Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229920000058 polyacrylate Polymers 0.000 description 2
- 244000228957 Ferula foetida Species 0.000 description 1
- -1 PIX-8803) Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920003051 synthetic elastomer Polymers 0.000 description 1
- 239000005061 synthetic rubber Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、薄膜トランジスタ（以下ではｒＴＦＴ」と称
する）、ダイオード、ＭＩＭ （金属−絶縁層−金属）
素子等のスイッチング素子を有するマトリクス型表示装
置に関する。Detailed Description of the Invention (Industrial Application Field) The present invention is applicable to thin film transistors (hereinafter referred to as "rTFT"), diodes, MIM (metal-insulating layer-metal)
The present invention relates to a matrix type display device having switching elements such as elements.
（従来の技術）
従来のマトリクス型表示装置を第２Ａ図〜第２Ｅ図に示
す。この表示装置を製造工程に従って説明する。第２Ａ
図〜第２Ｅ図では上側に示す平面図のＡ−Ａ線に沿った
断面図が下側に示されている。ガラス等の絶縁性の基板
２０上に、Ｔａからなるゲートバス配線１がパターン形
成され、ゲートバス配線１の上面を陽極酸化することに
より、Ｔａ２０５からなる陽極酸化膜２が形成される（
第２Ａ図）。ゲートバス配線１は走査線として機能し、
ゲートバス配線工の一部がゲート電極として機能してい
る。(Prior Art) A conventional matrix display device is shown in FIGS. 2A to 2E. This display device will be explained according to the manufacturing process. 2nd A
In FIGS. 2-2E, a cross-sectional view taken along line A--A of the top plan view shown on the upper side is shown on the lower side. A gate bus wiring 1 made of Ta is patterned on an insulating substrate 20 such as glass, and an anodic oxide film 2 made of Ta205 is formed by anodizing the upper surface of the gate bus wiring 1 (
Figure 2A). The gate bus wiring 1 functions as a scanning line,
A part of the gate bus wiring works as a gate electrode.
陽極酸化膜２を覆って基板２０上の全面に、５ｉＮ８か
らなるゲート絶縁膜３、後に半導体層４となるアモルフ
ァスシリコン（以下ではｒａ−５ｉＪと称する）層、及
び後にエツチングスト、パ５となる第２のＳｉＮ工層が
連続的に堆積される。次に、第２ｔｖＳＩＮ、Ｈｔがバ
ターニングされ、エツチングストッパ５が形成される（
第２Ｂ図）。Covering the anodic oxide film 2 and covering the entire surface of the substrate 20, there is a gate insulating film 3 made of 5iN8, an amorphous silicon (hereinafter referred to as RA-5iJ) layer that will later become the semiconductor layer 4, and an etching paste and a layer 5 that will later become the semiconductor layer 4. A second SiN layer is successively deposited. Next, the second tvSIN and Ht are patterned to form the etching stopper 5 (
Figure 2B).
更に、後にコンタクト層６．６となるｎ＋型ａ−３ｉ層
が基板２０上の全面に堆積され、上述のａＳｉ層及びｎ
ゝ型ａ−３ｔ層のバターニングにより、半導体層４及び
コンタクト層６．６が形成される（第２Ｃ図）。Furthermore, an n+ type a-3i layer, which will later become a contact layer 6.6, is deposited on the entire surface of the substrate 20, and is formed by depositing the above-mentioned aSi layer and n+ type a-3i layer.
By patterning the type A-3T layer, a semiconductor layer 4 and a contact layer 6.6 are formed (FIG. 2C).
次に、Ｔｉ金属層が基板２０上の全面にスパッタリング
法により形成され、このＴｆ金属層のバターニングが行
われて、信号線として機能するソースバス配線９、ソー
ス電極７、及び出力端子として機能するドレイン電極８
が形成される（第２Ｄ図）。従って、ソースバス配線９
はゲート絶縁膜３上に形成される。以上により、スイッ
チング素子として機能するＴＦＴＩＩが完成する。Next, a Ti metal layer is formed on the entire surface of the substrate 20 by sputtering, and this Tf metal layer is patterned to form source bus lines 9 that function as signal lines, source electrodes 7, and output terminals. Drain electrode 8
is formed (Figure 2D). Therefore, source bus wiring 9
is formed on the gate insulating film 3. Through the above steps, the TFT II functioning as a switching element is completed.
次に、Ｉ Ｔ Ｏ（Ｉｎｄｉｕｍ ｔｉｎ ｏｘｉｄｅ
）膜が基板２０上の全面にスパッタリング法により形成
され、このＩＴＯ膜がフォトリソグラフィ法及びエツチ
ングによってバターニングされ、絵素電極１０が形成さ
れる（第２Ｅ図）。従って、絵素電極１０はゲート絶縁
膜３上に形成されることになる。その後、ＳｉＮｘから
なる保護膜（図示せず）がプラズマＣＶＤ法により形成
される。Next, ITO (Indium tin oxide)
) A film is formed on the entire surface of the substrate 20 by sputtering, and this ITO film is patterned by photolithography and etching to form the picture element electrode 10 (FIG. 2E). Therefore, the picture element electrode 10 is formed on the gate insulating film 3. Thereafter, a protective film (not shown) made of SiNx is formed by plasma CVD.
（発明が解決しようとする課題）
上述のマトリクス型表示装置では、絵素電極１０とソー
スバス配線９とはゲート絶縁膜３上に形成されるため、
絵素電極１０とソースバス配線９との間には間隙が設け
られている。この間隙の幅が小さいと、エツチング不良
、レジスト不良等が起こった場合に、絵素電極１０とソ
ースバス配線９との開にリーク電流が生じることになる
。従って、この間隙の幅は十分に大きくする必要がある
。(Problem to be Solved by the Invention) In the above-described matrix type display device, since the picture element electrode 10 and the source bus wiring 9 are formed on the gate insulating film 3,
A gap is provided between the picture element electrode 10 and the source bus wiring 9. If the width of this gap is small, a leakage current will occur between the picture element electrode 10 and the source bus wiring 9 in the event of an etching defect, a resist defect, or the like. Therefore, the width of this gap needs to be sufficiently large.
ところが、絵素電極１０とソースバス配線９との間の間
隙を大きくすると絵素電極１０の面積が減少するため、
表示装置の開口率が低下することになる。However, if the gap between the picture element electrode 10 and the source bus wiring 9 is increased, the area of the picture element electrode 10 decreases.
The aperture ratio of the display device will be reduced.
開口率の低下を避けるために、ソースバス配線９の幅を
小さくすることが考えられる。しかし、ソースバス配線
９の幅を小さくすると、ソースバス配線９が断線する確
率が増大するので好ましくない。In order to avoid a decrease in the aperture ratio, it is conceivable to reduce the width of the source bus wiring 9. However, reducing the width of the source bus wiring 9 is not preferable because the probability that the source bus wiring 9 will be disconnected increases.
本発明はこのような問題点を解決するものであり、本発
明の目的は、大きな面積の絵素電極を有するマトリクス
型表示装置を提供することである。The present invention solves these problems, and an object of the present invention is to provide a matrix display device having a large area of picture element electrodes.
（課題を解決するための手段）
本発明のマトリクス型表示装置は、一対の絶縁性基板と
、該一対の基板の何れか一方の基板内面に配線された走
査線及び信号線と、該走査線及び該信号線に接続された
スイッチング素子と、該スイッチング素子の出力端子に
接続された絵素電極と、を有するマトリクス型表示装置
であって、該走査線と該信号線と該スイッチング素子と
を覆って形成された有機絶縁膜と、該有機絶縁膜の該出
力端子上の部分に形成されたスルーホールと、を有し、
該出力端子と該絵素電極とが該スルーホールを介して電
気的に接続され、該絵素電極が該走査線及び該信号線と
該有機絶縁膜を挟んで重畳されており、そのことによっ
て上記目的が達成される。(Means for Solving the Problems) A matrix type display device of the present invention includes a pair of insulating substrates, a scanning line and a signal line wired on the inner surface of one of the pair of substrates, and the scanning line and a switching element connected to the signal line, and a picture element electrode connected to an output terminal of the switching element, wherein the scanning line, the signal line, and the switching element are connected to each other. an organic insulating film formed over the organic insulating film, and a through hole formed in a portion of the organic insulating film above the output terminal;
The output terminal and the picture element electrode are electrically connected via the through hole, and the picture element electrode is overlapped with the scanning line and the signal line with the organic insulating film in between. The above objectives are achieved.
（作用）
本発明のマトリクス型表示装置では、走査線と信号線と
スイッチング素子とを覆う有機絶縁膜が形成されている
。有機絶縁膜上には絵素電極が形成されている。スイッ
チング素子の出力端子上の有機絶縁膜にはスルーホール
が形成され、このスルーホールを介して絵素電極と出力
端子とが電気的に接続される。このように有機絶縁膜を
走査線と信号線とスイッチング素子との上に形成したこ
とにより、絵素電極を走査線及び信号線に重畳して形成
することができる。このような構成としても、有機絶縁
膜の耐絶縁性が大きいので、絵素電極と走査線及び信号
線との間にはリーク電流は生じない。また、有機絶縁膜
の誘電率が小さいので、走査線及び信号線との間に形成
される浮遊容量も小さい。更に、有機絶縁膜は良好なレ
ベソング特性を示すので、走査線及び信号線を確実に覆
って形成される。従って、絵素電極を走査線及び信号線
の上に重ねて形成しても、絵素電極と走査線及び信号線
との間にリーク電流は生じない。(Function) In the matrix display device of the present invention, an organic insulating film is formed to cover the scanning lines, signal lines, and switching elements. A picture element electrode is formed on the organic insulating film. A through hole is formed in the organic insulating film on the output terminal of the switching element, and the picture element electrode and the output terminal are electrically connected via this through hole. By forming the organic insulating film on the scanning line, signal line, and switching element in this manner, the picture element electrode can be formed to overlap the scanning line and the signal line. Even with this configuration, since the organic insulating film has high insulation resistance, no leakage current occurs between the picture element electrode and the scanning line and signal line. Furthermore, since the dielectric constant of the organic insulating film is small, the stray capacitance formed between the scanning line and the signal line is also small. Furthermore, since the organic insulating film exhibits good level song characteristics, it can be formed to reliably cover the scanning lines and signal lines. Therefore, even if the picture element electrode is formed overlapping the scanning line and the signal line, no leakage current occurs between the picture element electrode and the scanning line and the signal line.
（実施例） 本発明の実施例について以下に説明する。(Example) Examples of the present invention will be described below.
本実施例のマトリクス型表示装置の製造工程を第１Ａ図
〜第１Ｇ図に示す。第１Ａ図〜第１Ｇ図を参照しながら
、本実施例を製造工程に従って説明する。第１Ａ図〜第
１Ｇ図では上側に示す平面図のＡ−Ａ線に沿った断面図
が下側に示されている。ガラス等の絶縁性基板２０上に
、Ｔａ金属層（層厚４０００Ａ）をスパッタリング法に
より堆積し、このＴａ金属層をバターニングすることに
より、ゲートバス配線１を形成した。ゲートバス配線１
は走査線として機能し、ゲートバス配線１の一部がゲー
ト電極として機能する。次に、ゲートバス配線１の上面
を陽極酸化することにより、Ｔａ２０５からなる陽極酸
化膜２を形成した（第１Ａ図）。陽極酸化膜２はゲート
絶縁膜としても機能する。The manufacturing process of the matrix type display device of this example is shown in FIGS. 1A to 1G. This embodiment will be described according to the manufacturing process with reference to FIGS. 1A to 1G. In FIGS. 1A to 1G, a sectional view taken along the line A-A of the top plan view is shown at the bottom. A Ta metal layer (layer thickness: 4000 Å) was deposited on an insulating substrate 20 made of glass or the like by sputtering, and this Ta metal layer was patterned to form the gate bus wiring 1. Gate bus wiring 1
functions as a scanning line, and a portion of the gate bus wiring 1 functions as a gate electrode. Next, the upper surface of the gate bus wiring 1 was anodized to form an anodic oxide film 2 made of Ta205 (FIG. 1A). The anodic oxide film 2 also functions as a gate insulating film.
陽極酸化膜２を覆って基板２０上の全面に、ＳｉＮ、か
らなるゲート絶縁膜３（層厚３０００人）、後に半導体
層４となる層厚３００Ａのアモルファスシリコン（以下
ではｒａ−ＳｊＪと称する）層、及び後にエツチングス
トッパ５となる第２の５ｔＮｘ層（層厚２０００人）を
プラズマＣＶＤ法により連続的に堆積した。次に、第２
の５ｊＮｘ層を７ ＜ターニングし、エツチングストッ
パ５を形成した（第１Ｂ図）。Covering the anodic oxide film 2 and covering the entire surface of the substrate 20, a gate insulating film 3 made of SiN (layer thickness: 3000 nm), and amorphous silicon (hereinafter referred to as ra-SjJ) having a layer thickness of 300 A, which will later become the semiconductor layer 4. This layer and a second 5tNx layer (layer thickness: 2000 nm), which will later become the etching stopper 5, were successively deposited by plasma CVD. Next, the second
The 5jNx layer was turned by 7 degrees to form an etching stopper 5 (FIG. 1B).
更に、後にコンタクト層６．６となるｎ″型ａ−３ｉ層
（層厚５００人）を基板２０上の全面に堆積し、上述の
ａ−Ｓｉ層及びｎ ＋型ａ−Ｓｉ層のバターニングによ
り、半導体層４及びコンタクト層６．６を形成した（第
１Ｃ図）。Furthermore, an n'' type a-3i layer (500 layers thick), which will later become the contact layer 6.6, is deposited on the entire surface of the substrate 20, and the above-mentioned a-Si layer and n + type a-Si layer are patterned. Accordingly, a semiconductor layer 4 and a contact layer 6.6 were formed (FIG. 1C).
次に、Ｍｏ金属層（層厚３０００人）を基板２０上の全
面にスパッタリング法により形成し、このＭｏ金属層の
バターニングを行なって、信号線として機能するソース
バス配線９、ソース電極７、及びＴＰＴの出力端子とし
て機能するドレイン電極８を形成した（第１Ｄ図）。従
って、ソースバス配線９はゲート絶縁膜３上に形成され
る。以上により、スイッチング素子として機能するＴＦ
Ｔｌｌが完成する。Next, a Mo metal layer (3000 layers thick) is formed on the entire surface of the substrate 20 by sputtering, and this Mo metal layer is patterned to form source bus wiring 9, source electrode 7, which functions as a signal line, Then, a drain electrode 8 functioning as an output terminal of the TPT was formed (FIG. 1D). Therefore, the source bus wiring 9 is formed on the gate insulating film 3. As described above, the TF that functions as a switching element
Tll is completed.
次に、ゲートバス配線１、ソースバス配！！９、及びＴ
ＦＴＩＩを覆って基板２０上の全面に、有機絶縁膜１２
を層厚１μｍでスピンコードした。Next, gate bus wiring 1, source bus wiring! ! 9, and T
An organic insulating film 12 is formed on the entire surface of the substrate 20 covering the FTII.
was spin-coded with a layer thickness of 1 μm.
有機絶縁膜１２として用い得る材料は、ポリイミド系ポ
リマー、ポリスチレン系ポリマー、アクリル系ポリマー
シロキサン変性ポリイミド系ポリマー等である。本実
施例では、シロキサン変性ポリイミド系ポリマー（日立
化成、ＰＩＸ−８８０３） 、ポリイミド系ポリマー（
東し・ダウコーニング７リコン、ＫＸ−１３１２Ｄ）
、又はアクリル系ポリマー（日本合成ゴム、オプトマー
ＳＳ）を用いた。有機絶縁膜１２の焼成後、フォトレジ
ス１−１３を層厚２μｍで有機絶縁膜１２上の全面にス
ピンコードし、該フォトレジスト１３をブリベイクした
。このフォトレジスト１３の露光及び現像を行い、フォ
トレジスト１３のドレイン電極８上の部分にホール１４
を形成した（第１Ｅ図）。Materials that can be used as the organic insulating film 12 include polyimide polymers, polystyrene polymers, acrylic polymers, siloxane-modified polyimide polymers, and the like. In this example, siloxane-modified polyimide polymer (Hitachi Chemical, PIX-8803), polyimide polymer (
East/Dow Corning 7 Recon, KX-1312D)
, or an acrylic polymer (Japan Synthetic Rubber, Optomer SS) was used. After baking the organic insulating film 12, a photoresist 1-13 was spin-coded to a thickness of 2 μm over the entire surface of the organic insulating film 12, and the photoresist 13 was baked. This photoresist 13 is exposed and developed, and a hole 14 is formed in the portion of the photoresist 13 above the drain electrode 8.
was formed (Fig. 1E).
次に、ＲＩ Ｅ （Ｒｅａｃｔｉｖｅ ｔｏｎ ｅｔｃ
ｈｉｎｇ）装置を用い、０□、１１００５ＣＣ，２０Ｐ
ａ、２００Ｗの条件で２０分間、フォトレジスト１３を
マスクとして有機絶縁膜１２のエツチングを行った。有
機絶縁膜１２とフォトレジスト１３との選択比は、１／
１と低いため、フォトレジスト１３の層厚を有機絶縁膜
１２のそれの２倍とした。その後、フォトレジスト１３
をレジスト剥離液を用いて除去した。上述のエツチング
により、スルーホール１５が形成される（第１Ｆ図）。Next, RI E (Reactive ton etc.
hing) device, 0□, 11005CC, 20P
a. The organic insulating film 12 was etched for 20 minutes at 200 W using the photoresist 13 as a mask. The selectivity ratio between the organic insulating film 12 and the photoresist 13 is 1/
1, the layer thickness of the photoresist 13 was made twice that of the organic insulating film 12. After that, photoresist 13
was removed using a resist stripping solution. Through the etching described above, through holes 15 are formed (FIG. 1F).
次に、Ｉ Ｔ Ｏ（Ｉｎｄｉｕｍ ｔｉｎ ｏｘｉｄｅ
）膜を基板２０上の全面にスパッタリング法により形成
し、このＩＴＯ膜をフォトリングラフィ法及びエツチン
グによってバターニングし、絵素電極１０を形成した（
第１Ｇ図）。絵素電極１０はスルーホール１５を介して
ドレイン電極と電気的に接続される。Next, ITO (Indium tin oxide)
) film was formed on the entire surface of the substrate 20 by sputtering, and this ITO film was patterned by photolithography and etching to form the picture element electrode 10 (
Figure 1G). The picture element electrode 10 is electrically connected to a drain electrode via a through hole 15.
また、絵素電極１０は、第１Ｇ図の上部に示すように、
ゲートバス配線１とソースバス配線９とに有機絶縁＄１
２を挟んで重畳されている。表示画面の開口率を大きく
する必要がない場合には、絵素電極１０をゲートバス配
線工及びソースバス配線９に重畳する必要はない。次に
、対向基板との間に液晶層が封入され、本実施例のマト
リクス型表示装置が得られる。Further, as shown in the upper part of FIG. 1G, the picture element electrode 10 is
Organic insulation $1 for gate bus wiring 1 and source bus wiring 9
They are superimposed with 2 in between. If there is no need to increase the aperture ratio of the display screen, there is no need to overlap the picture element electrode 10 with the gate bus wiring and the source bus wiring 9. Next, a liquid crystal layer is sealed between the counter substrate and the matrix type display device of this example.
本実施例のマトリクス型表示装置の絵素電極ｌＯは、ゲ
ートバス配線１及びソースバス配線９に有機絶縁膜１２
を挟んで重畳されているので、絵素電極の面積を大きく
することができる。従って、開口率の大きなマトリクス
型表示装置を得ることができる。また、有機絶縁膜１２
の耐絶縁性が大きいので、絵素電極１０とゲートバス配
線ｌ及びソースバス配線９との開にはリーク電流は生じ
ない。また、有機絶縁膜１２の誘電率が小さいので、絵
素電極１０とゲートバス配線１及びソースバス配線９と
の間に形成される浮遊容量も小さい。更ニ、有機絶縁膜
１２はスピンコード法によって形成され良好なレベリン
グ特性を示すので、ゲートバス配線１及びソースバス配
線９を確実に覆って形成される。従って、絵素電極１０
をゲートバス配線１及びソースバス配線９の上に重ねて
形成しても、絵素電極１０とゲートバス配線１及びソー
スバス配線９との間にリーク電流は生じない。The picture element electrode lO of the matrix type display device of this embodiment has an organic insulating film 12 on the gate bus wiring 1 and the source bus wiring 9.
Since the two electrodes are overlapped with each other on both sides, the area of the picture element electrode can be increased. Therefore, a matrix type display device with a large aperture ratio can be obtained. In addition, the organic insulating film 12
Since the insulation resistance is high, no leakage current occurs when the picture element electrode 10 is connected to the gate bus line 1 and the source bus line 9. Furthermore, since the dielectric constant of the organic insulating film 12 is small, the stray capacitance formed between the picture element electrode 10 and the gate bus wiring 1 and source bus wiring 9 is also small. Furthermore, since the organic insulating film 12 is formed by the spin code method and exhibits good leveling characteristics, it is formed to reliably cover the gate bus wiring 1 and the source bus wiring 9. Therefore, the picture element electrode 10
Even if the gate bus wiring 1 and the source bus wiring 9 are formed so as to overlap each other, no leakage current is generated between the picture element electrode 10 and the gate bus wiring 1 and the source bus wiring 9.
（発明の効果）
本発明のマ） ＩＪクス型表示装置の絵素電極は、走査
線及び信号線に重量して形成されているので、開口率の
大きな画面を有している。従って、本発明によれば、明
るい画面を有するマトリクス型表示装置が得られる。(Effects of the Invention) A) The picture element electrodes of the IJ box type display device are formed so as to overlap the scanning lines and the signal lines, so that the display device has a screen with a large aperture ratio. Therefore, according to the present invention, a matrix type display device having a bright screen can be obtained.
４、′−の な１日
第１Ａ図〜第１Ｇ図は本発明のマトリクス型表示装置の
製造工程を示す図、第２Ａ図〜第２Ｅ図は従来のマトリ
クス型表示装置の製造工程を示す図である。Figures 1A to 1G are diagrams showing the manufacturing process of the matrix type display device of the present invention, and Figures 2A to 2E are diagrams showing the manufacturing process of the conventional matrix type display device. It is.
１・・・ゲートバス配線、２・・・陽極酸化膜、３・・
・ゲート絶縁膜、４・・・半導体層、５・・・エツチン
グスト１バ、６・・・コンタクト層、７・・・ソース電
極、８・・・ドレイン電極、９・・・ソースバス配線、
１０・・・絵素電極、１１・・・ＴＦＴ、１２・・・有
機絶縁膜、スルーホール１５．２０・・・絶縁性基板。1... Gate bus wiring, 2... Anodic oxide film, 3...
- Gate insulating film, 4... Semiconductor layer, 5... Etching stop 1 bar, 6... Contact layer, 7... Source electrode, 8... Drain electrode, 9... Source bus wiring,
10... Picture element electrode, 11... TFT, 12... Organic insulating film, through hole 15.20... Insulating substrate.
以上that's all
Claims (1)
基板内面に配線された走査線及び信号線と、該走査線及
び該信号線に接続されたスイッチング素子と、該スイッ
チング素子の出力端子に接続された絵素電極と、を有す
るマトリクス型表示装置であって、 該走査線と該信号線と該スイッチング素子とを覆って形
成された有機絶縁膜と、該有機絶縁膜の該出力端子上の
部分に形成されたスルーホールと、を有し、該出力端子
と該絵素電極とが該スルーホールを介して電気的に接続
され、該絵素電極が該走査線及び該信号線と該有機絶縁
膜を挟んで重畳されているマトリクス型表示装置。[Claims] 1. A pair of insulating substrates, a scanning line and a signal line wired on the inner surface of one of the pair of substrates, and a switching element connected to the scanning line and the signal line. and a picture element electrode connected to an output terminal of the switching element, the organic insulating film being formed to cover the scanning line, the signal line, and the switching element; a through hole formed in a portion of the organic insulating film above the output terminal, the output terminal and the picture element electrode are electrically connected via the through hole, and the picture element electrode is electrically connected to the picture element electrode. A matrix display device in which the scanning line and the signal line are overlapped with the organic insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24171190A JP3151209B2 (en) | 1990-09-11 | 1990-09-11 | Manufacturing method of matrix type display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24171190A JP3151209B2 (en) | 1990-09-11 | 1990-09-11 | Manufacturing method of matrix type display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04120516A true JPH04120516A (en) | 1992-04-21 |
| JP3151209B2 JP3151209B2 (en) | 2001-04-03 |
Family
ID=17078400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24171190A Expired - Lifetime JP3151209B2 (en) | 1990-09-11 | 1990-09-11 | Manufacturing method of matrix type display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3151209B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05307194A (en) * | 1992-04-28 | 1993-11-19 | Semiconductor Energy Lab Co Ltd | Active matrix display device and its driving method |
| US5880797A (en) * | 1995-12-25 | 1999-03-09 | Sharp Kabushiki Kaisha | LCD with different surface free energies between insulator and pixel electrode |
-
1990
- 1990-09-11 JP JP24171190A patent/JP3151209B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05307194A (en) * | 1992-04-28 | 1993-11-19 | Semiconductor Energy Lab Co Ltd | Active matrix display device and its driving method |
| US5852488A (en) * | 1992-04-28 | 1998-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| US5880797A (en) * | 1995-12-25 | 1999-03-09 | Sharp Kabushiki Kaisha | LCD with different surface free energies between insulator and pixel electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3151209B2 (en) | 2001-04-03 |
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