JP3436487B2 - Active matrix substrate manufacturing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate, and more particularly to an active matrix substrate used in a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, active matrix liquid crystal display devices have been widely used. A substrate of an active matrix type liquid crystal display device provided with a plurality of gate wirings and source wirings intersecting each other and a switching element such as a thin film transistor (TFT) on the surface is called an active matrix substrate.

FIG. 5 shows a block diagram of a conventional active matrix substrate. FIG. 5A shows a plan view of one pixel portion of the active matrix substrate. FIG. 5B is the same as FIG.
It is sectional drawing corresponding to BB 'of (a).

The active matrix substrate 1 has a TFT 100 connected to a pixel electrode 17 via a gate wiring 2, a source wiring 20, and a connection electrode 110. TF
The T100, the gate wiring 2, the source wiring 20, and the connection electrode 110 are covered with the interlayer insulating film 15. A pixel electrode 17 is formed on the interlayer insulating film 15. The pixel electrode 17 is connected to the connection electrode 110 via a contact hole 16 provided in the interlayer insulating film 15. TFT
100 has a gate electrode 3, a gate insulating film 5, an amorphous Si layer 6, a source electrode contact layer 7a, a drain electrode contact layer 7b, a source electrode and a drain electrode. A channel region 14 is formed in the amorphous Si layer 6. The TFT 100, the gate wiring 2, the source wiring 20, and the connection electrode 110 are covered with the protective layer 13. In this example, the source electrode and the drain electrode have a two-layer structure composed of the first transparent conductive layers 9a and 9b and the metal layers 11a and 11b, respectively.

FIG. 5C is a sectional view corresponding to CC 'in FIG. 5A, showing a sectional view of the source wiring 20 portion. The source wiring 20 is formed on the active matrix substrate 1 and is covered with the interlayer insulating film 15. A pixel electrode 17 is formed on the interlayer insulating film 15. The source wiring 20 has a two-layer structure including the first transparent conductive layer 9 and the metal layer 11, and is covered with the protective layer 13. The source wiring 20 and the source electrode are integrally formed.

FIG. 6 shows a method of manufacturing the active matrix substrate shown in FIG.

First, the gate wiring 2 and the gate electrode 3 extending from the gate wiring 2 are formed on the substrate 1. Next, the gate insulating film 5, the amorphous Si layer 6, and the n ⁺ amorphous Si layer 7 are laminated in this order, and then the amorphous Si layer 6 and the n ⁺ amorphous Si layer 7 are formed in a predetermined pattern (see FIG. )reference).

Next, the first transparent conductive layer 9 and the metal layer 11
Is laminated on the entire substrate (see FIG. 6B). After that, the metal layer 11 is first patterned to form the upper layer of the source wiring, the upper layer 11a of the source electrode, and the upper layer 11 of the drain electrode.
b is formed. Then, the first transparent conductive layer 9 is patterned to form a lower layer of the source wiring, a lower layer 9a of the source electrode, a lower layer 9b of the drain electrode, and a connection electrode (FIG. 6).
(See (c)). This patterning is performed by a photolithography process using a resist.

After patterning the metal layer 11 and the first transparent conductive layer 9, an n ⁺ amorphous Si layer 7 and an amorphous Si layer are formed.
Layer 6 is etched and divided into source and drain electrodes to form TFT channel regions 14 (FIG. 6).
(D)).

After the channel region 14 is formed, a protective layer 13 that covers the TFT 100, the gate wiring 2, the source wiring, and the connection electrode is formed using SiNx or the like (FIG. 6 (e)).
reference). Next, the protective layer 13 at the position corresponding to the contact hole 16 on the connection electrode is removed (see FIG. 6F).

On top of this, an interlayer insulating film 1 is formed by using an organic resin.
5 is formed, and a contact hole 16 is formed in the obtained interlayer insulating film 15. A pixel electrode 17 connected to the connection electrode at the contact hole 16 is formed on the interlayer insulating film 15,
An active matrix substrate is completed (see FIG. 6 (g)).

Further, recently, in order to shorten the manufacturing process, a photolithography process using a resist is not performed when patterning the first transparent conductive layer 9, but the first transparent conductive layer 9 is not used. A manufacturing method has been devised in which the photolithography step is omitted by etching using the metal layer 11 formed on the mask as a mask (Japanese Patent Application No. 9-009156). The method will be described below. FIG. 7 shows a plan view and a sectional view of one pixel portion of an active matrix substrate obtained by this manufacturing method. Further, FIGS. 8A to 8G show the manufacturing process of the active matrix substrate. In this method, which omits the photolithography step, the first transparent conductive layer 9 is removed using the metal layer 11 as a mask (FIGS. 8B to 8E).
reference). Therefore, the metal layer 11 which was only on the drain electrode and the source electrode is also formed on the connection electrode 110 as shown in FIG. 7B.

By using the manufacturing method shown in FIG. 8, the photolithography step can be omitted once, and
It is possible to prevent defects due to defective patterning of the first transparent conductive layer in the photolithography process.

[0014]

However, the conventional manufacturing method shown in FIG. 8 has the following problems. First, T
Since the connection electrode 110 between the FT 100 and the pixel electrode 17 has a two-layer structure of the metal layer 11b and the transparent conductive layer 9b,
There is a problem that the aperture ratio of the pixel portion is reduced. Also,
The metal layer 11 is oxidized by plasma treatment at the time of etching the channel portion of the TFT in a later process and oxygen plasma treatment for eliminating contact failure in the hole portion after the formation of the contact hole, so that the connection electrode 110 and the pixel electrode 1 are oxidized.
There was a problem that the contact resistance with No. 7 became large, the adhesiveness was insufficient, and film peeling might occur.

Further, the external connection terminal for electrically connecting the gate wiring 2 to the outside has the following problems. FIG. 4A schematically shows the entire liquid crystal panel. FIG. 4B is an enlarged view of a portion surrounded by a circle in FIG.
4C is a sectional view taken along line CD of the external connection terminal 200c for electrically connecting the gate wiring 2 to the outside.

The external connection terminal 200c includes a metal layer 2, a gate insulating film 5 ', a first transparent conductive layer 9', a metal layer 11 ', a protective layer 13' and a second transparent conductive layer 17 '.
The gate insulating film 5 ′, the first transparent conductive layer 9 ′, the metal layer 11 ′ protective layer 13 ′, and the second transparent conductive layer 17 ′ are, respectively,
The gate insulating film 5, the first transparent conductive layer 9, the metal layer 11, the protective layer 13, and the pixel electrode 17 in the pixel region are formed at the same time. The external connection terminal 200c for electrically connecting the gate wiring 2 to the outside is formed of the first transparent conductive layer 200c as shown in FIG. The metal layer 11 'is sandwiched between the conductive layer 9'and the transparent conductive layer 17'. Due to the weak adhesion between the metal layer 11 'and the transparent conductive layer 9', there is a problem that film peeling occurs from this portion.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing an active matrix substrate capable of preventing a decrease in aperture ratio of a pixel portion. Further, another object of the present invention is to
It is an object of the present invention to provide a method for manufacturing an active matrix substrate, which can solve the problems of contact resistance increase and film peeling due to surface oxidation of a metal layer.

[0018]

A method of manufacturing an active matrix substrate according to the present invention comprises a gate wiring, a source wiring, a switching element connected to a pixel electrode via the gate wiring, the source wiring and a connection electrode. A method of manufacturing an active matrix substrate having: (a) a step of forming a first transparent conductive layer on the substrate on which the switching element is formed; and (b) a metal layer on the first transparent conductive layer. And (c) the source wiring having a two-layer structure of the first transparent conductive layer and the metal layer by etching the first transparent conductive layer and the metal layer in the same pattern. A step of forming a connection electrode, (d) a step of forming a protective layer covering at least the source wiring and the connection electrode, (e) the switching element, the gate wiring, and the source wiring, A step of forming an interlayer insulating film covering the connection electrode, (f) a step of forming a contact hole on the connection electrode of the interlayer insulating film, and (g) a position corresponding to at least the contact hole of the connection electrode. Forming a first contact portion for connecting the pixel electrode to the connection electrode by etching the protective layer in the same pattern as the metal layer of the connection electrode; and (h) forming the interlayer insulating film. Forming a second transparent conductive layer that covers and is connected to the connection electrode at the first contact portion; and (i)
By patterning the second transparent conductive layer,
And the step of forming the pixel electrode, whereby the above object is achieved.

The method further comprises an external connection terminal for electrically connecting the gate wiring to the outside, and the step (c) includes
The step of forming an external connection terminal having a two-layer structure of the first transparent conductive layer and the metal layer by etching the first transparent conductive layer and the metal layer in the same pattern, (D) includes a step of forming a protective layer covering the external connection terminal, and in the step (g), the protective layer on the external connection terminal is formed in the same pattern as the metal layer of the external connection terminal. The method may include a step of forming a second contact portion in which the first transparent conductive layer is exposed on the external connection terminal by etching with.

In the step (g), the protective electrode on the connection electrode and the metal layer of the connection electrode are etched in the same pattern to form the connection electrode composed of the first transparent conductive layer. Steps may be included.

Production of the active matrix substrate of the present invention
The method includes a gate wiring, a source wiring, the gate wiring,
A method for manufacturing an active matrix substrate having a switching element connected to a pixel electrode via the source wiring and a connection electrode, comprising: (a) a gate wiring and a switch.
On the substrate on which the gate electrode of the
A gate insulating film, and further, the switch is formed on the gate insulating film.
After forming the semiconductor layer that constitutes the etching element, the first
Forming a transparent conductive layer, forming a metal layer on the (b) Then, the first transparent conductive layer, followed by (c),
By etching the first transparent conductive layer and the metal layer in the same pattern, a connection electrode having a two-layer structure of the first transparent conductive layer and the metal layer is formed together with a source wiring. And (d) the step formed on the substrate.
Connection with switching element, gate wiring, source wiring
A step of forming an interlayer insulating film that covers at least the electrode ,
(E) Next, a contact hole is formed on the connection electrode of the interlayer insulating film by etching using a mask, and gold of the connection electrode corresponding to the contact hole is formed.
The metal layer is removed and the pixel electrode is connected to the connection electrode.
Forming a Ntakuto portion, a second transparent conductive layer to be connected to (f) Then, the connection electrodes in the contour <br/> transfected unit, before
Forming a serial interlayer insulating film and the contact hole, (g) then, by patterning the second transparent conductive layer, includes forming a pixel electrode, and by the above-described object Is achieved.

The first and second transparent conductive layers may be formed using indium tin oxide.

The gate wiring and the switching element
The child gate electrode may be formed using at least one of Ta, Mo, Cr, Ti, and a nitride thereof.

In the step of forming the connection electrode, C
At least one of F ₄ , SF ₆ , BCl ₃ , and HCl gas
You may etch using one.

The step (c) includes a step of etching the metal layer using the first transparent conductive layer as an etching stopper, and then etching the first transparent conductive layer using the metal layer as a mask. Good.

The step (g) may include a step of forming a second transparent conductive layer on the first transparent conductive layer of the external connection terminal.

The operation will be described below.

In the method for manufacturing an active matrix substrate of the present invention, the transparent conductive layer and the metal layer are etched in the same pattern to form a source wiring and a connection electrode having a two-layer structure composed of the transparent conductive layer and the metal layer. And the photolithography step for patterning the transparent conductive layer can be omitted. Further, at least the protective layer of the protective layer covering the connection electrode at a position corresponding to the contact hole of the connection electrode is etched in the same pattern as the metal layer of the connection electrode.

Further, in the method for manufacturing an active matrix substrate of the present invention, the source wiring having a two-layer structure composed of the transparent conductive layer and the metal layer is formed by etching the transparent conductive layer and the metal layer in the same pattern. A connection electrode and an external connection terminal are formed, at least the source wiring and the connection electrode are covered with an interlayer insulating film, and at least an interlayer insulation film at a position corresponding to the contact hole of the connecting electrode portion corresponds to the external connection terminal and the contact hole. Etching is performed in the same pattern as that of the metal layer at the desired position. According to such a manufacturing method of the active matrix substrate, the photolithography step at the time of patterning the transparent conductive layer layer can be reduced once, and the metal layer sandwiched between the transparent conductive layers of the external connection terminals can be removed. .

[0030]

The above and other objects and advantages of the present invention will become apparent upon consideration of the following detailed description with reference to the accompanying drawings. In the drawings, the same elements are designated by the same reference numerals.

(Embodiment 1) FIG. 1A shows a plan view of one pixel portion manufactured by the method of Embodiment 1 of the active matrix substrate of the present invention. FIG. 1B is the same as FIG.
It is sectional drawing corresponding to BB 'of (a). Figure 1 (c)
FIG. 3 is a sectional view corresponding to CC ′ in FIG.

FIG. 2 shows a method of manufacturing the active matrix substrate shown in FIG. The method of manufacturing the active matrix substrate will be described below with reference to FIG.

First, on the substrate, Ta, Mo, Cr, T
After depositing at least one of i and its nitride by a sputtering method, patterning is performed to form the gate wiring 2, the gate electrode 3 extending from the gate wiring 2, and the capacitor wiring 4. The substrate only needs to be formed of a material having an insulating property on its surface, and is formed of, for example, glass. An insulating film such as Ta ₂ O ₅ and SiO ₂ may be formed on the surface of the substrate as a base coat film. The capacitance wiring 4 may also serve as the gate wiring 2.

Next, the gate insulating film 5 is laminated on the gate electrode 3. In the present embodiment, for example, a SiNx film is laminated by a plasma chemical vapor deposition (P-CVD) method,
A gate insulating film is formed. The gate electrode may be anodized to improve the insulating property to form the first gate insulating film, and the insulating film deposited by CVD or the like may be used as the second insulating film.

Subsequently, the amorphous Si (semiconductor) layer 6
Is laminated on the gate insulating film 5 by the CVD method. Then, impurity-doped n ⁺ to be the source electrode contact layer 7a and the drain electrode contact layer 7b
Type amorphous Si or n ⁺ type microcrystalline Si layer 7
Are laminated on the amorphous Si layer 6 by the plasma CVD method.

Both the n ⁺ type amorphous Si or the n ⁺ type microcrystalline Si layer 7 doped with impurities and the amorphous Si layer 6 were patterned into islands. A dry etching method using a mixed gas of HCl and SF ₆ was adopted for etching. CF ₄ as etching gas
And a mixed gas of O ₂ or the like BCl _3, may be used. Further, as the Si etching liquid, HF + HNO ₃
Etching may be performed by wet etching using, etc. (see FIG. 2A).

Next, a transparent conductive layer 9 such as indium tin oxide (ITO) is laminated by a sputtering method, and then a metal layer 11 such as Ta, Ti and Al is laminated (see FIG. 2B). .

Next, the metal layer 11 is etched by using the transparent conductive layer 9 as an etching stopper. The etching is performed by dry etching using a mixed gas of CF ₄ and O ₂ , wet etching using a mixed solution of HF + HNO ₃ or wet etching using BCl ₃ or Cl ₂ . After etching the metal layer 11, the transparent conductive layer 9 is continuously etched (see FIG. 2C). At this time,
Since the first transparent conductive layer 9 is etched by using the upper metal layer 11 as a mask, the transparent conductive layer 9 has the same pattern as the upper metal layer 11. The transparent conductive layer 9 not only acts as an etching stopper for the metal layer 11, but also serves as the source electrode contact layer 7a and the drain electrode contact layer 7b, and is doped with impurities such as n ⁺ type amorphous Si or n ⁺ type microcrystalline Si layer. 7 to get good contact. As described above, the source wiring having the two-layer structure of the first transparent conductive layer 9 and the metal layer 11 and the connection electrode can be formed. Further, as described later, at this time, an external connection terminal having a two-layer structure of a first transparent conductive layer for electrically connecting the gate wiring to the outside and a metal layer may be formed.

Next, the n ⁺ type amorphous Si or n ⁺ type microcrystalline Si layer 7 doped with impurities on the amorphous Si (semiconductor layer) 6 is etched to form the source electrode contact layer 7a and the drain electrode contact layer 7
b, and the channel region 14 is formed (FIG. 2D).
reference).

Next, the protective layer 13 is laminated on the substrate by the CVD method (see FIG. 2 (e)). The protective layer 13 is formed using, for example, SiNx. Next, the protection layer 13 is patterned. At this time, as shown in FIG. 1B, the protective layer on the connection electrode 110 is also removed, and the protective layer 13 and the metal layer on the connection electrode 110 are formed by using, for example, a mixed gas of CF ₄ and O _2. 11 and 11 are simultaneously etched by the dry etching method. As described above, the etching method may be dry etching using BCl ₃ or SF ₆ gas. Alternatively, the protective layer on the connection electrode 110 may be etched using an HF-based solution, and then the metal layer 11 on the connection electrode 110 may be dry-etched or wet-etched.

After forming the protective layer 13, an interlayer insulating film 15 covering the TFT 100, the gate wiring 2, the source wiring, and the connection electrode 110 is formed. The interlayer insulating film 15 is formed by, for example, a photosensitive acrylic organic resin film by a spin coating method. After that, a contact hole 16 is formed on the connection electrode of the interlayer insulating film 15. Contact hole 1
6 exposes the organic resin according to a predetermined pattern,
It can be formed by treating with an alkaline solution or an organic solvent. Alternatively, after applying an organic resin film and patterning with a photoresist, dry etching may be performed with, for example, a mixed gas of CF ₄ and O ₂ .

As described above, by etching the protective layer in the same pattern as the metal layer, the first contact portion for connecting the pixel electrode 17 is formed at a position corresponding to the contact hole on the connection electrode. . Further, the connection electrode 110 composed of the first transparent conductive layer 9 is formed (FIG. 2).
(See (f)).

Further, in the external connection terminal for electrically connecting the gate wiring to the outside, the second contact portion in which the first transparent conductive layer 9'is exposed is formed.

Finally, a second transparent conductive layer of ITO or the like, which will be the pixel electrode 17, is formed by a sputtering method so as to cover the interlayer insulating film 15 and connect to the connection electrode 110 at the first contact portion, and the predetermined thickness is obtained. The pixel electrode 17 is formed by patterning in the shape of (see FIG. 2G).

A sectional view of an external connection terminal 200d for electrically connecting the gate wiring on the active matrix substrate manufactured by the manufacturing method of this embodiment to the outside is shown in (d). According to the manufacturing method of the present embodiment, the external connection terminal 200d has a pattern in which the protective layer on the first transparent conductive layer 9'is removed. In the conventional method, as shown in FIG. 4C, the metal layer 11 'is sandwiched between the lower transparent conductive layer 9'and the transparent conductive layer 17'. By patterning the protective layer 13 and simultaneously etching the protective layer 13 'and the metal layer 11', the structure shown in FIG. 4D is obtained, and the first transparent conductive layer is formed in the external connection terminal of the gate wiring. The metal layer 11 'sandwiched between 9'and the second transparent conductive layer 17' can be removed.

The active matrix substrate thus formed and a color filter substrate (not shown) on which a counter electrode and a color filter are formed are attached to each other with a predetermined gap therebetween, liquid crystal is sealed in the gap, and a drive circuit (not shown) is attached. And a lighting device are combined to complete the liquid crystal display device by the process of the present invention.

As described above, according to the method of manufacturing the active matrix substrate of the first embodiment, the connection electrode 110 is formed.
Since the metal layer can be removed, it is possible to prevent a reduction in the aperture ratio of the pixel portion.

Further, since the protective layer 13 and the metal layer 11 are simultaneously etched after the patterning of the protective layer 13, the metal layer sandwiched between the transparent conductive layers can be removed. Therefore, the problem of film peeling can be solved, and further,
It is possible to prevent an increase in contact resistance due to the oxidation of the metal layer. In addition, when patterning the transparent conductive layer, the photolithography process can be reduced once.

(Embodiment 2) FIG. 3G is a sectional view of one pixel portion of an active matrix substrate manufactured by the method of Embodiment 2 of the present invention. 3 (a)-(g)
9A to 9C show a method of manufacturing the active matrix substrate shown in the second embodiment. Hereinafter, a method of manufacturing the active matrix substrate will be described with reference to FIG. This embodiment is different from the manufacturing process of the above-described first embodiment in the following points.

In this embodiment, after forming the channel region 14 without forming a TFT protective layer such as formed by using SiNx, immediately after, for example, the substrate on which the metal layer 11 is formed, for example, Acrylic organic resin is applied by spin coating method (dielectric constant of organic resin is about 3.7μ
m, and the film thickness is about 3 μm), the interlayer insulating film 15 that covers the TFT 110, the gate wiring 2, the source wiring, and the connection electrode 110 is formed (see FIG. 3E).

Next, the interlayer insulating film 15 and the metal layer 11 are patterned by a photoresist using the same pattern, and dry etching is performed using a mask using a mixed gas of CF ₄ and O ₂ or the like to form an interlayer. A contact hole 16 is formed on the connection electrode 110 of the insulating film 15. At the same time, in the external connection terminal of the gate wiring, the interlayer insulating film on the connection terminal is removed (see FIG. 3F). As described above, SF ₆ , BCl ₃ or the like may be used in addition to CF ₄ + O ₂ gas as the dry etching method. Alternatively, wet etching may be performed. Next, by etching using the same mask as above, the metal layer 11 at the position corresponding to the contact hole of the connection electrode 110 is removed, and the pixel electrode 1 is formed on the connection electrode 110.
A first contact portion for connecting 7 is formed. Further, in the external connection terminal of the gate wiring, the metal layer 1
1'is removed to form a second contact portion in which the first transparent conductive layer 9'of the external connection terminal is exposed.

Next, the connection electrode 110 is formed at the first contact portion.
And the transparent conductive layer 9 ′ in the external connection terminal.
A second transparent conductive layer is formed so as to cover the exposed second contact portion.

Finally, by patterning the second transparent conductive layer, the pixel electrode 17 and the first transparent conductive layer 9 '
And the external connection terminal 200d having a two-layer structure with the second transparent conductive layer 17 'is formed.

In the case of this embodiment, the metal layer 11 remains on the connection electrode 110 as shown in FIG. 3G, but the metal layer 11 can be removed from the contact portion 16.
Further, in the external connection terminal 200d of the gate wiring,
As shown in FIG. 3D, the metal layer 11 'sandwiched between the transparent conductive layers 9'and 17' can be removed.

According to the method for manufacturing an active matrix substrate of Embodiment 2 of the present invention, since the interlayer insulating film 15 and the metal layer 11 are simultaneously etched after the patterning of the interlayer insulating film 15, the metal sandwiched between the transparent conductive layers is formed. The layer can be removed. Therefore, the problem of film peeling can be solved, and further, increase in contact resistance due to oxidation of the metal layer can be prevented. In addition, when patterning the transparent conductive layer, the photolithography process can be reduced once.

[0056]

As described in detail above, according to the method for manufacturing an active matrix substrate of the present invention, the photolithography process is reduced when patterning the transparent conductive layer while maintaining the performance of the conventional active matrix substrate. It is possible to provide an active matrix substrate that can prevent the decrease of the aperture ratio of the pixel portion.

Further, it is possible to solve the problems of increase in contact resistance and film peeling due to oxidation of the metal layer.

[Brief description of drawings]

1A and 1B are diagrams showing an active matrix substrate manufactured by a manufacturing method of the present invention, in which FIG. 1A is a plan view of one pixel portion, FIG. 1B is a sectional view taken along line BB ′, and FIG. −
It is a C'sectional view.

FIG. 2 is a diagram showing a manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing method according to the second embodiment of the present invention.

4A is an overall view of a liquid crystal panel, FIG. 4B is an enlarged view of an external connection terminal of a gate wiring, and FIG. 4C is a CD cross section of the external connection terminal formed by a conventional shortening process. Figure,
(D) is CD sectional drawing of the external connection terminal manufactured by the manufacturing method of this invention.

5A and 5B are diagrams showing an active matrix substrate manufactured by a conventional manufacturing method, in which FIG. 5A is a plan view of one pixel portion, FIG. 5B is a sectional view taken along line BB ′, and FIG. C '
FIG.

FIG. 6 is a diagram showing a conventional manufacturing method.

7A and 7B are diagrams showing an active matrix substrate manufactured by a conventional shortening manufacturing method, in which FIG. 7A is a plan view of one pixel portion, FIG. 7B is a sectional view taken along line BB ′, and FIG. −
It is a C'sectional view.

FIG. 8 is a diagram showing a conventional shortening manufacturing method.

[Explanation of symbols]

1 substrate 2 gate wiring 3 Gate electrode 4 capacitance wiring 5 Gate insulation film 6 Amorphous Si layer 7a Source electrode contact layer 7b Drain electrode contact layer 9 Transparent conductive layer 11 metal layer 13 Protective layer 14 channel area 15 Interlayer insulation film 16 contact holes 17 pixel electrodes 20 source wiring 100 TFT 110 connection electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Fujikawa 22-22 Nagaike-cho, Abeno-ku, Osaka City, Osaka Prefecture Sharp Corporation (56) References JP-A-9-325330 (JP, A) JP-A-9- 152625 (JP, A) JP 5-289105 (JP, A) JP 4-276723 (JP, A) JP 4-136919 (JP, A) JP 5-297415 (JP, A) JP-A-57-205712 (JP, A) JP-A-63-9977 (JP, A) JP-A-6-273782 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/13-1/141

Claims (5)

(57) [Claims] 1. A method of manufacturing an active matrix substrate having a gate wiring, a source wiring, and a switching element connected to the pixel electrode via the gate wiring, the source wiring, and a connection electrode, comprising: After forming a gate insulating film on the substrate on which the gate wiring and the gate electrode of the switching element are formed, and further forming a semiconductor layer forming the switching element on the gate insulating film, a first transparent conductive layer is formed. A step of forming, (b) a step of forming a metal layer on the first transparent conductive layer, and (c) a step of etching the first transparent conductive layer and the metal layer in the same pattern. A step of forming a connection electrode having a two-layer structure of the first transparent conductive layer and the metal layer together with a source wiring, and (d) a switchon formed on the substrate thereafter. A step of forming an interlayer insulating film that covers at least the element, the gate wiring, the source wiring, and the connection electrode; (e) Next, a contact hole is formed on the connection electrode of the interlayer insulation film by etching using a mask. A step of forming and forming a contact portion for connecting the pixel electrode to the connection electrode by removing the metal layer of the connection electrode corresponding to the contact hole, and (f) then forming the contact electrode at the contact portion. A step of forming a second transparent conductive layer to be connected on the interlayer insulating film and in the contact hole; and (g) then patterning the second transparent conductive layer to form a pixel electrode. A method for manufacturing an active matrix substrate including the following. 2. The method of manufacturing an active matrix substrate according to claim 1, wherein the first and second transparent conductive layers are formed using indium tin oxide. 3. The gate wiring and the switching
The method of manufacturing an active matrix substrate according to claim 1, wherein the gate electrode of the element is formed using at least one of Ta, Mo, Cr, Ti, and a nitride thereof. 4. In the step of forming the connection electrode,
The method for manufacturing an active matrix substrate according to claim 1, wherein etching is performed using at least one of CF ₄ , SF ₆ , BCl ₃ , and HCl gas. 5. The step (c) includes a step of etching the metal layer using the first transparent conductive layer as an etching stopper and then etching the first transparent conductive layer using the metal layer as a mask. The method for manufacturing an active matrix substrate according to claim 1 .