JPH04111444A - Manufacture of dielectric isolation substrate - Google Patents

Abstract

PURPOSE:To solve conventional defects caused by lamination and polishing of substrates, to make accuracy of groove formation unnecessary excepting on a depth of a groove and to enable remarkable improvement of operativity by making a groove of one single crystalline silicon substrate deeper than a groove of the other substrate. CONSTITUTION:A V-shaped groove 25 of a depth H1 is formed on a surface of a single crystalline silicon substrate 15 by anisotropic etching to make a region 40 remain which becomes a single crystalline silicon island region later, and an oxide film 35 is formed through thermal oxidation of a surface thereof. A groove 26 of a depth H2 which is shallower than the groove 25 is formed by anisotropic etching on a surface of a single crystalline silicon substrate 16 corresponding to the region 40 of the substrate 15 as a supportor layer. A thermal oxidation film 36 is formed by heat treatment and a land part is formed between grooves 26 of the substrate 16. Thereby, a clearance is produced, between the groove 25 and the land part between grooves 26 received thereby during lamination. The clearance part is removed later by polishing. Remaining bubbles can escape outside owing to the clearance.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor substrate formed by forming a thin semiconductor layer of silicon or the like on an insulating film, and more specifically, a method of manufacturing a semiconductor substrate by forming a thin semiconductor layer of silicon or the like on an insulating film. This invention relates to a method of manufacturing a dielectric isolation substrate using adhesive technology.

[Prior Art] In general, in the production of dielectric isolation substrates that use dielectrics to isolate elements in bipolar devices, polycrystalline silicon is deposited by CVD on a monocrystalline silicon support having grooves and a dielectric film formed on the entire surface. A method is to form a silicon thin film and cut the surface portion. However, this method has drawbacks such as large warping of the substrate due to the difference in coefficient of thermal expansion between single crystal silicon and polycrystalline silicon, and CVD requiring a relatively long time.

Recently, as a method to solve these drawbacks, a method has been proposed in which silicon wafers are bonded together directly or with an oxide film interposed to form a substrate, and a portion of this is removed. This is disclosed in Japanese Patent Application Laid-Open No. 1-1113411.

Figures 2(a)-(b) summarize the techniques shown therein. In other words, in this technology, as shown in Fig. 3 (a
), a single crystal silicon substrate 10 having a (100) plane has a (111) wall surface by anisotropic etching technique.
A groove 20 serving as a surface is formed, and then a thermal oxide film 30 is grown on the surface of the single crystal silicon substrate including the groove 20 to form one substrate. Next, as shown in FIG. 2(b), grooves 21 matching the shape of the portions between the grooves 20 on the surface of the single crystal silicon substrate 10 are formed on the surface of the other single crystal silicon substrate 11 by anisotropic etching. Then, a thermal oxide film 31 is formed on the surface to form a support layer.

Next, as shown in FIG. 2(C), the substrates 10 and 11 are subjected to hydrophilic treatment, and then the two are stacked and heat treated at a temperature of 700° C. or higher to bond the oxide films 30 and 31 and bond them together. conduct.

Next, as shown in FIG. 2(d), the line X-
Polishing is performed to the plane indicated by X to obtain single crystal silicon islands 12 completely separated by oxide films 30.degree. 31. In this way, a dielectric separator substrate having the single crystal silicon substrate 11 as a support layer is obtained.

[Problems to be Solved by the Invention] In the conventional bonding method described above, in forming the grooves 20 and 21 by anisotropic etching, the depths Hl and H2 and the widths W1 and W2 are accurately set to Hl-H2, Wl-W
It is necessary to set it to 2. Therefore, anisotropic etching must be performed with high precision using a high precision mask. However, even if processing is performed with such precision, it is practically impossible to completely eliminate variations in processing.

In particular, if the depth of the groove is Hl<H2, gaps will be created during bonding as shown in Figure 3.
If polishing is performed in this state, the single-crystal silicon island portion will fall off, and as a result, the quality of other surrounding substrates will be impaired, causing a major problem in terms of quality and yield.

Furthermore, warping of the wafer is a problem in bonding. If such warpage occurs, local adhesion occurs in the initial stage of adhesion, while other parts remain unadhered, which may result in air bubbles remaining after adhesion is completed. This is also true if there is a difference in the depth of the grooves to avoid such bubbles.
A method of bonding in a vacuum, or Japanese Patent Application Laid-Open No. 81-145
As shown in Publication No. 839, a method has been proposed in which the center of the wafer is bent to form a convex shape so that bonding is performed from the center to the periphery, but the former method requires large-scale The latter requires a special vacuum device, and the latter requires a special bonding jig, which is economically disadvantageous.

An object of the present invention is to provide a semiconductor substrate bonding technique that prevents the formation of voids even if the depth varies when grooves are formed.

Another object of the present invention is to provide a semiconductor substrate bonding technique in which voids are actively formed on the surfaces of substrates to be bonded, and air bubbles left behind during bonding can escape to the outside.

These techniques allow high-quality dielectrically isolated semiconductor devices to be manufactured with good yield.

[Means for Solving the Problems] When forming grooves to be brought into close contact with each other on the surface of the first single-crystal silicon substrate for support and the surface of the \s2 single-crystal silicon substrate for forming single-crystal silicon islands, The depth of the groove in the second single-crystal silicon substrate is made larger than the depth of the groove in the first single-crystal silicon substrate.

[Function] By providing such a difference in the depth of the respective grooves of the first and second single crystal silicon substrates, when bonding, the grooves of the second single crystal silicon and the first single crystal which are received therein are A gap is created between the land portions between the grooves of the silicon substrate. This void portion will be removed by subsequent polishing. This gap allows residual air bubbles to escape to the outside.

[Example] An example of the present invention will be described based on FIGS. 1(a) to 1(d).

First, as shown in FIG. 1(a), the surface of a single crystal silicon substrate 15 having a (100) plane is etched to a depth Hl by anisotropic etching so as to leave a region 40 that will later become a single crystal silicon substrate region. A V-shaped groove 25 is formed, and the surface thereof is thermally oxidized to form an oxide film 35.

Next, as shown in FIG. 1(b), (10
0) On the surface of the single crystal silicon substrate 16 having a surface, a groove 26 corresponding to the region 40 of the substrate 15 and having a depth H2 smaller than the depth of the groove 25 is formed by anisotropic etching, and a thermal oxide film is formed by heat treatment. 36 are formed, and land portions are formed between the grooves 26 of the substrate 16. Here, it is assumed that the depth H2 of the groove 25 in the substrate 16 corresponds to the thickness of the single crystal silicon island to be obtained as a result. The opening width W1 of the grooves 25 of the substrate 15 is equal to the width W2 of the base of the land portion between the grooves 26 of the substrate 16.

Next, as shown in FIG. 1(C), a single crystal silicon substrate 1
After applying hydrophilic treatment to No. 5 and No. 16 and pasting them together so that the grooves and land portions overlap, heat treatment is performed at a temperature of 700° C. or higher in a steam or dry oxygen atmosphere. As a result, the oxide films 35 and 36 are combined, and the substrates 15 and 16 are bonded together.

At this stage, residual air bubbles due to warping of the substrate can move through the gap between the groove 25 of the substrate 15 and the land between the groove 26 of the substrate 16. Therefore, by forming these holes 25 so as to extend over the entire substrate 15, air bubbles can escape to the outside.

Next, as shown in FIG. 1(d), the line x- in FIG. 1(c)
By polishing to the position indicated by x', a single crystal silicon island 17 is obtained. This island 17 is a bonded oxide film 35
．． completely separated by 36.

In the present invention, the depth Hl of the groove 25 of the substrate 15 is
For the height H2 of the land portion between the grooves 26 of No. 6, Hl>H2
It is. If this condition is satisfied, even if there is a difference between the opening width W1 of the groove 25 and the base width W2 of the land portion between the grooves 26, no major problem will actually occur.

For example, when Wl>W2, a gap is created between the groove 25 of the substrate 15 and the land between the groove 26 of the substrate 16 after bonding, but the groove 26 and the land between the groove 25 of the substrate 15 are in close contact. Therefore, the monocrystalline silicon island 17 as a result of polishing
does not fall off, and if Wl < W2, groove 2
Although a gap is formed between the groove 26 and the land between the grooves 25, the resulting silicon islands are in close contact with the side walls of the grooves 26 and do not fall off.

[Effects of the Invention] According to the present invention, the depth of the grooves in one single-crystal silicon substrate is made greater than the depth of the grooves in the other substrate, and all the conventional drawbacks caused by bonding and polishing the two substrates are solved. be done. Further, the precision required in the conventional groove formation process is no longer necessary except for the groove depth, and work efficiency is significantly improved. Note that the present invention is applicable not only to the production of 1[body-separated substrates but also to the production of So1 substrates using wafer bonding technology, for example.

[Brief explanation of drawings]

FIGS. 1(a)-(d) are diagrams showing an embodiment of the method of the present invention, FIGS. 2(a)-(d) are diagrams showing a conventional method,
FIG. 3 is a diagram illustrating one of the drawbacks in the conventional method. 15.16... Single crystal silicon substrate, 17... Single crystal silicon island, 25.26... Groove, 35.36...
Thermal oxide film. Figure 1 of the diagram of the present invention

Claims (3)

[Claims] (1) A method for manufacturing a dielectric isolation substrate comprising the following steps. (a) Forming a plurality of first grooves on one main surface of the first single crystal silicon substrate by anisotropic etching. (b) A second groove having a depth smaller than the depth of the first groove corresponds to the land portion formed between the first grooves on one main surface of the second single crystal silicon substrate. A step of forming by anisotropic etching. (c) forming a thermally oxidized silicon film by heat-treating one main surface of the first and second single-crystal silicon substrates; (d) Performing hydrophilic treatment on the first and second single crystal silicon substrates. (E) A step of bonding the first and second single crystal silicon substrates so that the thermally oxidized silicon films overlap. (f) A step of heat-treating the bonded single crystal silicon substrate to bond the thermally oxidized silicon films to each other. (G) Polishing the bonded single-crystal silicon substrates from the first single-crystal silicon substrate side to form a single-crystal silicon island in the second groove of the second single-crystal silicon substrate. . (2) Manufacturing the dielectric isolation substrate according to claim 1, wherein the first groove of the first single crystal silicon substrate in the step (a) is formed so as to extend over the entire substrate. Method. (3) The method for manufacturing a dielectrically separated substrate according to claim 1 or 2, wherein the heat treatment in step (f) is performed at a temperature of 700° C. or higher in a steam or dry oxygen atmosphere.