JPH04196340A - Dielectrics isolation substrate and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate the occurrence of outer peripheral polishing sag thereby avoiding the stain and separation of a wafer in the later steps by covering the peripheral part of an isolation substrate with a single crystal semiconductor. CONSTITUTION:The peripheral parts of an isolation substrate 5 are scraped off to reduce the diameter of the substrate and after bonding the substrate 5 onto the single crystal Si substrate 6 to be a supporting body, both substrate 5, 6 are joined to each other using produced silicon oxide by thermal oxidation step in oxidizing atmosphere to form a joined substrate 71. At this time, in order to bond together both substrates 5, 6, the occurrence of non-bonded part on the periphery of the contact surface 51 can be avoided by making the diameter of single crystal Si substrate 6 larger than that of the standard diameter so as to stick the isolation substrate 5 to the single crystal Si substrate 6 not through the intermediary of a bonding layer thereby making no gaps at the outer-most end of the bonding substrate 51. Through these procedures, the polishing sag can be perfectly removed thereby avoiding the separation from the wafer bonding surface 51 due to local etching step.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a dielectric isolation substrate using a bonding technique and a method for manufacturing the same.

[Conventional technology] Of the integrated circuit isolation technologies, the dielectric isolation method uses an insulator such as silicon oxide or silicon nitride as an insulating layer, so the withstand voltage between the isolation regions is high and high frequency It has excellent characteristics.

A conventional method for manufacturing a dielectric isolation substrate will be described with reference to FIG. In FIG. 4(a), separation grooves 2 having the required number and shape are formed on the entire surface of a single crystal 81 substrate 1 by etching, etc., and an 8102 film or the like is formed on the surface where the second separation groove 2 is formed and on the back surface. An insulating film 13.23 is deposited.

Next, as shown in FIG. 3(b), a polycrystalline S1 layer 4 is deposited on the insulating film 3 by vapor phase growth reaction, etc., and then, as shown in FIG.
), the surface of the polycrystalline S1 layer 4 is ground and polished to produce a separation substrate 5. Furthermore, as shown in FIG. 5(d), in order to bond the single crystal 81 substrate 6, which will become the other support, to the polished surface of the separation substrate 5,
A glass adhesive layer 50 containing impurities is provided. and,
As shown in FIG. 5E, the aforementioned single crystal Si substrate 6 is bonded to the separation substrate 5 via the adhesive layer 5°. After bonding, the single crystal 81 substrate 1 is ground and polished from the insulating film 23 side to produce a dielectric isolation substrate 7 as shown in FIG.

Note that, for example, Japanese Patent Publication No. 58-4518'2 may be mentioned as related to this type of manufacturing method.

[Challenges to be solved by the invention] The conventional method of bonding dielectric isolation substrates is an application of one of the semiconductor substrate bonding techniques, in which the substrates are heated and oxidized in an oxidizing atmosphere and bonded using silicon oxide. Since this method does not use an adhesive layer containing impurities, diffusion of impurities can be prevented. However, in the separation substrate, a polishing sag 52 on the outer periphery of about 5 to 10 pm occurs due to mechanical or chemical factors during the polishing process, as shown in FIG. Because of this outer periphery polishing sag 52, a minute gap 8 is formed at the extreme end of the bonding surface 51 of the separation substrate 5 and the single crystal 81 substrate 6 serving as the other support. If such a gap 8 is formed, cleaning liquid or etching liquid will remain in the gap 8 during cleaning or etching in the so-called post-wafer process, contaminating the wafer, and leaking from the gap 8. There is a problem in that the bonded wafers tend to peel off due to local etching or some external force.

In addition, with conventional dielectric separation substrates, if the diameters of the separation substrate and the single crystal 81 substrate serving as the support are the same, the periphery of the bonding surface may be distorted due to eccentricity or misalignment during assembly. There is also a problem in that it takes a long time to determine the bonding position because unbonded parts occur.

An object of the present invention is to provide a dielectric isolation substrate and a method for manufacturing the same, which can prevent contamination and peeling of the wafer in a post-wafer process by avoiding the occurrence of polishing sag on the outer periphery.

Another object of the present invention is to provide a dielectric separation substrate that does not cause unbonded parts without taking time for positioning the separation substrate and the support when the separation substrate and the support are bonded together. An object of the present invention is to provide a manufacturing method.

[Means to solve the problem]

To achieve the above object, the present invention provides an insulating film formed on a single crystal semiconductor having an isolation trench, a polycrystalline semiconductor deposited on the insulating film, and deposited in the isolation trench. In a dielectric separation substrate comprising a separation substrate in which the single crystal semiconductor is electrically insulated by the polycrystalline semiconductor, and a support bonded to a surface of the polycrystalline semiconductor, a peripheral edge of the separation substrate is covered with a single crystal semiconductor.

Furthermore, the present invention involves forming an insulating film on the surface of a single crystal semiconductor substrate having a separation groove, removing the insulating film from a certain area from the periphery of the substrate to expose the single crystal semiconductor substrate, and then performing vapor phase growth. A single crystal semiconductor is deposited on the exposed single crystal semiconductor substrate and a polycrystalline semiconductor is deposited on the insulating film by a method, and the surface of the deposited layer is ground and polished, and the peripheral edge of the semiconductor substrate is scraped off. Alternatively, after removal by punching, a support is attached to the surface of the deposited layer, and finally the single crystal semiconductor substrate is ground and polished from the surface opposite to the surface having the separation groove.

In addition, the present invention forms an insulating film on the surface of a single crystal semiconductor substrate having a diameter larger than a standard diameter and a separation groove, and removes the insulating film in a certain range from the periphery of the substrate to form a single crystal semiconductor substrate. Then, by vapor phase growth, a single crystal semiconductor is deposited on the exposed single crystal semiconductor substrate, and a polycrystalline semiconductor is deposited on the insulating film, and the surface of the deposited layer is ground and polished. , pasting a support with a diameter larger than the standard diameter on the surface of the deposited layer, further scraping off the peripheral edges of the semiconductor substrate and the support, and finally removing the single crystal semiconductor substrate from the surface opposite to the surface having the separation groove. It means grinding and polishing.

Furthermore, the present invention forms an insulating film on the surface of a single crystal semiconductor substrate having a separation groove, then deposits a polycrystalline semiconductor on the insulating film by vapor phase growth, and further grinds the surface of the deposited layer.・After polishing and removing the peripheral edge of the semiconductor substrate by scraping or punching, attaching a support to the surface of the deposited layer, and finally grinding the single crystal semiconductor substrate from the surface opposite to the surface having the separation groove.・It means polishing.

[Function] Comparing the polishing accuracy of single crystal semiconductors and polycrystalline semiconductors in the polishing process, the polishing rate of single crystal semiconductors is smaller than the polishing rate of polycrystalline semiconductors, so it is possible to suppress the polishing variation for single crystal semiconductors. It is possible to prevent polishing sag from occurring.

Therefore, as described above, when a separation substrate on which a single crystal semiconductor is deposited over a certain area from the periphery of the substrate is bonded to a support, polishing sag may occur on the outer periphery of the substrate during grinding and polishing in the subsequent grinding process. Does not occur.

For this reason, there is no gap at the end of the bonded surface, which prevents wafer contamination due to residual etching solution and the like, and also prevents peeling from the bonded surface.

Furthermore, since the outer peripheral surface of the dielectric isolation substrate is covered with a single crystal semiconductor and the polycrystalline semiconductor is not exposed, it is possible to avoid the generation of foreign substances from the polycrystalline semiconductor during the etching process and diffusion process. At the same time, it is possible to prevent chipping and wafer cracking during dielectric isolation manufacturing and sea urchin fly processing.

Furthermore, by making the diameters of the separation substrate and support body larger than the standard diameter to provide some margin, it is possible to bond the separation substrate and support body together without having to align them very precisely. There are no unbonded parts at the edges of the bonded surfaces, and a highly accurate dielectric separated substrate can be manufactured in a short time.

[Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

(First Embodiment) FIG. 1 is a manufacturing flow of a dielectric isolation substrate showing a first embodiment of the present invention. First, as shown in FIG. 1(a), a V-shaped separation groove 2 with a depth of 50 μm is formed on one main surface of a single crystal 81 substrate 1 by a method such as anisotropic selective etching. 8102 film 1 with a thickness of 1.5 μm as an insulating film on the main surface
3, and 810. on the back. The film 23 is formed by a thermal oxidation method.

Next, as shown in FIG. 6B, the S]○ film 13 on the surface of the single crystal 81 substrate 1 having the separation groove 2 is removed over a certain range from the periphery of the substrate, and the single crystal Si substrate 1 is Expose the surface of 1. Next, the separation groove 2 of the single crystal 81 substrate 1 is
The single crystal 81 substrate 1 was placed in a vapor phase growth reaction apparatus (not shown) with the surface having the surface facing upward and heated to a temperature of 1000'
The same figure (c>
As shown in S10. A polycrystalline Si layer 4 is deposited on the NJj 131, and a single bonded S1 layer 11 is deposited on the exposed surface of the single crystal 81 substrate 1 at the same time. Since the surface of the deposited layer 9 deposited in this way does not maintain flatness, if it is bonded to the single crystal 81 substrate 6 that will serve as a support, the deposited layer 9
The unevenness of the surface deteriorates the adhesion of the bonded surfaces and causes peeling. Therefore, as shown in FIG. 4(d), grinding and polishing are performed to improve the flatness of the surface of the deposited layer 9. That is, 30 to 4 μm of the deposited layer is removed by grinding, and then the single crystal 8 that has been damaged by this grinding is removed.
1 The surface of the substrate 1 after grinding is polished by a mechanical/chemical polishing method to remove the grinding strain remaining inside the single crystal Si substrate 1, and a separation substrate 5 as shown in FIG. 1(e) is manufactured. .

At this time, when the polishing rates of the single crystal S1 layer 11 and the polycrystalline S1 layer 4 are compared, the polishing rate of the single crystal S1 layer 1 is smaller than that of the polycrystalline Si layer 4, so that polishing variations can be suppressed. When we actually compared the polishing sag of the single crystal 81 layer and the polycrystalline S1 layer, we found that the polishing sag of the single crystal S1 layer was 0 to 0.
It was found that the thickness was as low as 1 μm. Therefore, by forming the single crystal S1 layer 11 in a certain range from the periphery of the separation substrate 5, it is possible to prevent the outer periphery polishing sag from occurring.

Note that the surface of the deposited layer 9 of the separation substrate 5 has a monocrystalline Si layer 11 in a certain area from the periphery and a polycrystalline S1 layer 4 in the inner periphery, so that the flatness is not impaired due to the polishing rate. , polishing using mechanical/chemical polishing methods while following the unevenness.

Next, as shown in FIG. 4E, the peripheral edge of the separation substrate 5 is scraped off using a chamfering device to reduce the diameter of the separation substrate 5. At this time, even if minute polishing sag remains at the outermost edge of the surface of the deposited layer 9 of the separation substrate 5, the polishing sag can be completely removed by reducing the diameter with this chamfering device. . In this case, instead of using a chamfering device to scrape off the peripheral edge of the separation substrate 5, a punching device may be used to punch out the peripheral edge of the separation substrate 5.

Next, as shown in FIG. 5(f), after bringing the separation substrate 5 and the single crystal 81 substrate 6, which will serve as a support, into close contact with each other, they are heated and oxidized in an oxidizing atmosphere at 1100° C., and the silicon oxide produced is used to bond them together. By bonding, a bonded substrate 71 is obtained. Here, when bringing the two into close contact, if the diameter of the single crystal 81 substrate 6 is made larger than the standard diameter, unbonded parts may occur at the periphery of the bonded contact surface 51 of the separation substrate 5 due to eccentricity or misalignment. This can be prevented and the positioning time for bonding can be shortened. However, the single crystal 81 substrate 6 serving as the support must have a standard diameter so as not to cause any problems with the photolithography or diffusion equipment in the subsequent process.

When the above-described separation substrate 5 and the single crystal 81 substrate 6 are bonded together without using an adhesive layer, no gap is formed at the extreme end of the bonding surface 51.

Therefore, it is possible to prevent bleeds due to residual etching solution and peeling from the wafer bonding adhesive surface 51 due to local etching. When this separation substrate 5 and single crystal Si substrate 6 are bonded together, the single crystal S1 layer 11 covers and confines the polycrystalline Si layer 4 deposited by vapor phase growth, so the polycrystalline S1 layer 4 is Since the polycrystalline Si layer is not exposed to the surface and does not come in contact with the outside, it is possible to prevent the generation of foreign substances from the polycrystalline Si layer, and also to prevent chipping and wafer cracking during wafer manufacturing.

Finally, the separation substrate 5 is ground and removed by approximately 350 to 400 μm from the surface opposite to the surface having the separation grooves 2.

Further, the surface of the single-crystal Si substrate 1 damaged by this grinding is polished by mechanical/chemical polishing to remove the grinding strain remaining inside the single-crystal 81 substrate 1. In this polishing method, residual grinding strain is removed in the primary polishing, and after the dielectric isolation structure is formed in the secondary polishing, the finishing is performed so that there is no problem even if a device film is formed on the surface of the dielectric isolation structure. Perform tertiary polishing. By the above steps, the same figure (
A dielectric isolation substrate 7 as shown in g) is manufactured.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention. In this embodiment, first, a single crystal 81 substrate 1 having a diameter of 2 to 3 mm larger than the standard diameter and a single crystal 81 substrate 6 having a diameter of 2 to 3 mm larger than the standard diameter are first prepared.

First, as shown in FIG. 2(a), etching is performed to a depth of 50 μm on one main surface of the single crystal S] substrate 1 by a method such as anisotropic selective etching.
After forming the V-shaped isolation groove 2 of m in length, a 1.5 μm thick insulating film 810 and film 13 are formed on the main surface thereof, and a Sin film 23 is formed on the back surface by thermal oxidation. Next, as shown in the same figure (b), $1 on the surface of the single crystal S1 substrate 1
0. The film 13 is removed over a certain range from the periphery of the substrate to dry the surface of the single crystal 81 substrate 1. Then,
This single crystal 81 substrate 1 was placed in a vapor phase growth reaction apparatus with the surface having the separation grooves 2 facing upward, and the temperature was set at 1000°C to 100°C.
A mixed gas of hydrogen and silane dioxide vapor is supplied at 200° C., and the treatment is carried out for about 30 to 40 minutes. As a result, the same figure (C
), there is a polycrystalline S1 layer 4 on the 5102 film 13.
However, on the exposed surface of the single crystal Si substrate 1, there is a single crystal S1.
Layer 11 is deposited simultaneously. Since the surface of the deposited layer 9 is not kept flat, if it is bonded to the single crystal S] substrate 6 that will serve as a support, the unevenness of the surface of the deposited layer 9 will deteriorate the adhesion of the bonded surface. This may cause peeling. Therefore, as shown in the same figure (c), in order to make the surface of the deposited layer 9 flat, grinding and polishing are carried out.The deposited layer 9 is removed by 30 to 40 pm of grinding, and then the grinding damage and grinding strain are removed. In order to remove the deposited layer, the surface of the deposited layer is finished by mechanical/chemical polishing, and the separation substrate 5 is manufactured.

Here, if the peripheral edge of the separation substrate 5 is scraped off using a chamfering device, there is a possibility that the bonded surface of the separation substrate 5 may be contaminated or the bonded surface may be damaged. Therefore, here, there is no difference in the diameters of the separation substrate 5 and the single crystal Si substrate 6 serving as a support, and the separation substrate 5 and the single crystal Si substrate 6 are kept the same diameter, as shown in FIG. After bringing 6 into close contact with
A bonded substrate 71 is obtained by heating and oxidizing the substrate in an oxidizing atmosphere at 1100° C. and bonding them together using Sumi oxide silicon.

In this case, when the two are brought into close contact, the separation substrate 5 and the single crystal 8
Since the substrates 6 have the same diameter, it takes a lot of time to bond them together precisely, and unbonded areas may occur at the periphery of the bonding surface 51 due to eccentricity or misalignment, causing the wafer This may cause peeling, chipping, foreign matter, etc.
This will reduce product yield. Therefore, in this example,
Since the separation substrate 5 and the single crystal 81 substrate 6 are larger than the standard diameter, after bonding them together, the outer peripheral surface of the bonded dielectric separation substrate is chamfered to the standard diameter using a chamfering device or the like. Scrape it off. At this time, even if minute gaps or unbonded parts occur, they can be removed by scraping.

As described above, the bonded substrate 71 has no gaps at the end of the bonded adhesive surface 51 and has good bonding accuracy.
You can get two. Finally, the separation substrate 5 is removed by grinding approximately 350 to 400 μm from the side opposite to the surface having the separation grooves 2, and then the grinding damage and grinding distortion caused by this grinding are removed by mechanical/chemical polishing. By this, a dielectric isolation substrate 7 as shown in FIG.
Manufacture.

Using the manufacturing method described above, the separation groove 2, the single crystal S1 layer 1
1. Dielectric separation was performed by creating samples in which the thickness of the deposited layer 9 and the thickness of the single crystal 81 substrate 1 were variously adjusted by changing the amount of deposited polycrystalline 81 layer 4 and the amount of grinding/polishing M. When the substrate 7 was manufactured, there was no peeling from the bonding surface 51, and a highly accurate dielectric separation substrate 7 could be obtained.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention. First, the third
As shown in Figure (a), after forming a v-type separation groove 2 on one main surface of a single crystal 81 substrate 1 by a method such as anisotropic selective etching, an insulating film 810, a film 13, and a back surface are formed. to 8
102 film 23 is formed by a thermal oxidation method. Next, the same figure (
As shown in b), after depositing a polycrystalline S layer 4 on the insulating film 13 by the vapor phase reaction growth method, as shown in FIG. When polishing is performed, outer periphery polishing sag 52 occurs. Therefore, as shown in FIG. 4D, the outer circumferential surface of the substrate is shaved using a chamfering device so that the outer circumferential polishing sag 52 can be removed, thereby creating a separation substrate 5 having only a flat surface.

In this case, instead of using a chamfering device to scrape off the peripheral edge of the separation substrate 5, a punching device may be used to punch out the peripheral edge of the separation substrate 5.

Next, as shown in FIG. 5(e), the separation substrate 5 and the single crystal 81 substrate 6 serving as a support are bonded together by a thermal oxidation method, and the bonding surface 51 is bonded so that no gap is formed at the extreme end. A laminated substrate 71 is created. At this time, the single crystal 81 substrate 6 serving as the support is made to have a standard diameter so as not to cause any trouble as the sea urchin fly will cause later.

In this way, it is possible to obtain a bonded substrate 71 with no gap at the end of the bonded bonding surface 51 and with good bonding accuracy. Finally, the single crystal 81 substrate 1 is ground by approximately 350 to 400 μm from the surface opposite to the surface having the separation grooves 2. Then, by polishing the surface of the single crystal 81 substrate 1 damaged by this grinding using a mechanical/chemical polishing method, the grinding strain remaining inside the single crystal 81 substrate 1 is removed. A dielectric isolation substrate 7 as shown in Figure (f) is manufactured.

According to this embodiment, since local etching of the polycrystalline S1 layer 4 can be prevented, the bonding strength can be increased and the generation of blemishes and foreign matter can be suppressed.

[Effects of the Invention] As described above, according to the present invention, since no gap is generated at the extreme end of the bonding surfaces, it is possible to prevent bleeds due to residual etching liquid, etc., and to increase the bonding strength.

In addition, by making the diameter of the support and separation substrate larger than the standard diameter, unbonded areas can occur at the periphery of the bonded surfaces even if the support and separation substrate are not precisely positioned. This improves the bonding accuracy and reduces the time required for bonding.

Furthermore, since the polycrystalline semiconductor is not exposed on the side surface of the dielectric isolation substrate, it is possible to prevent the generation of foreign substances from the polycrystalline semiconductor, and since the polycrystalline semiconductor is surrounded by the single crystal semiconductor, external forces It is possible to prevent chipping and cracking from occurring in the dielectric isolation substrate.

[Brief explanation of the drawing]

1 to 3 show the manufacturing procedure of the dielectric isolation substrate of the present invention, FIG. 1 shows the first embodiment, FIG. 2 shows the second embodiment,
3 is an explanatory diagram of the manufacturing procedure showing the third embodiment, FIG. 4 is an explanatory diagram of the manufacturing procedure of a conventional dielectric isolation substrate, and FIG. 5 is an explanatory diagram for explaining the problems of the conventional method. l... Single crystal S'' substrate, 2... Separation groove, 4. Polycrystalline S
1 layer, 5... Separation substrate, 6 - Single crystal 81 substrate serving as a support, 7 - Dielectric separation substrate, 9... Deposition layer, l].
Single crystal Si layer, 13.23 - Insulating film, 51... Adhesive surface, 71... Bonded substrate.

Claims (1)

[Claims] 1. An insulating film is formed on a single crystal semiconductor having an isolation trench, and a polycrystalline semiconductor is deposited on the insulating film, and the polycrystalline semiconductor is deposited in the isolation trench. A dielectric separation substrate comprising a separation substrate from which the single crystal semiconductor is electrically insulated, and a support bonded to a surface of the polycrystalline semiconductor, wherein a peripheral portion of the separation substrate is connected to the single crystal semiconductor. A dielectric isolation substrate characterized by being covered with. 2. The dielectric isolation substrate according to claim 1, wherein the single crystal semiconductor is made of silicon. 3. An insulating film is formed on the surface of a single crystal semiconductor substrate having a separation groove, the insulating film is removed from a certain area from the substrate periphery to expose the single crystal semiconductor substrate, and then the above-mentioned A single crystal semiconductor is deposited on the exposed single crystal semiconductor substrate, and a polycrystalline semiconductor is deposited on the insulating film, and the surface of the deposited layer is ground and polished, and the peripheral edge of the semiconductor substrate is removed by scraping or punching. After that, a support is attached to the surface of the deposited layer, and finally the single crystal semiconductor substrate is ground and polished from the surface opposite to the surface having the separation groove. 4. The manufacturing method according to claim 3, wherein when removing the peripheral edge of the semiconductor substrate by scraping or punching, scraping or punching is performed so that the semiconductor substrate has a smaller diameter than a standard diameter. Production method. 5. Forming an insulating film on the surface of a single crystal semiconductor substrate having a diameter larger than the standard diameter and having a separation groove, and removing the insulating film from a certain range from the periphery of the substrate to expose the single crystal semiconductor substrate; Next, by vapor phase growth, a single crystal semiconductor is deposited on the exposed single crystal semiconductor substrate and a polycrystalline semiconductor is deposited on the insulating film, and the surface of the deposited layer is ground and
After polishing, a support having a diameter larger than the standard diameter is attached to the surface of the deposited layer, the peripheral edges of the semiconductor substrate and the support are scraped off, and finally the single crystal is removed from the surface opposite to the surface having the separation groove. A method for manufacturing a dielectric isolation substrate, which comprises grinding and polishing a semiconductor substrate. 6. Forming an insulating film on the surface of a single crystal semiconductor substrate having a separation groove, then depositing a polycrystalline semiconductor on the insulating film by vapor phase growth, and further grinding and polishing the surface of the deposited layer. After removing the peripheral edge of the semiconductor substrate by scraping or punching, attaching a support to the surface of the deposited layer, and finally grinding and polishing the single crystal semiconductor substrate from the surface opposite to the surface having the separation groove. A method for manufacturing a dielectric isolation substrate characterized by: 7. The manufacturing method according to claim 6, wherein when removing the peripheral portion of the semiconductor substrate by scraping or punching, scraping or punching is performed so that the semiconductor substrate has a smaller diameter than a standard diameter. Production method.